DS07-16306-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-bit Proprietary Microcontrollers

CMOS

FR30 Family MB91150 Series

MB91F155/MB91154

DESCRIPTION

The MB91150 is a single-chip microcontroller using a RISC-CPU (FR 30 series) as its core. It contains peripheral
I/O resources suitable for audio, MD and so on which are required to operate at low power consumption.

FEATURES

CPU

· 32-bit RISC (FR30) , load/store architecture, 5-stage pipeline
· General-purpose registers: 32 bits

· 16-bit fixed-length instructions (basic instructions) , 1 instruction/ 1 cycle
· Memory-to-memory transfer, bit processing, barrel shift processing : Optimized for embedded applications
· Function entrance/exit instructions, and multiple load/store instructions of register contents, instruction systems

supporting high level languages

· Register interlock functions, efficient assembly language description
· Branch instructions with delay slots : Reduced overhead time in branching executions
· Internal multiplier/supported at instruction level

Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles

· Interrupt (PC and PS saving) : 6 cycles, 16 priority levels

(Continued)

PACKAGE

144-pin plastic LQFP

(FPT-144P-M08)

MB91F155/MB91154

Bus Interface

· 16-bit address output, 8/16-bit data input and output
· Basic bus cycle : 2-clock cycle
· Support for interface for various types of memory
· Unused data/address pins can be configured us input/output ports
· Support for little endian mode

Internal ROM

MB91F155

FLASH products : 510 Kbytes

MB91154

Mask product : 384 Kbytes

Internal RAM

Mask, FLASH products : 2 Kbytes

Internal Backup RAM

MB91F155

FLASH products : 32 Kbytes

MB91154

Mask product : 20 Kbytes

More power can be saved by entering backup mode and then applying power supply current only to the backup
RAM.

DMAC

DMAC in descriptor format for placing transfer parameters on to the main memory.
Capable of transferring a maximum of eight internal and external factors combined.
Three channels for external factors

Bit Search Module

Searches in one cycle for the position of the bit that changes from the MSB in one word to the initial I/O.

Timers

· 16-bit OCU

8 channels, ICU

4 channels, Free-run timer

1 channel

· 8/16-bit up/down timer/counter (8-bit

2 channels or 16-bit

1 channel)

AIN and BIN share pins with internal interrupts.

· 16-bit PPG timer

6 channels. The output pulse cycle and duty can be varied as desired

· 16-bit reload timer

4 channels

D/A Converter

· 8-bit

3 channels

10. A/D Converter (Sequential Comparison Type)

· 10-bit

8 channels

· Sequential conversion method (conversion time : 5.0

s@33 MHz)

· Single conversion or scan conversion can be selected, and one-shot or continuous or stop conversion mode

can be set respectively.

· Conversion starting function by hardware/software.

(Continued)

MB91F155/MB91154

(Continued)

11. Serial I/O

· UART

4 channels. Any of them is capable of serial transfer in sync with clock attached with the LSB/MSB

switching function.

· Serial data output and serial clock output are selectable by push-pull/open drain software.
· A 16-bit timer (U-timer) is contained as a dedicated baud rate generator allowing any baud rate to be generated.

12. I

C Bus Interface

· One channel master/slave send and receive
· Arbitration and clock synchronization functions

(The product is licensed with the Philips I

C patent to support those customers who intend to use this product

in an I

C system in compliance with the standard I

C specification stipulated by Philips.)

13. Clock Switching Function

· Gear function : Operating clock ratios to the basic clock can be set independently for the CPU and peripherals

from four types, 1 : 1, 1 : 2, 1 : 4 or 1 : 8.

14. Clock Function (Calendar Macro)

· Internal 32 kHz clock function
· Capable of operating in clock mode to run only the clock function while the CPU and peripheral macros are

stopped.

15. Interrupt Controller

External interrupt input (16 channels in total) :
· Allows the rising edge/falling edge/H level/L level to be set.

Internal interrupt factors :
· Interrupt by resources and delay interrupt

16. Others

· Reset cause : Power on reset/watchdog timer/software reset/external reset
· Low power consumption mode : Sleep/stop/clock mode
· Package : LQFP 144-pin
· CMOS technology (0.35

· Power supply voltage : 3.15 V to 3.6 V

MB91F155/MB91154

PIN ASSIGNMENT

(TOP VIEW)

(FPT-144P-M08)

P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23

P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31

P40/A00
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07

P50/A08
P51/A09
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P60/A16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

P61/A17

P62/A18

P63/A19

P64/A20

P65/A21

P66/A22

P67/A23

P80/RDY

P81/BGRNT

P82/BRQ

P83/RD

P84/WR0

P85/WR1

P86/CLK

MD2

MD1

MD0

RST

PC0/INT0

PC1/INT1

PC2/INT2

PC3/INT3

PC4/INT4/CS0

PC5/INT5/CS1

PC6/INT6/CS2

PC7/INT7/CS3

PD0/AIN0/INT8/TRG0

PD1/BIN0/INT9/TRG1

PD2/AIN1/INT10/TRG2

PD3/BIN1/INT11/TRG3

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

PH5/SCK1/TO1
PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
PI3/SIN3
PI4/SOT3
PI5/SCK3/TO3
V

PJ0/SCL
PJ1/SDA
V

PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
PF4/FRCK
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0
V

PD7/ATG/INT15
PD6/DEOP2/INT14
PD5/ZIN1/INT13/TRG5
PD4/ZIN0/INT12/TRG4

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

X1A

X0A

BACKUP

PK7/AN7

PK6/AN6

PK5/AN5

PK4/AN4

PK3/AN3

PK2/AN2

PK1/AN1

PK0/AN0

AVRL

AVRH

DAVC

DAVS

DA0

DA1

DA2

PL7/DACK2

PL6/DREQ2

PL5/DEOP1

PL4/DACK1

PL3/DREQ1

PL2/DEOP0

PL1/DACK0

PL0/DREQ0

PH0/SIN0

PH1/SOT0

PH2/SCK0/TO0

PH3/SIN1

PH4/SOT1

MB91F155/MB91154

PIN DESCRIPTION

(Continued)

Pin No.

Pin name

Circuit

type

Function

1
2
3
4
5
6
7
8

D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27

Bit 16 to bit 23 of external data bus
These pins are enabled only in 16-bit external bus mode.
These pins are available as ports in single-chip and 8-bit external bus
modes.

10
11
12
13
14
15
16
17

D24/P30
D25/P31
D26/P32
D27/P33

D28P34

D29/P35
D30/P36
D31/P37

Bit 24 to bit 31 of external data bus
These pins are available as ports in single-chip mode.

18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35

A00/P40
A01/P41
A02/P42
A03/P43
A04/P44
A05/P45
A06/P46
A07/P47
A08/P50
A09/P51
A10/P52
A11/P53
A12/P54
A13/P55
A14/P56
A15/P57

Bit 0 to bit 15 of external address bus
These pins are enabled in external bus mode.
These pins are available as ports in single-chip mode.

36
37
38
39
40
41
42
43

A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67

Bit 16 to bit 23 of external address bus
These pins are available as ports when the address bus is not in use.

RDY/P80

External RDY input
This function is enabled when external RDY input is allowed.
Input "0" when the bus cycle being executed does not end.
This pin is available as a port when external RDY input is not in use.

MB91F155/MB91154

(Continued)

Pin No.

Pin name

Circuit

type

Function

BGRNT/P81

External bus release acceptance output
This function is enabled when external bus release acceptance output is
allowed.
Output "L" upon releasing of the external bus.
This pin is available as a port when external bus release acceptance out-
put is not allowed.

BRQ/P82

External bus release request input
This function is enabled when external bus release request input is al-
lowed.
Input "1" when the release of the external bus is desired.
This pin is available as a port when external bus release request input is
not in use.

RD/P83

External bus read strobe output
This function is enabled when external bus read strobe output is allowed.
This pin is available as a port when external bus read strobe output is not
allowed.

WR0/P84

External bus write strobe output
This function is enabled in external bus mode.
This pin is available as a port in single chip mode.

WR1/P85

External bus write strobe output
This function is enabled in external bus mode when the bus width is 16
bits.
This pin is available as a port in single chip mode or when the external bus
width is 8 bits.

CLK/P86

System clock output
The pin outputs the same clock as the external bus operating frequency.
The pin is available as a port when it is not used to output the clock.

52
53
54

MD2
MD1
MD0

Mode pins
To use these pins, connect them directly to either Vcc or Vss.
Use these pins to set the basic MCU operating mode.

RST

External reset input

57
58

X1
X0

High-speed clock oscillation pins (16.5 MHz)

60
61
62
63

INT0/PC0
INT1/PC1
INT2/PC2
INT3/PC3

External interrupt request input 0-3
Since this input is used more or less continuously when the corresponding
external interrupt is allowed, output by the port needs to be stopped ex-
cept when it is performed deliberately.
Since this port is allowed to input also in standby mode, it can be used to
reset the standby state.
These pins are available as ports when external interrupt request input is
not in use.

MB91F155/MB91154

(Continued)

Pin No.

Pin name

Circuit

type

Function

64
65
66
67

INT4/PC4/CS0
INT5/PC5/CS1
INT6/PC6/CS2
INT7/PC7/CS3

These pins also serve as the chip select output and external inter-
rupt request input 4-7.
When the chip select output is not allowed, these pins are available
as external interrupt requests or ports.
Since this input is used more or less continuously when the corre-
sponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
Since this port is also allowed to input in standby mode, the port can
be used to reset the standby state.
These pins are available as ports when external interrupt request
input and chip select output are not in use.

69
70
71
72
73
74

PD0/AIN0/INT8/TRG0
PD1/BIN0/INT9/TRG1

PD2/AIN1/INT10/TRG2
PD3/BIN1/INT11/TRG3

PD4/ZIN0/INT12/TRG4
PD5/ZIN1/INT13/TRG5

External interrupt request input 8-13
Since this input is used more or less continuously when the corre-
sponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
[AIN, BIN] Up/down timer input.
[TRG] PPG external trigger input.
Since this input is used more or less continuously while input is al-
lowed, output by the port needs to be stopped except when it is per-
formed deliberately.
These pins are available as ports when the external interrupt re-
quest input, up timer counter input, and PPG external trigger input
are not in use.

PD6/DEOP2/INT14

External interrupt request input 14
Since this input is used more or less continuously when the corre-
sponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
[DEOP2] DMA external transfer end output.
This function is enabled when DMAC external transfer end output
is allowed.
This pin is available as a port when it is not in use as the external
interrupt request input or DMA external transfer end output.

PD7/ATG/INT15

External interrupt request input 15
Since this input is used more or less continuously when the corre-
sponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
[ATG] A/D converter external trigger input.
Since this input is used more or less continuously when selected as
an A/D activation factor, output by the port needs to be stopped ex-
cept when it is performed deliberately.
This pin is available as a port when it is not in use as the external
interrupt request input or A/D converter external trigger input.

MB91F155/MB91154

(Continued)

Pin No.

Pin name

Circuit

type

Function

78
79
80
81
82
83
84
85

PE0/OC0
PE1/OC1
PE2/OC2
PE3/OC3
PE4/OC4
PE5/OC5
PE6/OC6
PE7/OC7

Output compare output
These pins are available as ports when output compare output is not al-
lowed.

86
87
88
89

PF0/IN0
PF1/IN1
PF2/IN2
PF3/IN3

Input capture input
This function is enabled when the input capture operation is input.
These pins are available as ports when input capture input is not in use.

PF4/FRCK

Free-run timer external clock input pin
This pin is available as a port when free-run timer external clock input is
not in use.

91
92
93
94
95
96

PG0/PPG0
PG1/PPG1
PG2/PPG2
PG3/PPG3
PG4/PPG4
PG5/PPG5

PPG timer output
This function is enabled when PPG timer output is allowed.
These pins are available as ports when PPG timer output is not allowed.

PJ1/SDA

C interface I/O pin

This function is enabled when the I

C interface is allowed to operate.

While the I

C interface is in operation, keep the port output set to Hi-Z.

This pin is available as a port when the I

C interface is not in use.

100

PJ0/SCL

C interface I/O pin

This function is enabled when the I

C interface is allowed to operate.

While the I

C interface is in operation, keep the port output set to Hi-Z.

This pin is available as a port when the I

C interface is not in use.

102

PI5/SCK3/TO3

UART3 clock I/O, Reload timer 3 output
When UART3 clock output is not allowed, reload timer 3 can be output by
allowing it.
This pin is available as a port when neither UART3 clock output nor reload
timer output is allowed.

103

PI4/SOT3

UART3 data output
This function is enabled when UART3 data output is allowed.
This pin is available as a port when UART3 clock output is not allowed.

104

PI3/SIN3

UART3 data input
Since this input is used more or less continuously while UART3 is en-
gaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
This pin is available as a port when UART3 output data input is not in use.

MB91F155/MB91154

(Continued)

Pin No.

Pin name

Circuit

type

Function

105

PI2/SCK2/TO2

UART2 clock I/O, Reload timer 2 output
When UART2 clock output is not allowed, reload timer 2 can be output by
allowing it.
This pin is available as a port when neither UART2 clock output nor reload
timer output is allowed.

106

PI1/SOT2

UART2 data output
This function is enabled when UART2 data output is allowed.
This pin is available as a port when UART2 clock output is not allowed.

107

PI0/SIN2

UART2 data input
Since this input is used more or less continuously while UART2 is en-
gaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
This pin is available as a port when UART2 data input is not in use.

108

PH5/SCK1/TO1

UART1 clock I/O, Reload timer 1 output
When UART1 clock output is not allowed, reload timer 1 can be output by
allowing it.
This pin is available as a port when neither UART1 clock output nor reload
timer output is allowed.

109

PH4/SOT1

UART1 data output
This function is enabled when UART1 data output is allowed.
This pin is available as a port when UART1 clock output is not allowed.

110

PH3/SIN1

UART1 data input
Since this input is used more or less continuously while UART1 is en-
gaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
This pin is available as a port when UART1 data input is not in use.

111

PH2/SCK0/TO0

UART0 clock I/O, Reload timer 0 output
When UART0 clock output is not allowed, reload timer 0 can be output by
allowing it.
This pin is available as a port when neither UART0 clock output nor reload
timer output is allowed.

112

PH1/SOT0

UART0 data output
This function is enabled when UART0 data output is allowed.
This pin is available as a port when UART0 clock output is not allowed.

113

PH0/SIN0

UART0 data input
Since this input is used more or less continuously while UART0 is en-
gaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
This pin is available as a port when UART0 data input is not in use.

114

DREQ0/PL0

DMA external transfer request input
Since this input is used more or less continuously when selected as a
DMAC transfer factor, output by the port needs to be stopped except when
it is performed deliberately.
This pin is available as a port when DMA external transfer request input is
not in use.

MB91F155/MB91154

(Continued)

Pin No.

Pin name

Circuit

type

Function

115

DACK0/PL1

DMA external transfer request acceptance output
This function is enabled when the DMAC external transfer request accep-
tance is allowed to be output.
This pin is available as a port when the DMAC transfer request accep-
tance is not allowed to be output.

116

DEOP0/PL2

DMA external transfer end output
This function is enabled when the end of DMAC external transfer is al-
lowed to be output.

117

DREQ1/PL3

118

DACK1/PL4

DMA external transfer request acceptance output
This function is enabled when the DMAC external transfer request accep-
tance is allowed to be output.
This pin is available as a port when DMAC transfer request acceptance
output is not allowed.

119

DEOP1/PL5

DMA external transfer end output
This function is enabled when the end of DMAC external transfer is al-
lowed to be output.

120

DREQ2/PL6

121

DACK2/PL7

DMA external transfer request acceptance output
This function is enabled when the DMAC external transfer request accep-
tance is allowed to be output.
This pin is available as a port when DMAC transfer request acceptance
output is not allowed.

123
124
125

DA2
DA1
DA0

D/A converter output
This function is enabled when D/A converter output is allowed.

126

DAVS

Power supply pin for the D/A converter

127

DAVC

Power supply pin for the D/A converter

128

Vcc power supply for the A/D converter

129

AVRH

A/D converter reference voltage (high potential side)
Be sure to turn on/off this pin with potential higher than AVRH applied to
Vcc.

130

AVRL

A/D converter reference voltage (low potential side)

131

Vss power supply for the A/D converter

MB91F155/MB91154

(Continued)

Note : On the majority of pins listed above, the I/O port and the resource I/O are multiplexed, such as XXXX/Pxx.

When the port and the resource output compete against each other on these pins, priority is given to the
resource.

Pin No.

Pin name

Circuit

type

Function

132
133
134
135
136
137
138
139

AN0/PK0
AN1/PK1
AN2/PK2
AN3/PK3
AN4/PK4
AN5/PK5
AN6/PK6
AN7/PK7

A/D converter analog input
These pins are enabled when the AIC register is designated for analog
input.
These pins are available as ports when A/D converter analog input is
not in use.

140

Backup power supply pin

141

BACKUP

Backup circuit protection signal input

142
143

X0A
X1A

Low-speed clock (32 kHz) oscillation pin

27, 56, 68,

77, 97, 122

Power supply pin (V

) for digital circuit

Always power supply pin (V

) must be connected to the power

supply

9, 26, 44,

59, 98,

101, 144

Earth level (V

) for digital circuit

Always power supply pin (V

) must be connected to the power

supply

MB91F155/MB91154

I/O CIRCUIT TYPE

(Continued)

Type

Circuit

Remarks

· High-speed oscillation circuit

(16.5 MHz)
Oscillation feedback resistor

approx. 1 M

· CMOS hysteresis input pin

CMOS hysteresis input
(standby control not attached)
Pullup resistor

· CMOS level I/O pin

CMOS level output
CMOS level input
(attached with standby control)

4 mA

· CMOS hysteresis I/O pin

CMOS level output
CMOS hysteresis input
(attached with standby control)

4 mA

Xout

Digital input

Pout

Nout

CMOS input

Standby control

Pout

Nout

Hysteresis input

Standby control

MB91F155/MB91154

(Continued)

Type

Circuit

Remarks

· CMOS level input pin

CMOS level input
(standby control not attached)

· CMOS hysteresis I/O pin with pul-

lup control
CMOS level output
CMOS level input
(standby control not attached)
Pullup resistance

approx. 50 k

(Typ.)

4 mA

· Clock oscillation circuit (32 kHz)

· Analog/CMOS level I/O pin.

CMOS level output
CMOS level input
(attached with standby control)
Analog input (Analog input is en-
abled when AIC's corresponding
bit is set to "1.")

4 mA

Digital input

Pout

Pullup control

Hysteresis input

Nout

X1A

X0A

Xout

Pout

Nout

CMOS input

Standby control

Analog input

MB91F155/MB91154

(Continued)

Type

Circuit

Remarks

· CMOS hysteresis I/O pin

with pullup control
CMOS level output
CMOS hysteresis input
(attached with standby control)
Pullup resistance

approx. 50 k

(Typ.)

4 mA

· CMOS hysteresis I/O pin

with pullup control.
CMOS level output
(attached with open drain control)
CMOS hysteresis input
(attached with standby control)
Pullup resistance

approx. 50 k

(Typ.)

4 mA

· Open drain I/O pin
· 5 V tolerance of voltage
· CMOS hysteresis input

(attached with standby control)

15 mA

Pout

Pullup control

Hysteresis input

Standby control

Nout

Pullup control

Open drain control

Hysteresis input

Standby control

Nout

Hysteresis input

Standby control

MB91F155/MB91154

HANDLING DEVICES

Preventing Latchup

In CMOS ICs, applying voltage higher than V

or lower than V

to input/output pin or applying voltage over

rating across V

and V

may cause latchup.

This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.

Treatment of Pins

· Treatment of unused pins

Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.

· Treatment of open pins

Be sure to use open pins in open state.

· Treatment of output pins

Shortcircuiting an output pin with the power supply or with another output pin or connecting a large-capacity
load may causes a flow of large current. If this conditions continues for a lengthy period of time, the device
deteriorates. Take great care not to exceed the absolute maximum ratings.

· Mode pins (MD0-MD2)

These pins should be used directly connected to either V

or V

. In order to prevent noise from causing

accidental entry into test mode, keep the pattern length as short as possible between each mode pin and V

or V

on the board and connect them with low impedance.

· Power supply pins

When there are several V

and V

pins, each of them is equipotentially connected to its counterpart inside

of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions,
to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and
to observe the total output current standard, connect all V

and V

pins to the power supply or GND.

It is preferred to connect V

and V

of MB91F15

/MB9115

to power supply with minimal impedance possible.

It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1

F between V

and V

at a position as close as possible to MB91F155/MB91154.

· Crystal oscillator circuit

Noises around X0, X1, X0A, and X1A pins may cause malfunctions of MB91F155/MB91154. In designing the
PC board, layout X0, X1 (X0A, X1A) and crystal oscillator (or ceramic oscillator) and bypass capacitor for
grounding as close as possible.

It is strongly recommended to design PC board so that X0, X1, X0A, and X1A pins are surrounded by grounding
area for stable operation.
The MB91F155 and MB91154 devices do not contain a feedback resistor. To use the clock function, you need
to connect an external resistor.

Precautions

· External Reset Input

It takes at least 5 machine cycle to input "L" level to the RST pin and to ensure inner reset operation properly.

· External Clocks

When using an external clock, normally, a clock of which the phase is opposite to that of X0 must be supplied

X0A

X1A

MB91F155/MB91154

MB91F155/MB91154

to the X0 and X1 pins simultaneously. However, when using the clock along with STOP (oscillation stopped)
mode, the X1 pin stops when "H" is input in STOP mode. To prevent one output from competing against another,
an external resistor of about 1 k

should be provided.

The following figure shows an example usage of an external clock.

Figure 2.1 An example usage of an external clock

Care During Powering Up

· When powering up

When turning on the power supply, never fail to start from setting the RST pin to "L" level. And after the power
supply voltage goes to V

level, at least after ensuring the time for 5 machine cycle, then set to "H" level.

· Source oscillation input

At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing
waiting.

· Power on resetting

When powering up or when turning the power back on after the supply voltage drops below the operation
assurance range, be sure to reset the power.

· Power on sequence (When Vcc2 is connected to Vcc)

Turn on the power in the order of Vcc, AVcc and AVRH. The power should be disconnected in inverse order.

· Even when an AD converter is not in use, connect AVcc to the Vcc level and AVss to the Vss level.
· Even when a DA converter is not in use, connect DAVC to the Vcc level and DAVS to the Vss level.

Powering Up and Backup Mode

This product type has a backup RAM and a Vcc2 power supply dedicated to the calendar macro. With respect
to the Vcc2 and backup pin, adhere to the following :
· When turning on only Vcc2 with Vcc turned off, be sure that the BACK UP pin is on the "L" level.
· Be sure that the BACK UP pin reaches the "H" level after Vcc is turned on. When Vcc is off, the BACK UP pin

must be on the "L" level.

· When setting the BACK UP pin from the "H" to "L" level, be sure that the CPU is in stop mode.

MB91F155/MB91154

BACK UP

2 ON

OFF

CPU

operation

STOP

mode

Backing up
in progress

Note : Do not turn on Vcc from Vcc2 off state.

MB91F155/MB91154

BLOCK DIAGRAM

FR30 CPU Core

I - Bus

D - Bus

I - Bus

D - Bus

C - Bus

External
Bus CTL

UART 4 ch
UTIMER 4 ch

16 bit
Reload Timer

RAM
2 KB

ROM
510 KB

Clock
Control

Interrupt
Controller

8 bit
Up/Down
Counter

External
Interrupt

2 ch

1 ch

4 ch

16 bit
Free RUN Timer

1 ch

16 bit
Input Capture

4 ch

16 bit
Output Compare

10 bit 8 input
A/D converter

8 bit 3 output
D/A converter

C Interface

8 ch

16 bit PPG

6 ch

16 ch

Calendar

Backup RAM

DMAC 8 ch

Bit Search

32 KB

D - Bus

R - Bus

O
R

( )

O
R

( )

O
R

T
6

O
R

T
3

M
O

D
E

( )

(
)

O
R

7( )

O
R

( )

PD7/INT15/ATG (I)
PD6/INT14/DEOP2
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1
PD2/INT10/AIN1
PD1/INT9/BIN0 (I)
PD0/INT8/AIN0 (I)
PC7/INT7/CS3
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
PC2/INT2
PC1/INT1
PC0/INT0 (I)

A/D

DMAC

Up/Down

Counter

External

Interrupt

OSC

(2)

OSC

(2)

O
R

D
A

( )

6( )

( )

PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0

PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
PL3/DREQ1
PL2/DEOP0 (O)
PL1/DACK0 (O)
PL0/DREQ0 (I)

P86/CLK (O)
P85/WR1 (O)
P84/WR0
P83/RD (O)
P82/BRQ (I)
P81/BGRNT (O)
P80/RDY (I)

P67/A23 (O)

P60/A16
P57/A15

P50/A8
P47/A7

P40/A0

P37/D31 (IO)

P30/D24
P27/D23

P20/D16

PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0

PF4/FRCK
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0

DA2
DA1
DA0

X0A
X1A

X0 (I)
X1 (I)

PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
PH3/SIN1
PH4/SOT1
PH5/SCK1/TO1

PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
PI3/SIN3
PI4/SOT3
PI5/SCK3/TO3

PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7

PJ0/SCL
PJ1/SDA

UART
TOX:
Reload
Timer

PPG

Free Run
Timer

Input
Capture

Clock

DMAC

Bus
Control

Address

DATA

Output
Compare

A/D

MD1
MD2

RST

(MB91F155)

MD0

BACKUP

MB91F155/MB91154

FR30 CPU Core

I - Bus

D - Bus

I - Bus

D - Bus

C - Bus

External
Bus CTL

UART 4 ch
UTIMER 4 ch

16 bit
Reload Timer

RAM
2 KB

ROM
384 KB

Clock
Control

Interrupt
Controller

8 bit
Up/Down
Counter

External
Interrupt

2 ch

1 ch

4 ch

16 bit
Free RUN Timer

1 ch

16 bit
Input Capture

4 ch

16 bit
Output Compare

10 bit 8 input
A/D converter

8 bit 3 output
D/A converter

C Interface

8 ch

16 bit PPG

6 ch

16 ch

Calendar

Backup RAM

DMAC 8 ch

Bit Search

20 KB

D - Bus

R - Bus

O
R

( )

O
R

( )

O
R

T
6

O
R

T
3

M
O

D
E

( )

(
)

O
R

7( )

O
R

( )

A/D

DMAC

Up/Down

Counter

External

Interrupt

OSC

(2)

OSC

(2)

O
R

D
A

( )

6( )

(

)

( )

PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0

PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
PL3/DREQ1
PL2/DEOP0 (O)
PL1/DACK0 (O)
PL0/DREQ0 (I)

P86/CLK (O)
P85/WR1 (O)
P84/WR0
P83/RD (O)
P82/BRQ (I)
P81/BGRNT (O)
P80/RDY (I)

P67/A23 (O)

P60/A16
P57/A15

P50/A8
P47/A7

P40/A0

P37/D31 (IO)

P30/D24
P27/D23

P20/D16

PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0

PF4/FRCK
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0

DA2
DA1
DA0

X0A
X1A

X0 (I)
X1 (I)

PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
PH3/SIN1
PH4/SOT1
PH5/SCK1/TO1

PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
PI3/SIN3
PI4/SOT3
PI5/SCK3/TO3

PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7

PJ0/SCL
PJ1/SDA

UART
TOX:
Reload
Timer

PPG

Free Run
Timer

Input
Capture

Clock

DMAC

Bus
Control

Address

DATA

Output
Compare

A/D

MD1
MD2

RST

(MB91154)

MD0

BACKUP

MB91F155/MB91154

CPU CORE

Memory Space

The FR family has a logical address space of 4 Gbytes (2

bytes) and the CPU linearly accesses the memory

space.

· Direct addressing area

The following area in the address space is used for I/O.
This area is called direct addressing area and an operand address can be specified directly in an instruction.
The direct addressing area varies with the data size to be accessed as follows :

Memory Map

byte data access :

0-0FF

half word data access : 0-1FF

word data access :

0-3FF

· MB91F155 memory space

Note : External areas are not accessible in single-chip mode.

0000 0000

0000 0400

0000 0800

0000 1000

0000 9000

0001 0000

01FF FFFF

FFFF FFFF

0001 0000

Direct
addressing
area

I/O map reference

0008 0000

0008 0800

0010 0000

FFFF FFFF

I/O

External ROM-

external bus mode

Internal ROM-

external bus mode

Single-chip mode

I/O

Not accessible

32 KB

internal RAM

32 KB

internal RAM

32 KB

internal RAM

Not accessible

External area

Not accessible

External area

Not accessible

2 KB internal RAM

510 KB

internal ROM

510 KB

internal ROM

External area

Not accessible

MB91F155/MB91154

· MB91154 Memory Space

Note : External areas are not accessible in single-chip mode.

0000 0000

0000 0400

0000 0800

0000 1000

0000 6000

0001 0000

01FF FFFF

FFFF FFFF

0001 0000

Direct
addressing
area

I/O map references

0008 0000

0008 0800

000A 0000

0010 0000

FFFF FFFF

I/O

External ROM-

external bus mode

Internal ROM-

external bus mode

Single-chip mode

I/O

Not accessible

External area

Not accessible

External area

Not accessible

384 KB

internal ROM

384 KB

internal ROM

External area

Not accessible

2 KB internal RAM

20 KB

internal RAM

20 KB

internal RAM

20 KB

internal RAM

MB91F155/MB91154

Registers

The family of FR microcontrollers has two types of registers : the registers residing in the CPU which are dedicated
to applications and the general-purpose registers residing in the memory.

· Dedicated registers :

· Program status (PS)

The PS register holds program status and is further divided into three registers which are a Condition Code
Register (CCR) , a System condition Code Register (SCR) , and an Interrupt Level Mask register (ILM) .

Program counter (PC)

: A 32-bit register to indicate the location where an instructions is stored.

Program status (PS)

: A 32-bit register to store a register pointer or a condition code.

Tablebase register (TBR)

: Holds the vector table lead address used when EIT (exceptions/interrupt/

trap) is processed.

Return pointer (RP)

: Holds the address to return from a subroutine to.

System stack pointer (SSP) : Points to the system stack space.

User stack pointer (USP)

: Points to the user stack space.

Multiplication and division result register (MDH/MDL) : A 32-bit multiplication and division register.

TBR

SSP

USP

MDH

MDL

Program counter

Program status

Tablebase register

Return pointer

System stack pointer

User stack pointer

Multiplication and division register

(Undefined)

XXXX XXXX

0000 0000

000F FC00

32 bit

Initial value

ILM4 ILM3 ILM2

ILM

SCR

CCR

ILM1 ILM0

MB91F155/MB91154

· Condition Code Register (CCR)

· System condition Code Register (SCR)

· Interrupt Level Mask register (ILM)

S flag

: Designates the stack pointer for use as R15.

I flag

: Controls enabling and disabling of user interrupt requests.

N flag

: Indicates the sign when arithmetic operation results are considered to be an integer represented

by 2's complement.

Z flag

: Indicates if arithmetic results were "0."

V flag

: Considers the operand used for an arithmetic operation to be an integer represented by 2's com-

plement and indicates if the operation resulted in an overflow.

C flag

: Indicates whether or not an arithmetic operation resulted in a carry or a borrow from the most sig-

nificant bit.

T flag

: Designates whether or not to enable step trace trap.

ILM4 to ILM0

: Holds an interrupt level mask value to be used for level masking.

An interrupt request is accepted only if the corresponding interrupt level among interrupt
requests input to the CPU is higher than the value indicated by the ILM register.

ILM4

ILM3

ILM2

ILM1

ILM0

Interrupt level

High-Low

Higher

Lower

MB91F155/MB91154

GENERAL-PURPOSE REGISTERS

General-purpose registers are CPU registers R0 through R15 and used as accumulators during various oper-
ations and as memory access pointers (fields indicating addresses) .

Of the 16 general-purpose registers, the following registers are assumed for specific applications. For this reason,
some instructions are enhanced.

R13 : Virtual accumulator (AC)
R14 : Frame pointer (FP)
R15 : Stack pointer (SP)

Initial values to which R0 through R14 are reset are not defined. The initial value of R15 is 0000 0000

(the SSP

value) .

· Register Bank Configuration

R12

R13

R14

R15

AC (Accumulator)

FP (Frame Pointer)

SP (Stack Pointer)

XXXX XXXX

Initial value

XXXX XXXX

0000 0000

32 bit

MB91F155/MB91154

SETTING MODE

Mode Pins

As shown in Table 1 three pins, MD2, 1, and 0 are used to indicate an operation.

Table 1 Mode pins and set modes

Mode Data

The data which the CPU writes to "0000 07FF

" after reset is called mode data.

It is the mode register (MODR) that exists at "0000 07FF

." Once a mode is set in this register, operations will

take place in that mode. The mode register can be written only once after reset.
The mode specified in the register is enabled immediately after it is written.

[bits 7 and 6] : M1, M0

These are bus mode setting bits. Specify the bus mode to be set to after writing to the mode register.

[bits 5 to 0] :

These bits are reserved for the system.

Mode pin

Mode name

Reset vector

access area

External data

bus width

MD2

MD1

MD0

External vector mode 0

External

8 bits

External ROM bus mode

External vector mode 1

External

16 bits

External vector mode 2

External

32 bits

Not available on this
product type

External vector mode

Internal

(Mode register) Single-chip mode

Not available

Function

Remarks

Single-chip mode

Internal ROM-external bus mode

External ROM-external bus mode

Setting not allowed

"0" should be written to these bits at all times.

MODR

Initial value Access

Address : 0000 07FF

XXXXXXXX

W: Write only, X: Undefined

Bus mode setting bits

MB91F155/MB91154

[Precautions When Writing to the MODR]

Before writing to the MODR, be sure to set AMD0 through 5 and determine the bus width in each CS (Chip
Select) area.
The MODR does not have bus width setting bits.
The bus width value set with mode pins MD2 through 0 is enabled before writing to the MODR and the bus width
value set with BW1 and 0 of AMD0 through 5 is enabled after writing to the MODR.
For example, the external reset vector is normally executed with area 0 (the area where CS0 is active) and the
bus width at that time is determined by pins MD 2 through 0. Suppose that the bus width is set to 32 or 16 bits
in MD2 though 0 but no value is specified in AMD 0. If the MODR is written in this state, area 0 then switches
to 8-bit bus mode and operates the bus since the initial bus width in AMD0 is set to 8 bits. This causes a
malfunction.

In order to prevent this type of problem, AMD0 through 5 must always be set before writing to the MODR.

Writing to the MODR.

AMD0 to AMD5 BW1, 0

Designated bus width : MD2,1,0

RST (Reset)

MB91F155/MB91154

I/O MAP

(Continued)

Address

Register

Block

000000

PDR3 (R/W)

XXXXXXXX

PDR2 (R/W)

XXXXXXXX

Port Data Register

000004

PDR6 (R/W)

XXXXXXXX

PDR5 (R/W)

XXXXXXXX

PDR4 (R/W)

XXXXXXXX

000008

PDR8 (R/W)

- XXXXXXX

00000C

000010

PDRF (R/W)

- - - XXXXX

PDRE (R/W)

XXXXXXXX

PDRD (R/W)

XXXXXXXX

PDRC (R/W)

XXXXXXXX

000014

PDRJ (R/W)

- - - - - - 11

PDRI (R/W)

- - XXXXXX

PDRH (R/W)

- - XXXXXX

PDRG (R/W)

- - XXXXXX

000018

PDRL (R/W)

XXXXXXXX

PDRK (R/W)

XXXXXXXX

00001C

SSR0 (R, R/W)

00001000

SIDR0/SODR0

(R, W)

XXXXXXXX

SCR0 (R/W, W)

00000100

SMR0 (R/W)

00000 - 00

UART0

000020

SSR1 (R, R/W)

00001000

SIDR1/SODR1

(R, W)

XXXXXXXX

SCR1 (R/W, W)

00000100

SMR1 (R/W)

00000 - 00

UART1

000024

SSR2 (R, R/W)

00001000

SIDR2/SODR2

(R, W)

XXXXXXXX

SCR2 (R/W, W)

00000100

SMR2 (R/W)

00000 - 00

UART2

000028

SSR3 (R, R/W)

00001000

SIDR3/SODR3

(R, W)

XXXXXXXX

SCR3 (R/W, W)

00000100

SMR3 (R/W)

00000 - 00

UART3

00002C

TMRLR0 (W)

XXXXXXXX XXXXXXXX

TMR0 (R)

XXXXXXXX XXXXXXXX

Reload Timer 0

000030

TMCSR0 (R/W)

- - - - 0000 00000000

000034

TMRLR1 (W)

XXXXXXXX XXXXXXXX

TMR1 (R)

XXXXXXXX XXXXXXXX

Reload Timer 1

000038

TMCSR1 (R/W)

- - - - 0000 00000000

00003C

TMRLR2 (W)

XXXXXXXX XXXXXXXX

TMR2 (R)

XXXXXXXX XXXXXXXX

Reload Timer 2

000040

TMCSR2 (R/W)

- - - - 0000 00000000

MB91F155/MB91154

(Continued)

Address

Register

Block

000044

TMRLR3 (W)

XXXXXXXX XXXXXXXX

TMR3 (R)

XXXXXXXX XXXXXXXX

Reload Timer 3

000048

TMCSR3 (R/W)

- - - - 0000 00000000

00004C

CDCR1 (R/W)

0 - - - 0000

CDCR0 (R/W)

0 - - - 0000

Communications

prescaler 1

000050

CDCR3 (R/W)

0 - - - 0000

CDCR2 (R/W)

0 - - - 0000

000054

000058

Reserved

00005C

RCR1 (W)

00000000

RCR0 (W)

00000000

UDCR1 (R)

00000000

UDCR0 (R)

00000000

8/16 bit U/D Counter

000060

CCRH0 (R/W)

00000000

CCRL0 (R/W, W)

- 000X000

CSR0 (R/W, R)

00000000

000064

CCRH1 (R/W)

- 0000000

CCRL1 (R/W, W)

- 000X000

CSR1 (R/W, R)

00000000

000068

IPCP1 (R)

XXXXXXXX XXXXXXXX

IPCP0 (R)

XXXXXXXX XXXXXXXX

16 bit ICU

00006C

IPCP3 (R)

XXXXXXXX XXXXXXXX

IPCP2 (R)

XXXXXXXX XXXXXXXX

000070

ICS23 (R/W)

00000000

ICS01 (R/W)

00000000

000074

OCCP1 (R/W)

XXXXXXXX XXXXXXXX

OCCP0 (R/W)

XXXXXXXX XXXXXXXX

16 bit OCU

000078

OCCP3 (R/W)

XXXXXXXX XXXXXXXX

OCCP2 (R/W)

XXXXXXXX XXXXXXXX

00007C

OCCP5 (R/W)

XXXXXXXX XXXXXXXX

OCCP4 (R/W)

XXXXXXXX XXXXXXXX

000080

OCCP7 (R/W)

XXXXXXXX XXXXXXXX

OCCP6 (R/W)

XXXXXXXX XXXXXXXX

000084

OCS2, 3 (R/W)

XXX00000 0000XX00

OCS0, 1 (R/W)

XXX00000 0000XX00

000088

OCS6, 7 (R/W)

XXX00000 0000XX00

OCS4, 5 (R/W)

XXX00000 0000XX00

00008C

TCDT (R/W)

00000000 00000000

TCCS (R/W)

0 - - - - - - - 00000000

16 bit Freerun Timer

000090

STPR0 (R/W)

0000 - - - -

STPR1 (R/W)

00000000

STPR2 (R/W)

000000 - -

Stop Register 0, 1, 2

000094

GCN1 (R/W)

00110010 00010000

GCN2 (R/W)

00000000

PPG ctl

MB91F155/MB91154

(Continued)

Address

Register

Block

000098

PTMR0 (R)

11111111 11111111

PCSR0 (W)

XXXXXXXX XXXXXXXX

PPG0

00009C

PDUT0 (W)

XXXXXXXX XXXXXXXX

PCNH0 (R/W)

0000000 -

PCNL0 (R/W)

00000000

0000A0

PTMR1 (R)

11111111 11111111

PCSR1 (W)

XXXXXXXX XXXXXXXX

PPG1

0000A4

PDUT1 (W)

XXXXXXXX XXXXXXXX

PCNH1 (R/W)

0000000 -

PCNL1 (R/W)

00000000

0000A8

PTMR2 (R)

11111111 11111111

PCSR2 (W)

XXXXXXXX XXXXXXXX

PPG2

0000AC

PDUT2 (W)

XXXXXXXX XXXXXXXX

PCNH2 (R/W)

0000000 -

PCNL2 (R/W)

00000000

0000B0

PTMR3 (R)

11111111 11111111

PCSR3 (W)

XXXXXXXX XXXXXXXX

PPG3

0000B4

PDUT3 (W)

XXXXXXXX XXXXXXXX

PCNH3 (R/W)

0000000 -

PCNL3 (R/W)

00000000

0000B8

PTMR4 (R)

11111111 11111111

PCSR4 (W)

XXXXXXXX XXXXXXXX

PPG4

0000BC

PDUT4 (W)

XXXXXXXX XXXXXXXX

PCNH4 (R/W)

0000000 -

PCNL4 (R/W)

00000000

0000C0

PTMR5 (R)

11111111 11111111

PCSR5 (W)

XXXXXXXX XXXXXXXX

PPG5

0000C4

PDUT5 (W)

XXXXXXXX XXXXXXXX

PCNH5 (R/W)

0000000 -

PCNL5 (R/W)

00000000

0000C8

EIRR0 (R/W)

00000000

ENIR0 (R/W)

00000000

EIRR1 (R/W)

00000000

ENIR1 (R/W)

00000000

Ext int

0000CC

ELVR0 (R/W)

00000000 00000000

ELVR1 (R/W)

00000000 00000000

0000D0

0000D8

Reserved

0000DC

DACR2 (R/W)

- - - - - - - 0

DACR1 (R/W)

- - - - - - - 0

DACR0 (R/W)

- - - - - - - 0

D/A Converter

0000E0

DADR2 (R/W)

XXXXXXXX

DADR1 (R/W)

XXXXXXXX

DADR0 (R/W)

XXXXXXXX

0000E4

ADCR (R, W)

00101- XX XXXXXXXX

ADCS1 (R/W)

00000000

ADCS0 (R/W)

00000000

A/D Converter

(Sequential type)

0000E8

AICK (R/W)

00000000

Analog Input Control

0000EC

0000F0

Reserved

MB91F155/MB91154

(Continued)

Address

Register

Block

0000F4

PCRI (R/W)

- - 000000

PCRH (R/W)

- - 000000

PCRD (R/W)

00000000

PCRC (R/W)

00000000

Pull Up Control

0000F8

OCRI (R/W)

- - 000000

OCRH (R/W)

- - 000000

Opendrain Control

0000FC

DDRF (R/W)

- - - 00000

DDRE (R/W)

00000000

DDRD (R/W)

00000000

DDRC (R/W)

00000000

Data Direction Reg-

ister

000100

DDRI (R/W)

- 0000000

DDRH (R/W)

- - 000000

DDRG (R/W)

- - 000000

000104

DDRL (R/W)

00000000

DDRK (R/W)

00000000

000108

00011C

Reserved

000120

IBCR (R/W)

00000000

IBSR (R)

00000000

IADR (R/W)
- XXXXXXX

ICCR (R/W)

- - 0XXXXX

C Interface

000124

IDAR (R/W)

XXXXXXXX

000128

0001FC

Reserved

000200

DPDP (R/W)

- - - - - - - - - - - - - - - - - - - - - - - - - 0000000

DMAC

000204

DACSR (R/W)

00000000 00000000 00000000 00000000

000208

DATCR (R/W)

XXXXXXXX XXXX0000 XXXX0000 XXXX0000

00020C

000210

CAC (R/W)

00000000

CA1 (R/W)

- - XXXXXX

CA2 (R/W)

- - XXXXXX

CA3 (R/W)

- - - XXXXX

Calendar

000214

CA4 (R/W)

- - - XXXXX

CA5 (R/W)

- - - - - XXX

CA6 (R/W)

- - - - XXXX

CA7 (R/W)

- XXXXXXX

000218

Reserved

00021C

CAS (R/W)

0 - - - - - - 0

Calendar

000220

0003EC

Reserved

MB91F155/MB91154

(Continued)

Address

Register

Block

0003F0

BSD0 (W)

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search Module

0003E4

BSD1 (R/W)

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8

BSDC (W)

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FC

BSRR (R)

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000400

ICR00 (R/W)

- - - - 1111

ICR01 (R/W)

- - - - 1111

ICR02 (R/W)

- - - - 1111

ICR03 (R/W)

- - - - 1111

Interrupt Control unit

000404

ICR04 (R/W)

- - - - 1111

ICR05 (R/W)

- - - - 1111

ICR06 (R/W)

- - - - 1111

ICR07 (R/W)

- - - - 1111

000408

ICR08 (R/W)

- - - - 1111

ICR09 (R/W)

- - - - 1111

ICR10 (R/W)

- - - - 1111

ICR11 (R/W)

- - - - 1111

00040C

ICR12 (R/W)

- - - - 1111

ICR13 (R/W)

- - - - 1111

ICR14 (R/W)

- - - - 1111

ICR15 (R/W)

- - - - 1111

000410

ICR16 (R/W)

- - - - 1111

ICR17 (R/W)

- - - - 1111

ICR18 (R/W)

- - - - 1111

ICR19 (R/W)

- - - - 1111

000414

ICR20 (R/W)

- - - - 1111

ICR21 (R/W)

- - - - 1111

ICR22 (R/W)

- - - - 1111

ICR23 (R/W)

- - - - 1111

000418

ICR24 (R/W)

- - - - 1111

ICR25 (R/W)

- - - - 1111

ICR26 (R/W)

- - - - 1111

ICR27 (R/W)

- - - - 1111

00041C

ICR28 (R/W)

- - - - 1111

ICR29 (R/W)

- - - - 1111

ICR30 (R/W)

- - - - 1111

ICR31 (R/W)

- - - - 1111

000420

ICR32 (R/W)

- - - - 1111

ICR33 (R/W)

- - - - 1111

ICR34 (R/W)

- - - - 1111

ICR35 (R/W)

- - - - 1111

000424

ICR36 (R/W)

- - - - 1111

ICR37 (R/W)

- - - - 1111

ICR38 (R/W)

- - - - 1111

ICR39 (R/W)

- - - - 1111

000428

ICR40 (R/W)

- - - - 1111

ICR41 (R/W)

- - - - 1111

ICR42 (R/W)

- - - - 1111

ICR43 (R/W)

- - - - 1111

00042C

ICR44 (R/W)

- - - - 1111

ICR45 (R/W)

- - - - 1111

ICR46 (R/W)

- - - - 1111

ICR47 (R/W)

- - - - 1111

000430

DICR (R/W)

- - - - - - - 0

HRCL (R/W)

- - - - 1111

Delay int

000434

00047C

Reserved

000480

RSRR/WTCR

(R, W)

1-XXX-00

STCR (R/W, W)

000111- -

PDRR (R/W)

- - - - 0000

CTBR (W)

XXXXXXXX

Clock Control unit

000484

GCR (R/W, R)

110011-1

WPR (W)

XXXXXXXX

MB91F155/MB91154

(Continued)

Address

Register

Block

000488

PTCR (R/W)

00XX0XXX

PLL Control

00048C

0005FC

Reserved

000600

DDR3 (W)

00000000

DDR2 (W)

00000000

Data Direction

000604

DDR6 (W)

00000000

DDR5 (W)

00000000

DDR4 (W)

00000000

000608

DDR8 (W)

- 0000000

00060C

ASR1 (W)

00000000 00000001

AMR1 (W)

00000000 00000000

T-unit

000610

ASR2 (W)

00000000 00000010

AMR2 (W)

00000000 00000000

000614

ASR3 (W)

00000000 00000011

AMR3 (W)

00000000 00000000

000618

ASR4 (W)

00000000 00000100

AMR4 (W)

00000000 00000000

00061C

ASR5 (W)

00000000 00000101

AMR5 (W)

00000000 00000000

000620

AMD0 (R/W)

- - - 00111

AMD1 (R/W)

0 - - 00000

AMD32 (R/W)

00000000

AMD4 (R/W)

0 - - 00000

000624

AMD5 (R/W)

0 - - 00000

000628

EPCR0 (W)

- - - - 1100 -1- - - - - -

EPCR1 (W)

- - - - - - - - 11111111

00062C

Reserved

000630

PCR6 (R/W)

00000000

Pull Up Control

000634

0007BC

Reserved

0007C0

FLCR (R/W, R)

000X0000

FLASH Control

0007C4

FWTC (R/W, W)

- - - - - 000

0007C8

0007F8

Reserved

MB91F155/MB91154

Note : Do not execute RMW instructions on registers having a write-only bit.

RMW instructions (RMW : Read Modify Write)

Data is undefined in "Reserved" or (

) areas.

( ):

Access

R/W: Read/Write enabled
R:

Read only

Write only

Not in use

Undefined

0007FC

LER (W)

- - - - - 000

MODR (W)

XXXXXXXX

Little Endian Regis-

ter

Mode Register

AND

Rj, @Ri

EOR

Rj, @Ri

ANDH

Rj, @Ri

ORH

Rj, @Ri

EORH

Rj, @Ri

ANDB

Rj, @Ri

ORB

Rj, @Ri

EORB

Rj, @Ri

BANDL #u4, @Ri

BORL #u4, @Ri

BEORL #u4, @Ri

BANDH #u4, @Ri

BORH #u4, @Ri

BEORH #u4, @Ri

Address

Register

Block

MB91F155/MB91154

INTERRUPT FACTORS AND ASSIGNMENT OF INTERRUPT VECTORS AND RESISTERS

(Continued)

Factor

Interrupt No.

Interrupt

level

Offset

Default TBR

address

Decimal

Hex.

Reset

3FC

000FFFFC

Reserved for the system

3F8

000FFFF8

Reserved for the system

3F4

000FFFF4

Reserved for the system

3F0

000FFFF0

Reserved for the system

3EC

000FFFEC

Reserved for the system

3E8

000FFFE8

Reserved for the system

3E4

000FFFE4

Reserved for the system

3E0

000FFFE0

Reserved for the system

3DC

000FFFDC

Reserved for the system

3D8

000FFFD8

Reserved for the system

3D4

000FFFD4

Reserved for the system

3D0

000FFFD0

Reserved for the system

3CC

000FFFCC

Reserved for the system

3C8

000FFFC8

Undefined instruction exception

3C4

000FFFC4

Reserved for the system

3C0

000FFFC0

External interrupt 0

ICR00

3BC

000FFFBC

External interrupt 1

ICR01

3B8

000FFFB8

External interrupt 2

ICR02

3B4

000FFFB4

External interrupt 3

ICR03

3B0

000FFFB0

External interrupt 4

ICR04

3AC

000FFFAC

External interrupt 5

ICR05

3A8

000FFFA8

External interrupt 6

ICR06

3A4

000FFFA4

External interrupt 7

ICR07

3A0

000FFFA0

External interrupts 8 - 15

ICR08

39C

000FFF9C

Reserved for the system

398

000FFF98

UART0 (receiving complete)

ICR10

394

000FFF94

UART1 (receiving complete)

ICR11

390

000FFF90

UART2 (receiving complete)

ICR12

38C

000FFF8C

UART3 (receiving complete)

ICR13

388

000FFF88

Reserved for the system

384

000FFF84

UART0 (sending complete)

ICR15

380

000FFF80

UART1 (sending complete)

ICR16

37C

000FFF7C

UART2 (sending complete)

ICR17

378

000FFF78

MB91F155/MB91154

(Continued)

Factor

Interrupt No.

Interrupt

level

Offset

Default TBR

address

Decimal

Hex.

UART3 (sending complete)

ICR18

374

000FFF74

ICR19

370

000FFF70

DMAC (End, Error)

ICR20

36C

000FFF6C

Reload timer 0

ICR21

368

000FFF68

Reload timer 1

ICR22

364

000FFF64

Reload timer 2

ICR23

360

000FFF60

Reload timer 3

ICR24

35C

000FFF5C

A/D (sequential type)

ICR26

354

000FFF54

PPG0

ICR27

350

000FFF50

PPG1

ICR28

34C

000FFF4C

PPG2

ICR29

348

000FFF48

PPG3

ICR30

344

000FFF44

PPG4

ICR31

340

000FFF40

PPG5

ICR32

33C

000FFF3C

U/Dcounter 0
(compare/underflow, overflow, up-down
inversion)

ICR33

338

000FFF38

U/Dcounter 1
(compare/underflow, overflow, up-down
inversion

ICR34

334

000FFF34

ICU0 (Read)

ICR35

330

000FFF30

ICU1 (Read)

ICR36

32C

000FFF2C

ICU2 (Read)

ICR37

328

000FFF28

ICU3 (Read)

ICR38

324

000FFF24

OCU0 (Match)

ICR39

320

000FFF20

OCU1 (Match)

ICR40

31C

000FFF1C

OCU2 (Match)

ICR41

318

000FFF18

OCU3 (Match)

ICR42

314

000FFF14

OCU4/5 (Match)

ICR43

310

000FFF10

OCU6/7 (Match)

ICR44

30C

000FFF0C

Reserved for the system

308

000FFF08

16-bit free-run timer

ICR46

304

000FFF04

Delay interrupt factor bit

ICR47

300

000FFF00

MB91F155/MB91154

(Continued)

* : REALOS/FR uses 0X40 and 0X41 interrupts for system codes.

Factor

Interrupt No.

Interrupt

level

Offset

Default TBR

address

Decimal

Hex.

Reserved for the system
(used by REALOS*)

2FC

000FFEFC

Reserved for the system
(used by REALOS*)

2F8

000FFEF8

Reserved for the system

2F4

000FFEF4

Reserved for the system

2F0

000FFEF0

Reserved for the system

2EC

000FFEEC

Reserved for the system

2E8

000FFEE8

Reserved for the system

2E4

000FFEE4

Reserved for the system

2E0

000FFEE0

Reserved for the system

2DC

000FFEDC

Reserved for the system

2D8

000FFED8

Reserved for the system

2D4

000FFED4

Reserved for the system

2D0

000FFED0

Reserved for the system

2CC

000FFECC

Reserved for the system

2C8

000FFEC8

Reserved for the system

2C4

000FFEC4

Reserved for the system

2C0

000FFEC0

Used with the INT instruction

80
to

255

50
to

2BC

000

000FFEBC

000FFC00

MB91F155/MB91154

PERIPHERAL RESOURCES

I/O Port

(1) Port Block Diagram

This LSI is available as an I/O port when the resource associated with each pin is set not to use a pin for input/
output.
The pin level is read from the port (PDR) when it is set for input. When the port is set for output, the value in the
data register is read. The same also applies to reload by read modify write.
When switching from input to output, output data is set in the data register beforehand. However, if a read modify
write instruction (such as bit set) is used at that time, keep in mind that it is the input data from the pin that is
read, not the latch value of the data register.

· Basic I/O Port

Figure PORT-1 Basic port block

The I/O port consists of the PDR (Port Data Register) and the DDR (Data Direction Register) .

Notes: AIC controls switching between the resource and port of the analog pin (A/D) .

AICK (Analog Input Control register on port-K)
The register controls whether port K should be used for analog input or as a general-purpose port.

0 : General-purpose port
1 : Analog input (A/D)

In input mode (DDR

"0")

PDR read : Reads the level of the corresponding external pin.

PDR write : Writes the set value to the PDR.

In output mode (DDR

"1")

PDR read : Reads the PDR value.

PDR write : Outputs the PDR value to the corresponding external pin.

Data bus

PDR read

PDR

DDR

PDR : Port Data Register
DDR : Data Direction Register

Resource input

Resource output

Resource output
allowed

MB91F155/MB91154

· I/O Port (attached with a pullup resistor)

Figure PORT-2 Port block attached with a pullup resistor

Notes :

· Pullup resistor control register (PCR) R/W

Controls turning the pullup resistor on/off.

0 : Pullup resistor disabled
1 : Pullup resistor enabled

· In stop mode priority is also given to the setting of the pullup resistor control register.
· This function is not available when a relevant pin is in use as an external bus pin. Do not write "1" to this register.

Data bus

PDR read

PDR

DDR

PCR

PDR : Port Data Register
DDR : Data Direction Register
PCR : Pull-up Control Register

Resource output

Resource input

Resource output
allowed

MB91F155/MB91154

· I/O Port (attached with the open drain output function and a pullup resistor)

Figure PORT-3 Port block attached with the open drain output function and a pullup resistor

Notes :

· Pullup resistor setup register (PCR) R/W

Controls turning the pullup resistor on/off.

0 : Pullup resistor disabled
1 : Pullup resistor enabled

· Open drain control register (ODCR) R/W

Controls open drain in output mode.

0 : Standard output port during output mode
1 : Open-drain output port during output mode

This register has no significance in input mode (output Hi-Z) . Input/output mode is determined by the direction
register (DDR) .

· Priority is also given to the setting of the pullup resistor control register in stop mode.
· When a relevant pin is used as an external bus pin, neither function is available. Do not write "1" to either register.

Data bus

PDR read

Resource input

Resource output

Resource output
allowed

PDR

DDR

ODCR

PCR

PDR
DDR
ODCR
PCR

: Port Data Register
: Data Direction Register
: OpenDrain Control Register
: Pull-up Control Register

MB91F155/MB91154

(2) Register Descriptions

· Port Data Register (PDR)

PDR2 to PDRL are the I/O data registers of the I/O port.
Input/output is controlled with corresponding DDR2 to DDRL.
R/W: Read/Write enabled, X: Undefined,

: Not in use

PDR2

Initial value

Access

Address : 000001

XXXXXXXX

R/W

PDR3

Initial value

Access

Address : 000000

XXXXXXXX

R/W

PDR4

Initial value

Access

Address : 000007

XXXXXXXX

R/W

PDR5

Initial value

Access

Address : 000006

XXXXXXXX

R/W

PDR6

Initial value

Access

Address : 000005

XXXXXXXX

R/W

PDR8

Initial value

Access

Address : 00000B

- XXXXXXX

R/W

PDRC

Initial value

Access

Address : 000013

XXXXXXXX

R/W

PDRD

Initial value

Access

Address : 000012

XXXXXXXX

R/W

PDRE

Initial value

Access

Address : 000011

XXXXXXXX

R/W

PDRF

Initial value

Access

Address : 000010

- - - XXXXX

R/W

PDRG

Initial value

Access

Address : 000017

- - XXXXXX

R/W

PDRH

Initial value

Access

Address : 000016

- - XXXXXX

R/W

PDRI

Initial value

Access

Address : 000015

- - XXXXXX

R/W

PDRJ

Initial value

Access

Address : 000014

- - - - - - 11

R/W

PDRK

Initial value

Access

Address : 00001B

XXXXXXXX

R/W

PDRL

Initial value

Access

Address : 00001A

XXXXXXXX

R/W

P26

P27

P25

P24

P23

P22

P21

P20

P36

P37

P35

P34

P33

P32

P31

P30

P46

P47

P45

P44

P43

P42

P41

P40

P56

P57

P55

P54

P53

P52

P51

P50

P66

P67

P65

P64

P63

P62

P61

P60

P86

P85

P84

P83

P82

P81

P80

PC6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PD6

PD7

PD5

PD4

PD3

PD2

PD1

PD0

PE6

PE7

PE5

PE4

PE3

PE2

PE1

PE0

PF4

PF3

PF2

PF1

PF0

PG5

PG4

PG3

PG2

PG1

PG0

PH5

PH4

PH3

PH2

PH1

PH0

PI5

PI4

PI3

PI2

PI1

PI0

PJ1

PJ0

PK6

PK7

PK5

PK4

PK3

PK2

PK1

PK0

PL6

PL7

PL5

PL4

PL3

PL2

PL1

PL0

MB91F155/MB91154

· Data Direction Register (DDR)

DDR2 to DDRL control the I/O direction of the I/O port by bit.
DDR

0 : Port input

DDR

1 : Port output

Note : DDRI's bit 6 is a test bit. Be sure to write "0" to the bit.

"0" is the value that is read.

R/W: Read/Write enabled, W: Write only,

: Not in use

DDR2

Initial value

Access

Address : 000601

00000000

DDR3

Initial value

Access

Address : 000600

00000000

DDR4

Initial value

Access

Address : 000607

00000000

DDR5

Initial value

Access

Address : 000606

00000000

DDR6

Initial value

Access

Address : 000605

00000000

DDR8

Initial value

Access

Address : 00060B

- 0000000

DDRC

Initial value

Access

Address : 0000FF

00000000

R/W

DDRD

Initial value

Access

Address : 0000FE

00000000

R/W

DDRE

Initial value

Access

Address : 0000FD

00000000

R/W

DDRF

Initial value

Access

Address : 0000FC

- - - 00000

R/W

DDRG

Initial value

Access

Address : 000103

- - 000000

R/W

DDRH

Initial value

Access

Address : 000102

- - 000000

R/W

DDRI

Initial value

Access

Address : 000101

- 0000000

R/W

DDRK

Initial value

Access

Address : 000107

00000000

R/W

DDRL

Initial value

Access

Address : 000106

00000000

R/W

P26

P27

P25

P24

P23

P22

P21

P20

P36

P37

P35

P34

P33

P32

P31

P30

P46

P47

P45

P44

P43

P42

P41

P40

P56

P57

P55

P54

P53

P52

P51

P50

P66

P67

P65

P64

P63

P62

P61

P60

P86

P85

P84

P83

P82

P81

P80

PC6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PD6

PD7

PD5

PD4

PD3

PD2

PD1

PD0

PE6

PE7

PE5

PE4

PE3

PE2

PE1

PE0

PF4

PF3

PF2

PF1

PF0

PG5

PG4

PG3

PG2

PG1

PG0

PH5

PH4

PH3

PH2

PH1

PH0

TEST

PI5

PI4

PI3

PI2

PI1

PI0

PK6

PK7

PK5

PK4

PK3

PK2

PK1

PK0

PL6

PL7

PL5

PL4

PL3

PL2

PL1

PL0

MB91F155/MB91154

· Pull-up Control Register (PCR)

PCR6 to PCRI control the pullup resistor when the corresponding I/O port is in input mode.
PCR

0 : Pullup resistor not available in input mode

PCR

1 : Pullup resistor available in input mode

The register has no significance in output mode (a pullup resistor not available) .

PCR6

Initial value Access

Address : 000631

00000000

R/W

PCRC

Initial value Access

Address : 0000F7

00000000

R/W

PCRD

Initial value Access

Address : 0000F6

00000000

R/W

PCRH

Initial value Access

Address : 0000F5

- - 000000

R/W

PCRI

Initial value Access

Address : 0000F4

- - 000000

R/W

P66

P67

P65

P64

P63

P62

P61

P60

PC6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PD6

PD7

PD5

PD4

PD3

PD2

PD1

PD0

PH5

PH4

PH3

PH2

PH1

PH0

PI5

PI4

PI3

PI2

PI1

PI0

· Open Drain Control Register (ODCR)

OCRH to OCRI control open drain when the corresponding I/O port is in output mode.
OCR

0 : Standard output port during output mode

OCR

1 : Open drain output port during output mode

The register has no significance in input mode (output Hi-z) .

DCRH

Initial value Access

Address : 0000F9

- - 000000

R/W

OCRI

Initial value Access

Address : 0000F8

- - 000000

R/W

PH5

PH4

PH3

PH2

PH1

PH0

PI5

PI4

PI3

PI2

PI1

PI0

· Analog Input Control Register (AICR)

The AICK controls each pin of a corresponding I/O port as follows :
AIC

1 : Port input mode

AIC

0 : Analog input mode

The register is reset to "0."

R/W: Read/Write enabled,

: Not in use

AICK

Initial value Access

Address : 0000EB

00000000

R/W

PK6

PK7

PK5

PK4

PK3

PK2

PK1

PK0

MB91F155/MB91154

DMA Controller (DMAC)

The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.

DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to en-
hanced performance of the system.
· 8 channels
· Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer
· Transfer all through the area
· Max. 65536 of transfer cycles
· Interrupt function right after the transfer
· Selectable for address transfer increase/decrease by the software
· External transfer request input pin, external transfer request accept output pin, external transfer complete

output pin three pins for each

· Block Diagram

DREQ0 to DREQ2

Edge/level

detection circuit

Data buffer

Internal resource
transfer request

DACK0 to DACK2

EOP0 to EOP2

Interrupt request

DPDP

Switcher

Sequencer

DACSR

DATCR

Mode

BLK DEC

INC / DEC

BLK

DMACT

SADR

DADR

Data bus

MB91F155/MB91154

· Registers (DMAC internal registers)

00000200

00000201

00000202

00000203

00000204

00000205

00000206

00000207

00000208

00000209

0000020A

0000020B

XXXXXXXX

X 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

XXXXXXXX

XXXX0000

(R/W)

DPDP

bit 16

bit 31

Address

bit 0

Initial value

DACSR

DATCR

(

) : Access

R/W : Read/Write enabled

: Undefined

· Register (DMA descriptor)

bit 31

Address

bit 0

DPDP

DMA
ch0
Descriptor
DMA
ch1
Descriptor

DMA
ch7
Descriptor

MB91F155/MB91154

UART

The UART is a serial I/O port for asynchronous (start and stop synchronization) communication or CLK syn-
chronous communication. Its features are as follows :
· Full-duplex double buffer
· Capable of asynchronous (start and stop synchronization) and CLK synchronous communication.
· Support for multiprocessor mode
· Baud rate by a dedicated baud rate generator
· Baud rate by an internal timer

The baud rate can be set with a 16-bit reload timer.

· Any baud rate can be set using an external clock.
· Error detection function (parity, framing, and overrun)
· NRZ-encoded transfer signals
· DMA transfer can be invoked by interrupt.

MB91F155/MB91154

· Block Diagram

MD1
MD0
CS2
CS1
CS0

SCKE
SOE

PEN
P
SBL
CL
A

REC
RXE
TXE

PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE

SIDR0 to SIDR3

Internal data bus

SODR0 to SODR3

Sending start

Reception
error

Generated signals
(to the CPU)

(SCK0 to SCK3)

Receive clock

Send clock

Start bit

detection circuit

Receive bit

counter

Receive parity

counter

Receive

shift register

Receiving

control circuit

Sending start

circuit

Send bit

counter

Send parity

counter

Send

shift register

Sending

control circuit

Received status

determination circuit

SMR 0 - 3
registers

SCR 0 - 3
registers

SSR 0 - 3
registers

Clock

selector

Dedicated baud rate
generator

16-bit reload timer

Control bus

Receive
interrupt signal
#26 to 29 *

Send
interrupt signal
#31 to 34 *

(SIN0 to SIN3)

(SOT0 to SOT3)

* : Interrupt numbers

MB91F155/MB91154

· Register List

SCR0

SCR1

SCR2

SCR3

SMR0

SMR1

SMR2

SMR3

SSR0

SSR1

SSR2

SSR3

SIDR0/SODR0

SIDR1/SIDR1

SIDR2/SIDR2

SIDR3/SIDR3

(R/W, W)

(R/W)

(R, R/W)

(R, W)

bit 8

bit 15

Address

bit 0

Initial value

00000100

00000-00

00001000

XXXXXXXX

0000001E

00000022

00000026

0000002A

0000001F

00000023

00000027

0000002B

0000001C

00000020

00000024

00000028

0000001D

00000021

00000025

00000029

(

) : Access

R/W : Read/Write enabled

R : Read only

W : Write only

: Not in use

X : Undefined

MB91F155/MB91154

PPG Timer

The PPG timer can output highly accurate PWM waveforms efficiently.
The MB91F155/MB91154 contains six PPG timer channels and its features are as follows :
· Each channel consists of a 16-bit down counter, a 16-bit data register attached with a frequency setting buffer,

a 16-bit compare register attached with a duty setting buffer, and a pin controller.

· The count clock for the 16-bit down counter can be selected from the following four types :

Internal clocks

/4,

/16, and

/64

· The counter value can be initialized by reset or counter borrow to "FFFF

· PWM output (by channel)
· DMA transfer can be invoked by interrupt.

· Block Diagram (Entire configuration)

External TRG 0 to 3

External TRG4

External TRG5

16-bit reload timer

channel 0

General control

(Factor selection)

16-bit reload timer

channel 1

General control

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

TRG input
PWM timer channel 0

TRG input
PWM timer channel 1

TRG input
PWM timer channel 2

TRG input
PWM timer channel 3

TRG input
PWM timer channel 4

TRG input
PWM timer channel 5

MB91F155/MB91154

· Register List

(Continued)

GCN1

GCN2

PTMR0

PCSR0

PDUT0

PCNH0

PCNL0

PTMR1

PCSR1

PDUT1

PCNH1

PCNL1

PTMR2

PCSR2

PDUT2

PCNH2

(R/W)

(R )

(W)

(R/W)

(R)

(W)

(R/W)

(R)

(W)

(R/W)

bit 8

bit 15

Address

bit 0

Initial value

0 0 1 1 0 0 1 0

0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

XXXXXXXX

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

XXXXXXXX

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

XXXXXXXX

0 0 0 0 0 0 0 -

00000094

00000095

00000097

00000098

00000099

0000009A

0000009B

0000009C

0000009D

0000009E

0000009F

000000A0

000000A1

000000A2

000000A3

000000A4

000000A5

000000A6

000000A7

000000A8

000000A9

000000AA

000000AB

000000AC

000000AD

000000AE

PCNL2

PTMR3

PCSR3

PDUT3

PCNH3

PCNL3

(R/W)

(R)

(W)

(R/W)

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

XXXXXXXX

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

000000AF

000000B0

000000B1

000000B2

000000B3

000000B4

000000B5

000000B6

000000B7

(

) : Access R/W : Read/Write enabled R : Read only W : Write only

: Not in use

X : Undefined

MB91F155/MB91154

(Continued)

PTMR4

PCSR4

PDUT4

PCNH4

PCNL4

PTMR5

PCSR5

PDUT5

PCNH5

PCNL5

(R )

(W)

(R/W)

(R)

(W)

(R/W)

1 1 1 1 1 1 1 1

XXXXXXXX

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

XXXXXXXX

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

000000B8

000000B9

000000BA

000000BB

000000BC

000000BD

000000BE

000000BF

000000C0

000000C1

000000C2

000000C3

000000C4

000000C5

000000C6

000000C7

bit 8

bit 15

Address

bit 0

Initial value

(

) : Access

R/W : Read/Write enabled

R : Read only

W : Write only

: Not in use

X : Undefined

MB91F155/MB91154

16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating internal
count clocks, and a control register.
The input clock can be selected from three internal clock types (2/8/32 machine clock divisions) .
DMA transfer can be invoked by interrupt.
This product type contains this 16-bit reload timer for four channels.

· Block Diagram

RELD

OUTE

OUTL

INTE

CNTE

TRG

OUT
CTL.

CSL1

CSL0

MOD2

MOD1

MOD0

16-bit reload register

16-bit down counter

Clock selector

IN CTL.

EXCK

Internal clocks

Clear

prescaler

GATE

Retrigger

Reload

R bus

IRQ

PWM (ch0, ch1)
A/D (ch2)

MB91F155/MB91154

· Register List

TMCSR0

TMCSR1

TMCSR2

TMCSR3

TMR0

TMR1

TMR2

TMR3

TMRLR0

TMRLR1

(R/W)

(R)

(W)

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

XXXXXXXX

00000032

00000033

0000003A

0000003B

00000042

00000043

0000004A

0000004B

0000002E

0000002F

00000036

00000037

0000003E

0000003F

00000046

00000047

0000002C

0000002D

00000034

00000035

TMRLR2

TMRLR3

(W)

XXXXXXXX

0000003C

0000003D

00000044

00000045

bit 15

Address

bit 0

Initial value

(

) : Access

R/W : Read/Write enabled

R : Read only

W : Write only

: Not in use

X : Undefined

MB91F155/MB91154

Bit Search Module

The module searches data written to the input register for "0" or "1" or a "change" and returns the detected bit
position.

· Block Diagram

· Register List

D bus

Address
decoder

Detection

mode

Input latch

Changing one detection into data

Bit search circuit

Search results

000003F0

000003F1

000003F2

000003F3

000003F4

000003F5

000003F6

000003F7

000003F8

000003F9

000003FA

000003FB

XXXXXXXX

(W)

(R/W)

(W)

BSD0

bit 16

bit 31

Address

bit 0

Initial value

BSD1

BSDC

000003FC

000003FD

000003FE

000003FF

XXXXXXXX

(R)

BSRR

(

) : Access

R/W : Read/Write enabled

R : Read only

W : Write only

X : Undefined

MB91F155/MB91154

8/10-bit A/D Converter (Sequential Conversion Type)

The A/D converter is a module that converts analog input voltage into a digital value. Its features are as follows :
· A minimum conversion time of 5.0

s/ch. (Including sampling time at a 33 MHz machine clock)

· Contains a sample and hold circuit.
· Resolution : 10 or 8 bits selectable.
· Selection of analog input from eight channels by program

· DMA transfer can be invoked by interrupt.
· Selection of an invoking factor from software, external pin trigger (falling edge) , and 16-bit reload timer (rising

edge) .

· Block Diagram

Single conversion mode :

Selects and converts one channel.

Continuous conversion mode : Converts a specified channel repeatedly.

Stop and convert mode :

Stops after converting one channel and stands by until invoked the next time.
(Conversion invoking can be synchronized.)

Decoder

Comparator

Data register

A/D control register 1

A/D control register 2

Sample & hold circuit

AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7

ADCR

D/A converter

Sequential compare

Input

circuit

ADCS1

Operating clock

Prescaler

16-bit reload timer 2

External pin trigger

AVR

R - BUS

MB91F155/MB91154

Interrupt Controller

The interrupt controller accepts and arbitrates interrupts.

· Block Diagram

to LEVEL0*

NMI processing

Level

determination

Vector

determination

Level vector

generation

Priority determination

INT0*

NMI*

.
.
.

RI00

RI47

(DLYIRQ)

.
.
.

DLYI*

.
.

ICR00

ICR47

Request to

withdraw

HLDREQ

R bus

LEVEL4

HLDCAN*

to VCT0*

VCT5

*1 : DLY1 represents the delay interrupt module (delay interrupt generator) . (For detailed information, see

section 10, "Delay Interrupt Module."

*2 : INT0 is a wake-up signal for the clock controller in sleep or stop mode.

*3 : HLDCAN is a bus surrender request signal for bus masters except for the CPU.

*4 : LEVEL 4 - 0 are interrupt level outputs.

*5 : VCT 5 - 0 are interrupt vector outputs.

*6 : This product type does not have the NMI function.

MB91F155/MB91154

· Register List

(Continued)

ICR00

00000400

(R/W)

- - - - 1 1 1 1

ICR01

00000401

(R/W)

- - - - 1 1 1 1

ICR02

00000402

(R/W)

- - - - 1 1 1 1

ICR03

00000403

(R/W)

- - - - 1 1 1 1

ICR04

00000404

(R/W)

- - - - 1 1 1 1

ICR05

00000405

(R/W)

- - - - 1 1 1 1

ICR06

00000406

(R/W)

- - - - 1 1 1 1

ICR07

00000407

(R/W)

- - - - 1 1 1 1

ICR08

00000408

(R/W)

- - - - 1 1 1 1

ICR09

00000409

(R/W)

- - - - 1 1 1 1

ICR10

0000040A

(R/W)

- - - - 1 1 1 1

ICR11

0000040B

(R/W)

- - - - 1 1 1 1

ICR12

0000040C

(R/W)

- - - - 1 1 1 1

ICR13

0000040D

(R/W)

- - - - 1 1 1 1

ICR14

0000040E

(R/W)

- - - - 1 1 1 1

ICR15

0000040F

(R/W)

- - - - 1 1 1 1

ICR16

00000410

(R/W)

- - - - 1 1 1 1

ICR17

00000411

(R/W)

- - - - 1 1 1 1

ICR18

00000412

(R/W)

- - - - 1 1 1 1

ICR19

00000413

(R/W)

- - - - 1 1 1 1

ICR20

00000414

(R/W)

- - - - 1 1 1 1

ICR21

00000415

(R/W)

- - - - 1 1 1 1

ICR22

00000416

(R/W)

- - - - 1 1 1 1

ICR23

00000417

(R/W)

- - - - 1 1 1 1

ICR24

00000418

(R/W)

- - - - 1 1 1 1

ICR25

00000419

(R/W)

- - - - 1 1 1 1

ICR26

0000041A

(R/W)

- - - - 1 1 1 1

ICR27

0000041B

(R/W)

- - - - 1 1 1 1

ICR28

0000041C

(R/W)

- - - - 1 1 1 1

ICR29

0000041D

(R/W)

- - - - 1 1 1 1

ICR30

0000041E

(R/W)

- - - - 1 1 1 1

ICR31

0000041F

(R/W)

- - - - 1 1 1 1

ICR32

00000420

(R/W)

- - - - 1 1 1 1

ICR33

00000421

(R/W)

- - - - 1 1 1 1

ICR34

00000422

(R/W)

- - - - 1 1 1 1

ICR35

00000423

(R/W)

- - - - 1 1 1 1

ICR36

00000424

(R/W)

- - - - 1 1 1 1

ICR37

00000425

(R/W)

- - - - 1 1 1 1

ICR38

00000426

(R/W)

- - - - 1 1 1 1

ICR39

00000427

(R/W)

- - - - 1 1 1 1

bit 7

bit 0

bit 7

bit 0

Address

Initial value

Address

Initial value

(

) : Access

R/W : Read/Write enabled

: Not in use

MB91F155/MB91154

External Interrupt

The external interrupt controller controls external interrupt requests input to INT pins 0 through 15.
The level of requests to be detected can be selected from "H, " "L, " rising edge, and falling edge.

· Block Diagram

· Register List

10. Delay Interrupt Module

The delay interrupt is a module that generates task switching interrupts. The use of this module allows the
software to generate/cancel interrupt requests to the CPU.
For the block diagram of the delay interrupt module, see section 8, "Interrupt Controller."

· Register List

Interrupt permission register

Interrupt factor register

Request level setting register

R bus

Interrupt

request

Gate

Factor F/F

Edge detection

circuit

INT0 to INT15

EIRR0

EIRR1

ENIR0

ENIR1

ELVR0

ELVR1

(R/W)

0 0 0 0 0 0 0 0

000000C8

000000C9

000000CA

000000CB

000000CC

000000CD

000000CE

000000CF

bit 8

bit 15

Address

bit 0

Initial value

(

) : Access

R/W : Read/Write enabled

DICR

(R/W)

bit 7

Address

bit 0

Initial value

- - - - - - - 0

00000430

(

) : Access

R/W : Read/Write enabled

: Not in use

MB91F155/MB91154

· Block Diagram

[Gear controller]

[Stop/sleep controller]

[Reset factor circuit]

[Watchdog controller]

GCR register

CPU gear

CPU Clock
Internal bus clock

Stop state
Sleep state
CPU Hold request

Internal reset

Internal
peripheral clock

Peripheral

gear

Internal clock

generating

circuit

Status

transition

control

circuit

Oscillator

circuit

Power on

detection circuit

GND

RSRR register

WPR register

Timebase timer

CTBR register

Watchdog F/F

Count clock

RST pin

P
X

PLL

Reset

generating

F/F

STCR register

PDRR register

Internal interrupt

Internal reset

DMA request

MB91F155/MB91154

12. External Bus Interface

The external bus interface controls the interface between the external memory and the external I/O. Its features
are as follows :
· 24-bit (16 MB) address output
· An 8/16-bit bus width can be set by chip select area.
· Inserts an automatic and programmable memory wait (for seven cycles at maximum) .
· Unused addresses/data pins are available as I/O ports.
· Support for little endian mode
· Use of a clock doubler, 33 MHz internal and 16.5 MHz external bus operations

· Block Diagram

Write
buffer

Read
buffer

Address
buffer

Switch

A-Out

U
X

External DATA Bus

ASR

AMR

Registers

Control

External pin controller

Shifter

Comparator

Controls all blocks.

Inpage

1 or

DATA BLOCK

ADDRESS BLOCK

External
Address Bus

CS0 to CS3

RD
WR0, WR1

BRQ
BGRNT
RDY
CLK

ADDRESS B

ATA

MB91F155/MB91154

· Register List

ASR1

AMR1

ASR2

AMR2

ASR3

AMR3

ASR4

AMR4

ASR5

AMR5

AMD0

AMD1

AMD32

AMD4

AMD5

EPCR0

(W)

(R/W)

bit 16

bit 31

bit 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0

(W)

0 0 0 0 0 0 0 0

(W)

0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 1

(W)

0 0 0 0 0 0 0 0

(W)

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 0

(W)

0 0 0 0 0 0 0 0

(W)

0 0 0 0 0 0 0 0

(W)

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 1

(W)

- - - - - - - -

1 1 1 1 1 1 1 1

(W)

- - - - 1 1 0 0

- 1 1 1 1 1 1 1

- - - 0 0 1 1 1

0 - - 0 0 0 0 0

0 0 0 0 0 0 0 0

0 - - 0 0 0 0 0

0000060C

0000060D

0000060E

0000060F

00000610

00000611

00000612

00000613

00000614

00000615

00000616

00000617

00000618

00000619

0000061A

0000061B

0000061C

0000061D

0000061E

0000061F

00000628

00000629

0000062A

0000062B

00000620

00000621

00000622

00000623

00000624

000007FE

EPCR1

LER

MODR

(W)

- - - - - 0 0 0

XXXXXXXX

000007FF

Address

Initial value

(

) : Access

R/W : Read/Write enabled

W : Write only

: Not in use

X : Undefined

MB91F155/MB91154

13. Multifunction Timer

The multifunction timer unit consists of one 16-bit free-run timer, eight 16-bit output compare registers, four 16-
bit input capture registers, and six 16-bit PPG timer channels. By using this function 12 independent waveforms
can be output based on the 16-bit free-run timer and the input pulse width and external clock cycle can also be
measured.

· Timer Components
· 16-bit free-run timer (

The 16-bit free-run timer consists of a 16-bit up counter, a control register, a 16-bit compare clear register,
and a prescaler. The output value of this counter is used as the basic time (base timer) for output compare
and input capture.

· Output compare (

The output compare consists of eight 16-bit compare registers, a compare output latch, and a control register.
When the 16-bit free-run timer value agrees to the compare register value, the output level can be inverted
and an interrupt can also be generated.

· Input capture (

The input capture consists of capture registers corresponding to four independent external input pins and a
control register. By detecting any edge of signals input from external input pins, the 16-bit free-run timer value
can be held in the capture register and an interrupt can be generated at the same time.

· 16-bit PPG timer (

See the section on the PPG Timer.

MB91F155/MB91154

· Register List

bit15

bit8 bit7

bit0

IPCP1

IPCP0

IPCP3

IPCP2

OCCP1

OCCP0

OCCP3

OCCP2

OCCP5

OCCP4

OCCP7

OCCP6

OCS3,2

OCS1,0

OCS7,6

OCS5,4

TCDT

TCCS

ICS23

ICS01

000068

000069

00006A

00006B

00006C

00006D

00006E

00006F

000071

000073

000074

000075

000076

000077

000078

000079

00007A

00007B

00007C

00007D

00007E

00007F

000080

000081

000082

000083

000084

000085

000086

000087

000088

000089

00008A

00008B

00008C

00008D

00008E

00008F

XXXXXXXX

( R )

XXXXXXXX

( R )

XXXXXXXX

( R )

XXXXXXXX

( R )

XXXXXXXX

( R )

XXXXXXXX

( R )

XXXXXXXX

( R )

XXXXXXXX

( R )

00000000

( R/W )

00000000

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXX00000

( R/W )

0000XX00

( R/W )

XXX00000

( R/W )

0000XX00

( R/W )

XXX00000

( R/W )

0000XX00

( R/W )

XXX00000

( R/W )

0000XX00

( R/W )

00000000

( R/W )

00000000

( R/W )

0 - - - - - - -

( R/W )

00000000

( R/W )

Address

Initial value

(

) : Access R/W : Read/Write enabled R : Read only

: Not in use

X : Undefined

MB91F155/MB91154

14. Calendar Macro

·
·
·
·

Backup RAM

This macro is a calendar macro with a basic clock of 32.768 kHz.
The macro accomplishes clock functions including, year, month, date, hour, minutes, seconds, day of the week,
and leap years.
The macro counts the last two digits of calendar years 0 through 99.
A backup RAM is also contained.

· Block Diagram

· Register List

32 kHz

Oscillator

Calendar circuit

Backup RAM

Bus

controller

2 (for backup)

BACKUP
(for data protection)

b
u
s

bit15

Address

bit8

bit17

bit0

Initial value

CAC

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CAS

000210

000211

00000000

( R/W )

- - XXXXXX

( R/W )

000212

000213

- - XXXXXX

( R/W )

- - - XXXXX

( R/W )

000214

000215

- - -XXXXX

( R/W )

- - - - - XXX

( R/W )

000216

000217

- - - - XXXX

( R/W )

- XXXXXXX

( R/W )

00021F

0 - - - - - - 0

( R/W )

(

) : Access

R/W : Read/Write enabled

: Not in use

X : Undefined

MB91F155/MB91154

15. I

C Interface

The I

C interface is a serial I/O port that supports the Inter IC BUS and operates as a master/slave device on

the I

C bus.

· Features of the I

C Interface

Contains one I

C interface channel.

The interface has the following features :

· Master/slave send and receive
· Arbitration function
· Clock synchronization function
· Slave address/general call address detection function
· Transfer direction detection function
· Repeated generation and detection of start conditions
· Bus error detection function

· Register List

· Bus control register (IBCR)

· Bus status register (IBSR)

· Address register (IADR)

· Clock control register (ICCR)

· Data register (IDAR)

R/W : Read/Write enabled, R: Read only,

: Not in use, X: Undefined

Address

Initial value

0000-0120

00000000

Address

Initial value

0000-0121

00000000

Address

Initial value

0000-0122

- XXXXXXX

Address

Initial value

0000-0123

0XXXXX

Address

Initial value

0000-0125

XXXXXXXX

R/W

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

BER

BEIE

SCC

MSS

ACK

GCAA

INTE

INT

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RSC

LRB

AAS

GCA

FBT

R/W

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

R/W

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

CS4

CS3

CS2

CS1

CS0

R/W

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

MB91F155/MB91154

· Block Diagram

C enable

Peripheral clock

Clock division 1

Clock selection 1

Clock division 2

Shift clock generation

Clock selection 2

R bus

ICCR

IBCR

Start

Master

Slave

Global call

ACK permission

GC-ACK permission

IBSR

Slave address

comparison

IBSR

BER

SCC

MSS

ACK

AAS

GCAA

GCA

IADR

IRQ

End

Start/stop condition detection

SDA

SCL

First Byte

Error

Start/stop condition detection

Arbitration lost detection

Interrupt request

Last Bit

Bus busy

Send/Receive

Repeat start

Sync

Shift clock

edge variation timing

IDAR

BEIE

INTE

INT

RSC

LRB

FBT

CS4

CS3

CS2

CS1

CS0

128

256

ICCR

MB91F155/MB91154

16. FLASH Memory

The MB91F155 contains a 510-Kbyte (4 Mbits) flash memory of which the sectors can be erased all at once or
sector by sector and that can be written with the FR-CPU by half word (16 bits) using a single 0.3 V power supply.

The MB91F155 accomplishes the following functions by a combination of the flash memory macro and the FR-
CPU interface circuit :
· Functions as the CPU program/data storage memory :

When used as a ROM, the memory is accessible with a 32-bit bus width.
Allows the CPU to read from/write to/erase the memory (automatic program algorithm*) .

· Functions equivalent to the stand-alone MBM29LV400C flash memory product :

Allows a ROM programmer to read from/write to/erase the memory (automatic program algorithm*)

At this time, using the flash memory from the FR-CPU is described. For detailed information about using the
flash memory from the ROM programmer, refer to the ROM programmer instruction manual.

* : Automatic program algorithm

Embedded Algorithm

is a trademark of Advanced Micro Devices, Inc.

· Block Diagram

RDY/BUSY

Rising edge detection

Flash memory
4 Mbit (510 K

8/255 K

16)

Control signal

generation

RESET

BYTE
OE

FA18 - 0

Address buffer

FR-C bus (instructions/data)

Data buffer

CA18 - 0

INTE

Interrupt requests

Bus control signals

RDYINT

RDY

CD31 - 0

DI15 - 0

DO31 - 0

MB91F155/MB91154

· Memory Map

Flash memory address mapping varies between FLASH memory mode and CPU mode. Mapping in each mode
is shown next.

SA6

SA5

SA4

SA3

SA2

SA1

SA0

SA13

SA12

SA11

SA10

SA9

SA8

SA7

( SAn : sector address n )

0FFFFF

0F8000

0F4000

0F0000

0E0000

0C0000

080000

080800

080000

0007C0

000000

0A0000

080800

CPU mode

FLASH memory area

RAM area 2 Kbytes

Status register

SA13

SA12

SA11

SA10

SA9

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

( SAn : sector address n )

0FFFFF

4M-FLASH

memory image

07FFFF

010000

000000

FLASH memory mode

Memory mapping in FLASH memory mode :

Memory mapping in CPU mode :

MB91F155/MB91154

· Sector Address Table

· Registers

FLCR : Status register (CPU mode)

This register indicates the FLASH memory operating status. The register controls interrupts to the CPU as well
as writing to the FLASH memory.
This register is accessible only in CPU mode. Do not access this register with read modify write instructions.

FWTC : Wait register

This register controls waiting for the FLASH memory in CPU mode.
The register also controls accessing to read from the FLASH memory (33 MHz operations) at high speeds.

Sector address

Address range

Corresponding bit

positions

Sector capacity

SA7

080802, 3

to 09FFFE, F

(16 bits on LSB side)

bit15 to 0

64 Kbyte

SA8

0A0002, 3

to 0BFFFE, F

(16 bits on LSB side)

bit15 to 0

64 Kbyte

SA9

0C0002, 3

to 0DFFFE, F

(16 bits on LSB side)

bit15 to 0

64 Kbyte

SA10

0E0002, 3

to 0EFFFE, F

(16 bits on LSB side)

bit15 to 0

32 Kbyte

SA11

0F0002, 3

to 0F3FFE, F

(16 bits on LSB side)

bit15 to 0

8 Kbyte

SA12

0F4002, 3

to 0F7FFE, F

(16 bits on LSB side)

bit15 to 0

8 Kbyte

SA13

0F8002, 3

to 0FFFFE, F

(16 bits on LSB side)

bit15 to 0

16 Kbyte

SA0

080800, 1

to 09FFFC, D

(16 bits on MSB side)

bit31 to 16

64 Kbyte

SA1

0A0000, 1

to 0BFFFC, D

(16 bits on MSB side)

bit31 to 16

64 Kbyte

SA2

0C0000, 1

to 0DFFFC, D

(16 bits on MSB side)

bit31 to 16

64 Kbyte

SA3

0E0000, 1

to 0EFFFC, D

(16 bits on MSB side)

bit31 to 16

32 Kbyte

SA4

0F0000, 1

to 0F3FFC, D

(16 bits on MSB side)

bit31 to 16

8 Kbyte

SA5

0F4000, 1

to 0F7FFC, D

(16 bits on MSB side)

bit31 to 16

8 Kbyte

SA6

0F8000, 1

to 0FFFFE, F

(16 bits on MSB side)

bit31 to 16

16 Kbyte

R/W

( 0 )

R/W

( 0 )

( X )

R/W

( 0 )

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RDYINT

R/W

( 0 )

INTE

RDY

LPM

0007C0

R/W: Read/Write enabled, R: Read only,

: Not in use, X: Undefined

(

)

(

)

(

)

(

)

( 0 )

R/W

( 0 )

R/W

( 0 )

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

(

)

FACH

WTC1

WTC0

0007C4

R/W: Read/Write enabled, W: Write only,

: Not in use, X: Undefined

MB91F155/MB91154

· Register List

Initial value

DA06

DA07

DA05

DA04

DA03

DA02

DA01

DA00

DADR0
00000E3

bit

DA16

DA17

DA15

DA14

DA13

DA12

DA11

DA10

DADR1
00000E2

bit

DA26

DA27

DA25

DA24

DA23

DA22

DA21

DA20

DADR2
00000E1

bit

DAE0

DACR0
00000DF

bit

DAE1

DACR1
00000DE

bit

DAE2

DACR2
00000DD

bit

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

XXXXXXXX

( R/W )

- - - - - - - 0

( R/W )

- - - - - - - 0

( R/W )

- - - - - - - 0

( R/W )

( ): Access, R/W: Read/Write enabled,

: Not in use, X: Undefined

MB91F155/MB91154

18. 8/16-bit Up/Down Counters/Timers

This is the up/down counter/timer block consisting of six event input pins, two 8-bit up/down counters, two 8-bit
reload/compare registers, and their control circuits.

The features of this module are as follows :
· Capable of counting in the (0) d- (256) d range by the 8-bit count register.

(In 16-bit

1 operating mode, the register can count in the (0) d- (65535) d range.)

· Four count modes to choose from by the count clock.
· In timer mode the count clock can be selected from two internal clock types.
· In up/down count mode an external pin input signal detection edge can be selected.
· The phase-difference count mode is suitable for encoder counting, such as of motors. Rotation angles, rotating

speeds, and so on can be counted accurately and easily by inputting the output of phases A, B, and Z.

· Two types of function to choose from for the ZIN pin. (Enabled in all modes)
· Equipped with compare and reload functions which can be used individually or in combination. When combined,

these functions can count up/down at any width.

· The immediately preceding count direction can be identified by the count direction flag.
· Capable of individually controlling interrupt generation when comparison results match, at occurrence of reload

(underflow) or overflow, or when the count direction changes.

MB91F155/MB91154

· Register List

( ): Access, R/W: Read/Write enabled, R: Read only, W: Write only,

: Not in use, X: Undefined

Initial value

Address : 00005F

00000000

(R)

Initial value

Address : 00005E

00000000

(R)

Initial value

Address : 00005D

00000000

(W)

Initial value

Address : 00005C

00000000

(W)

Initial value

Address : 000063

00000000

(R/W)

Initial value

Address : 000067

00000000

(R/W)

Initial value

Address : 000061

-000X000

(R/W, W)

Initial value

Address : 000065

-000X000

(R/W, W)

Initial value

Address : 000060

00000000

(R/W)

Initial value

Address : 000064

-0000000

(R/W)

bit

UDCR0

bit

UDCR1

bit

RCR0

bit

RCR1

bit

CSR0

bit

CSR1

bit

CCRL0

bit

CCRL1

bit

CCRH0

bit

CCRH1

MB91F155/MB91154

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

0.0 V)

*1 : Take care not to exceed Vcc

0.3 V when turning on the power, for example.

Take care also to prevent AVcc from exceeding Vcc when turning on the power, for example.

*2 : The maximum output current stipulates the peak value of a single concerned pin.

*3 : The average output current stipulates the average current flowing through a single concerned pin over a period

of 100 ms.

*4 : The total average output current stipulates the average current flowing through all concerned pins over a period

of 100 ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter

Symbol

Value

Unit

Remarks

Min.

Max.

Power supply voltage

, V

0.3

3.6

Analog supply voltage

0.3

3.6

Analog reference voltage

AVRH

0.3

3.6

Input voltage

0.3

Input voltage
(open drain port J)

0.3

5.5

Analog pin input voltage

0.3

Output voltage

0.3

"L" level maximum output current

"L" level average output current

OLAV

"L" level total maximum output current

100

"L" level total average output current

OLAV

"H" level maximum output current

"H" level average output current

OHAV

"H" level total maximum output current

"H" level total average output current

OHAV

Power consumption

500

Operating temperature

Storage temperature

Tstg

150

MB91F155/MB91154

Recommended Operating Conditions

0.0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

Parameter

Symbol

Value

Unit

Remarks

Min.

Max.

Power supply voltage

, V

3.15

3.6

During normal operations.

2.0

3.6

The RAM state is retained
when stopped.

Analog supply voltage

3.15

3.6

Analog reference voltage

AVRH

Operating temperature

MB91F155/MB91154

DC Characteristics

3.15 V to 3.6 V, V

0 V, T

C to

* : See "

I/O Circuit Type" in chapter 1.

(Continued)

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

"H" level input
voltage

Input except for
hysteresis input pin*

0.65

0.3

IHS

Hysteresis input pin*

0.8

0.3

"L" level input
voltage

Input except for
hysteresis input pin*

0.3

0.25

ILS

Hysteresis input pin*

0.3

0.2

"H" level output
voltage

Except for port J.

3.15 V

4.0 mA

0.5

"L" level output
voltage

Except for port J.

3.15 V

4.0 mA

0.4

Input leakage
current

3.6 V,

< V

"L" level output
voltage

OL2

Port J

3.15 V

15 mA

0.4

Open drain

Output appli-
cation voltage

Port J

0.3

5.0

Open drain

Pullup
resistance

PULL

RST, pullup pin

Power supply
current

3.3 V

TBD

CCS

3.3 V

TBD

During sleep
mode

CCH

3.3 V,

TBD

When
stopped

CCH2

CC2

3.3 V,

TBD

Backup cur-
rent when
calendar is
not in use (32
kHz stopped)

MB91F155/MB91154

(Continued)

3.15 V to 3.6 V, V

0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

Power supply
current
(Products with
an internal
flash memory)

3.3 V,

33 MHz

120

External buss
access avail-
able

CCS

3.3 V,

33 MHz

100

During sleep
mode

CCH

3.3 V,

150

When stopped

CCH2

CC2

3.3 V,

0.1

Backup cur-
rent when cal-
endar is not in
use (32 kHz
stopped)

Input capacity

Other than Vcc,
Vss, AVcc,
AVss, and
AVRH

MB91F155/MB91154

AC Characteristics

(1) Clock Timing Ratings

3.15 V to 3.6 V, V

0 V, T

C to

*1 : Frequency regulation is the maximum fluctuation from a set center frequency, represented in percentage, when

locked to a multiple.

*2 : The target analog section is the A/D.

*3 : The maximum external bus operating frequency allowed is 25 MHz.

*4 : The value when a minimum clock frequency of 10 MHz is input to X0 and half a division of the oscillator circuit

and the 1/8 gear are in use.

Parameter

Sym-

bol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Clock frequency
(high speed and self oscilla-
tion)

X0, X1

16.5

MHz

Range in which self
oscillation is allowed

Clock frequency
(high speed and PLL in use)

Range in which self
oscillation and the
use of the PLL for ex-
ternal clock input are
allowed

Clock frequency
(High speed an 1/2 division
input)

MHz

Range in which exter-
nal clocks can be in-
put

Clock frequency
(for the calendar macro)

X0A,

X1A

kHz

Self oscillation and
external clocks

Clock cycle time

30.3

1600*

Frequency regulation *

(When the PLL is locked.)

Internal operat-
ing clock fre-
quency

CPU

system

One wait is

set with the

wait con-

troller.

0.625*

MHz

Bus

system

CPB

0.625*

25*

Peripheral

system

CPP

0.625*

Analog section ex-
cluded. *

Analog section *

Internal operat-
ing clock cycle
time

CPU

system

30.3

1600*

Bus

system

CPB

40*

1600*

Peripheral

system

CPP

30.3

1600*

Analog section ex-
cluded. *

30.3

1000

section *

MB91F155/MB91154

The relationship between the X0 input and the internal clock set with the CHC/CCK1/CCK0 bit of the GCR (Gear
Control Register) is as shown next.

CYC

X0 input

· Source oscillation

(GCR CHC bit : 0)

(a) Gear

internal clock

CCK1/0 : 00

(b) Gear

1/2

internal clock

CCK1/0 : 01

1/4

internal clock

CCK1/0 : 10

(d) Gear

1/8

internal clock

CCK1/0 : 11

· Source oscillation

1/2

(GCR CHC bit : 1)

(a) Gear

internal clock

CCK1/0 : 00

(b) Gear

1/2

internal clock

CCK1/0 : 01

1/4

internal clock

CCK1/0 : 10

(d) Gear

1/8

internal clock

CCK1/0 : 11

Where t

CYC

H represents the internal clock H width and t

CYC

L the L width.

MB91F155/MB91154

(2) Reset Input Ratings

3.15 V to 3.6 V, V

0 V, T

C to

(3) Power On Reset

3.15 V to 3.6 V, V

0 V, T

C to

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Reset input time

RSTL

RST

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Power supply rising time

Vcc

0.2 V before

turning up the power.

Power supply cutoff time

OFF

Oscillation stabilization
delay

OSC

RST

RSTL

0.2 V

0.9

0.2 V

OSC

(Oscillation stabilization delay)

Holding RAM data.

OFF

RST

RSTL

A rapid change in supply voltage might activate power on reset.
When the supply voltage needs to be varied while operating, it is recommended to minimize
fluctuations to smoothly start up the voltage.

It is recommended to keep the rising
inclination less than 50 mV/ms.

When turning on the power, start the RST pin in
"L" level state, allow as much time as for t

RSTL

after

reaching the Vcc power supply level and then set
the pin to the H level.

MB91F155/MB91154

(4) Serial I/O (CH0-4)

3.15 V to 3.6 V, V

0 V, T

C to

Parameter

Symbol

Pin

name

Condition

Value

Unit Remarks

Min.

Max.

Serial clock cycle time

SCYC

Internal

clock

8 t

CPP

SCK

SO delay time

SLOV

Valid SI

SCK

IVSH

SCK

valid SI hold time

SHIX

Serial clock "H" pulse width

SHSL

External

clock

4 t

CPP

Serial clock "L" pulse width

SLSH

4 t

CPP

SCK

SO delay time

SLOV

Valid SI

SCK

IVSH

SCK

valid SI hold time

SHIX

Serial busy period

BUSY

6 t

CPP

SCS

SCK and SO delay time

CLZO

SCS

SCK input mask time

CLSL

3 t

CPP

SCS

SCK and SO Hi-Z time

CHOZ

SCK

SHIX

IVSH

SLOV

SCYC

SCK

SCS

CHOZ

BUSY

CLSL

IVSH

SHIX

SLOV

SLSH

CLZO

SHSL

Internal shift clock mode

External shift clock mode

MB91F155/MB91154

(6) Normal Bus Access and Read/Write Operations

3.15 V to 3.6 V, V

0 V, T

C to

*1 : If the bus is extended with either automatic wait insertion or RDY input, add the (t

CYC

the number of extended

cycles) time to this value.

*2 : This is the value at the time of (gear cycle

1) .

When the gear cycle is set to 1/2, 1/4 or 1/8, substitute "n" in the following formula with 1/2, 1/4 or 1/8 respectively.

Formula : (2

CYC

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

CS 0 - 3 delay time

CHCSL

CLK

CS0 to 3

CS 0 - 3 delay time

CHCSH

Address delay time

CHAV

CLK

A24 to A00

Data delay time

CHDV

CLK

D31 to D16

RD delay time

CLRL

CLK

RD delay time

CLRH

WR0 - 1 delay time

CLWL

CLK

WR0 to 1

WR0 - 1 delay time

CLWH

Valid address

valid data input time

AVDV

A24 to A00

D31 to D16

CYC

*1, *2

valid data input time

RLDV

D31 to D16

CYC

Data setup

time

DSRH

Rdata hold time

RHDX

MB91F155/MB91154

(8) Hold Timing

3.15 V to 3.6 V, V

0 V, T

C to

Note : More than one cycle exist after BRQ is fetched and before BGRNT changes.

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

BGRNT delay time

CHBGL

CLK

BGRNT

BGRNT delay time

CHBGH

Pin floating

BGRNT

time

XHAL

BGRNT

CYC

BGRNT

Pin valid time

HAHV

CYC

CLK

High impedance

CHBGL

XHAL

HAHV

CHBGH

tcyc

BRQ

BGRNT

Each pin

MB91F155/MB91154

(9) DMA Controller Timing

3.15 V to 3.6 V, V

0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

DREQ input pulse width

DRWH

DREQ0 to 2

2 t

CYC

DACK delay time
(typical bus)
(typical DRAM)

CLDL

CLK

DACK0 to 2

CLDH

EOP delay time
(typical bus)
(typical DRAM)

CLEL

CLK

EOP0 to 2

CLEH

DACK delay time
(Single Dram)
(Hyper Dram)

CHDL

CLK

DACK0 to 2

CYC

CHDH

EOP delay time
(Single Dram)
(Hyper Dram)

CHEL

CLK

EOP0 to 2

CYC

CHEH

CLK

CLEL

CLDL

CLEH

CLDH

CHDH

CHDL

CHEL

DRWH

tcyc

DACK0 - 2
EOP0 - 2
(Typical bus)
(Typical DRAM)

DACK0 - 2
EOP0 - 2
( Single DRAM )
( Hyper DRAM )

DREQ0 - 2

MB91F155/MB91154

A/D Converter Electrical Characteristics

3.15 V to 3.6 V, V

0 V, T

C to

Notes :

· The smaller the |AVRH| is, the greater the error is in general.
· The external circuit output impedance of analog input should be used in compliance with the following require-

ments :
External circuit output impedance

2 (k

)

If the output impedance of the external circuit is too high, an analog voltage sampling duration shortage might
occur. (Sampling duration

1.4

s : @33 MHz)

Parameter

Sym-

bol

Pin

name

Condition

Value

Unit

Re-

marks

Min.

Typ.

Max.

Resolution

Bit

Conversion time

5.1

Total error

3.3 V,

AVRH

3.3 V

4.0

LSB

Linearity error

3.5

LSB

Differential linearity error

2.0

LSB

Zero transition error

AN0 to

AN7

3.3 V,

3.3 V

1.5 AV

0.5 AV

2.5 LSB

Full-scale transition error

FST

AN0 to

AN7

5.5 AV

1.5 AV

0.5 LSB

Analog input current

AIN

AN0 to

AN7

0.1

Analog input voltage

AIN

AN0 to

AN7

Reference voltage

Supply cur-
rent

Conversion
in operation

3.3 V

3.0

5.0

Conversion
stopped

5.0

Reference
voltage
supply cur-
rent

Conversion
in operation

AVRH

3.3 V,

AVRH

3.3 V

2.0

3.0

Conversion
stopped

Interchannel variation

AN0 to

AN7

LSB

MB91F155/MB91154

100

· A/D Converter Glossary

(Continued)

· Resolution

: Analog changes that are identifiable by the A/D converter.

· Linearity error

: The deviation of the straight line connecting the zero transition point

(00 0000 0000

00 0000 0001) with the full-scale transition point

(11 1111 1110

11 1111 1111) from actual conversion characteristics.

· Differential linearity error : The deviation of input voltage needed to change the output code by one LSB

from the theoretical value.

· Total error

: The difference between actual and theoretical conversion values including a

zero transition/full-scale transition/linearity error.

3FF

3FE

3FD

004

003

002

001

AVRH

Analog input

0.5 LSB

{

1 LSB ( N

1 )

0.5 LSB

}

1.5 LSB

Theoretical characteristics

Actual conversion
characteristics

(Actual measurement)

Actual conversion

characteristics

Total error

Digital output

Total error of digital output N

{1 LSB

0.5 LSB}

1 LSB

1 LSB (theoretical value)

AVRH

1024

[V]

(theoretical value)

: Voltage at which digital output changes from (N

1) to N.

0.5 LSB

[V]

FST

(theoretical value)

AVRH

1.5 LSB

[V]

MB91F155/MB91154

101

(Continued)

D/A Converter Electrical Characteristics

3.15 V to 3.6 V, V

0 V, T

C to

* : CL

20 pF

Parameter

Symbol

Pin

name

Condi-

tion

Value

Unit

Re-

marks

Min.

Typ.

Max.

Resolution

Bit

Differential linearity error

LSB

Conversion time

Analog output impedance

Linearity error of digital

output N

{1 LSB

}

1 LSB

[LSB]

Differential linearity error

of digital output N

1) T

1 LSB

(theoretical value)

FST

1022

[V]

: Voltage at which digital output changes from (000)

to (001)

FST

: Voltage at which digital output changes from (3FE)

to (3FF)

[LSB]

3FF

3FE

3FD

004

003

002

001

AVRH

Analog input

Theoretical characteristics

Actual conversion
characteristics

Digital output

Actual conversion

characteristics

Linearity error

{

1 LSB ( N

1 )

}

FST

(Actual
measurement)

(Actual measurement)

AVRH

Analog input

Actual conversion
characteristics

Actual conversion

characteristics

Theoretical

characteristics

Digital output

Differential linearity error

FST

(Actual
measurement)

MB91F155/MB91154

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED
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F0101

FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.

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applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91154

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91154

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91154