DS07-16506-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-bit Microcontroller

CMOS

FR60Lite

MB91230 Series

MB91233L/MB91F233/MB91F233L/MB91V230

DESCRIPTION

The MB91230 series is a line of standard microcontrollers, based on a 32-bit high-performance RISC CPU and
containing variety of I/O resources, for embedded control applications which require high CPU performance at
high speed processing.

Audio motor control storage : Designed to specifications for embedded control applications which high CPU
performance power processing.

The MB91230 series belongs to the FR60Lite family.

FEATURES

· 32-bit RISC, load/store architecture with a 5 stage pipeline
· Maximum operating frequency: 33.6 MHz (oscillation frequency

4.2 MHz, oscillation frequency 8-multiplier

(PLL clock multiplication method) )

· 16-bit fixed length instructions (basic instructions)
· Execution speed of instructions : 1 instruction per cycle

(Continued)

PACKAGES

401-pin Ceramic PGA

120-pin Plastic LQFP

128-pin plastic FLGA

(PGA-401C-A02)

(FPT-120P-M05)

(LGA-128P-M01)

MB91230 Series

(Continued)

· Memory-to-memory transfer, bit handling, and barrel shift instructions, etc. : Instructions suitable for embedded

applications

· Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
· Register interlock function : Facilitates coding in assembler
· Built-in multiplier with instruction-level support

- 32-bit multiplication with sign : 5 cycles
- 16-bit multiplication with sign : 3 cycles

· Interrupt (PC and PS save) : 6 cycles (16 priority levels)
· Harvard architecture allowing program access and data access to be executed simultaneously
· Instruction compatible with FR family
· Capacity of built-in ROM and ROM type

- MASK ROM

: 256 KB

- FLASH ROM

: 256 KB

· Capacity of built-in RAM : 16 KB
· General-purpose ports : Maximum 98 ports (including N-ch open-drain port : 4 ports)
· A/D converter (series-parallel type)

- Resolution : 10-bit : 8 ch (4 ch

2 unit)

- Conversion time : 1.69

s (Minimum conversion time)

· D/A converter (R-2R type)

- Resolution : 8-bit : 2 ch (independence)
- Conversion speed : 0.6

s (when load capacitance 20 pF)

· External interrupt input : 16 ch
· Bit search module (for REALOS)

- Function for searching the MSB (Upper bit) in each word for the first "0" or "1" inverted point

· UART (full-duplex double buffer) : 4 ch

- Selectable parity On/Off
- Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
- Internal timer for dedicated baud rate (U-timer) on each channel
- External clock can be used as transfer clock
- Error detection function for parity, frame and overrun

· PPG : 16-bit

6 ch

· Up/down counter : 2 ch (8-bit

2 ch or 16-bit

1 ch)

· Reload timer : 16-bit

4 ch

· Free-run timer : 16-bit

2 ch

· Watch timer : 15-bit

1 ch

· PWC : 8-bit

2 ch

· Input capture : 2 ch (interface with free-run timer 0)
· Output compare : 4 ch (free-run timer 0 and output compare unit 0/1 cooperate, free-run timer 1 and

output compare units 2/3)

· LCD controller : SEG00 to SEG31/COM0 to COM3 (also serving as a port)
· Clock monitor (peripheral clock output function) : 1 ch
· Timebase/watchdog timer (26-bit)
· Real-time clock (counting even with the real-time clock stopped)
· Low Power Consumption Mode
· Sleep/stop function
· Package : LQFP-120, FLGA-128
· Technology : CMOS 0.35

· Power supply
· Dual power supply configuration [internal logic 3.3 V, I/O 5.5 V(3.3 V for ADC and DAC input/output)]

Note : Do not set the external bus mode in which the MB91230 series cannot operate.

MB91230 Series

PIN ASSIGNMENT

MB91233L, MB91F233, MB91F233L

(Continued)

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

P26/SCK2

P27/SIN3

P30/SOT3

P31/SCK3

P32/AIN0
P33/BIN0

P34/ZIN0

P35/AIN1
P36/BIN1

P37/ZIN1

P40/PPG0
P41/PPG1

X0A
X1A

P42/PPG2
P43/PPG3

P44/TOT0
P45/TOT1
P46/TOT2

P47/CKOT

P50/INT8
P51/INT9

P52/INT10

P53/INT11/PPG4
P54/INT12/PPG5

P55/INT13/TIN2
P56/INT14/TIN1

90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61

INIT
MD0
MD1
MD2
P73/COM3
P72/COM2
P71/COM1
P70/COM0
P67/SEG31

P66/SEG30

P65/SEG29

P64/SEG28

PB3/SEG27
PB2/SEG26
V

PB1/SEG25
PB0/SEG24
PA7/SEG23
PA6/SEG22
PA5/SEG21
PA4/SEG20
PA3/SEG19
PA2/SEG18
PA1/SEG17
PA0/SEG16
P97/SEG15
P96/SEG14
P95/SEG13
P94/SEG12

P57/INT15/TIN0/ADTG0

PF3/T

PF4/TIN3/ADTG1

PD0/D

PD1/D

VRH

PC0/AN0

PC1/AN1

PC2/AN2

PC3/AN3

PC4/AN4

PC5/AN5

PC6/AN6

PC7/AN7

3IO

P80/SEG0

P81/SEG1

P82/SEG2

P83/SEG3

P84/SEG4

P85/SEG5

P86/SEG6

P87/SEG7

P90/SEG8

P91/SEG9

P92/SEG10

P93/SEG11

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

P25/SO

P24/SIN2

P23/PWI1/OP3

P22/PWI0/OP2

P21/CKI1/OP1

P20/CKI0/OP0

P17/INT7

P16/INT6

P15/INT5

P14/INT4

P13/INT3

P12/INT2

P11/INT1

P10/INT0

P07/IC1

P06/IC0

P05/SCK1

P04/SO

P03/SIN1

P02/SCK0

P01/SO

P00/SIN0

(TOP VIEW)

(FPT-120P-M05)

* : Open-drain

MB91230 Series

(Continued)

MB91F233L

M10

M11

M12

L10

L11

L12

K10

K11

K12

J10

J11

J12

H10

H11

H12

G10

G11

G12

F10

F11

F12

E10

E11

E12

D10

D11

D12

C10

C11

C12

B10

B11

B12

A10

A11

A12

TOP VIEW

INDEX

(LGA-128P-M01)

MB91230 Series

Pin correspondence table of LQFP-120 and FLGA-128 in MB91230 series (LGA-128P-M01)

(Continued)

LQFP-120

No.

FLGA-128

No.

(JEDEC

No.)

Signal

name

LQFP-120

No.

FLGA-128

No.

(JEDEC

No.)

Signal

name

LQFP-120

No.

FLGA-128

No.

(JEDEC

No.

)

Signal

name

P26/SCK2

P03/SIN1

P42/PPG2

120

P25/SOT2

C10

117

P22/PWI0/

OP2

C11

P72/COM2

G3*

114

P17/INT7

C12

MD2

P37/ZIN1

PA6/

SEG22

109

P12/INT2

P33/BIN0

G10

107

P35/AIN1

G11

PB1/

SEG25

103

P10/INT0

119

P24/SIN2

G12

PB2/

SEG26

100

P05/SCK1

111

P14/INT4

P45/TOT1

A10

P02/SCK0

P43/PPG3

A11

101

P06/IC0

P47/CKOT

A12

P00/SIN0

P44/TOT0

P31/SCK3

MD0

PA0/

SEG16

118

P23/PWI1/

OP3

D10

P73/COM3

H10

PA7/

SEG23

115

P20/CKI0/

OP0

D11

P67/

SEG31*

H11

PA4/

SEG20

112

P15/INT5

D12

P71/COM1

H12

PB0/

SEG24

110

P13/INT3

X0A

P50/INT8

106

P36/BIN1

P46/TOT2

104

P11/INT1

P41/PPG1

P52/INT10

P04/SOT1

P32/AIN0

P55/INT13/

TIN2

P01/SOT0

P66/

SEG30*

PD1/DA1

B10

E10

P70/COM0

PC1/AN1

B11

MD1

E11

P65/

SEG29*

B12

INIT

E12

P81/SEG1

MB91230 Series

(Continued)

*1 : Open-drain

*2 : Connected to pin 17(V

3) on the LQFP120 version

*3 : Connected to pin 38(AV

) on the LQFP120 version

*4 : Signals added to the FLGA version

*5 : NC pin on the FLGA version

LQFP-120

No.

FLGA-128

No.

(JEDEC

No.)

Signal

name

LQFP-120

No.

FLGA-128

No.

(JEDEC

No.)

Signal

name

LQFP-120

No.

FLGA-128

No.

(JEDEC

No.

)

Signal

name

P34/ZIN0

P92/

SEG10

P27/SIN3

J10

PA3/

SEG19

P30/SOT3

X1A

J11

PA1/

SEG17

116

P21/CKI1/

OP1

P40/PPG0

J12

PA5/

SEG21

113

P16/INT6

PB3/

SEG27

P53/

INT11/

PPG4

108

F10

P64/

SEG28*

P51/INT9

105

F11

PF4/TIN3/

ADTG1

102

P07/IC1

F12

PC2/AN2

AVRH

PC5/AN5

L5*

AVRL*

PC0/AN0

3IO

PC4/AN4

PC3/AN3

P84/SEG4

PC6/AN6

PC7/AN7

P87/SEG7

P80/SEG0

K10

P96/

SEG14

P83/SEG3

P82/SEG2

K11

P95/

SEG13

L10

P86/SEG6

P85/SEG5

K12

PA2/

SEG18

L11

P91/SEG9

M10

P90/SEG8

P56/

INT14/

TIN1

L12

P97/

SEG15

M11

P93/

SEG11

P54/

INT12/

PPG5

P57/

INT15/

TIN0/

ADTG0

M12

P94/

SEG12

PF3/TOT3

PD0/DA0

MB91230 Series

PIN DESCRIPTION

(Continued)

Pin no.

Pin name

Circuit type

Description

LQFP

FLGA

SCK2

UART2 clock input/output.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

P26

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

SIN3

UART3 data input.
When using this function, corresponding bit of DDR2
register is set to input.

P27

General purpose input/output port.
This function is always valid.

SOT3

UART3 data output.
This function is valid when corresponding bit of PFR3
register is set to peripheral function.

P30

General purpose input/output port.
This function is valid when corresponding bit of PFR3
register is set to port function.

SCK3

UART3 clock input/output.
This function is valid when corresponding bit of PFR3
register is set to peripheral function.

P31

General purpose input/output port.
This function is valid when corresponding bit of PFR3
register is set to port function.

AIN0

Up/down counter 0 AIN input.
When using this function, corresponding bit of DDR3
register is set to input.

P32

General purpose input/output port.
This function is alwais valid.

BIN0

Up/down counter 0 BIN input.
When using this function, corresponding bit of DDR3
register is set to input.

P33

General purpose input/output port.
This function is always valid.

ZIN0

Up/down counter 0 ZIN input.
When using this function, corresponding bit of DDR3
register is set to input.

P34

General purpose input/output port.
This function is always valid.

AIN1

Up/down counter 1 AIN input.
When using this function, corresponding bit of DDR3
register is set to input.

P35

General purpose input/output port.
This function is always valid.

MB91230 Series

(Continued)

Pin no.

Pin name

Circuit type

Description

LQFP

FLGA

BIN1

Up/down counter 1 BIN input.
When using this function, corresponding bit of DDR3
register is set to input.

P36

General purpose input/output port.
This function is always valid.

ZIN1

Up/down counter 1 ZIN input.
When using this function, corresponding bit of DDR3
register is set to input.

P37

General purpose input/output port.
This function is always valid.

PPG0

PPG0 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.

P40

General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.

PPG1

PPG1 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.

P41

General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.

X0A

Sub-clock oscillation pin (32 kHz)

X1A

Power supply pin for backup (RTC)

Power supply pin (GND)

Power supply pin (3.3 V internal logic)

PPG2

PPG2 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.

P42

General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.

PPG3

PPG3 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.

P43

General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.

MB91230 Series

(Continued)

Pin no.

Pin name

Circuit type

Description

LQFP

FLGA

TOT0

Reload timer 0 output port.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.

P44

General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.

TOT1

Reload timer 1 output port.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.

P45

General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.

TOT2

Reload timer 2 output port.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.

P46

General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.

CKOT

Clock monitor function output pin.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.

P47

General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.

INT8

External interrupt input.
When using this function, corresponding bit of DDR5
register is set to input.

P50

General purpose input/output port.
This function is always valid.

INT9

External interrupt input.
When using this function, corresponding bit of DDR5
register is set to input.

P51

General purpose input/output port.
This function is always valid.

INT10

External interrupt input.
When using this function, corresponding bit of DDR5
register is set to input.

P52

General purpose input/output port.
This function is always valid.

MB91230 Series

(Continued)

Pin no.

Pin name

Circuit type

Description

LQFP

FLGA

PPG4

PPG4 output.
This function is valid when corresponding bit of PFR5
register is set to peripheral function.

INT11

External interrupt input.
This function is enabled when corresponding bit of
PFR5 register is set to port function and corresponding
bit of DDR5 resister is set to input.

P53

General purpose input/output port.
This function is valid when corresponding bit of PFR5
register is set to port function.

PPG5

PPG5 output.
This function is valid when corresponding bit of PFR5
register is set to peripheral function.

INT12

External interrupt input.
This function is enabled when corresponding bit of
PFR5 register is set to port function and corresponding
bit of DDR5 resister is set to input.

P54

General purpose input/output port.
This function is valid when corresponding bit of PFR5
register is set to port function.

TIN2

Reload timer 2 event input pin.
This function is valid when corresponding bit of DDR5
register is set to input.

INT13

External interrupt input.
This function is valid when corresponding bit of DDR5
register is set to input.

P55

General purpose input/output port.
This function is always valid.

TIN1

Reload timer 1 event input pin.
This function is valid when corresponding bit of DDR5
register is set to input.

INT14

External interrupt input.
This function is valid when corresponding bit of DDR5
register is set to input.

P56

General purpose input/output port.
This function is always valid.

MB91230 Series

(Continued)

Pin no.

Pin name

Circuit

type

Description

LQFP

FLGA

ADTG0

External trigger input pin of A/D converter 0.
This function is valid when corresponding bit of DDR5 reg-
ister is set to input.

TIN0

Reload timer 0 event input pin.
This function is valid when corresponding bit of DDR5 reg-
ister is set to input.

INT15

External interrupt input.
This function is valid when corresponding bit of DDR5 reg-
ister is set to input.

P57

General purpose input/output port.
This function is always valid.

TOT3

Reload timer 3 output port.
This function is valid when corresponding bit of PFRF
register is set to peripheral function.

PF3

General purpose input/output port.
This function is valid when corresponding bit of PFRF
register is set to port function.

ADTG1

External trigger input pin of A/D converter 1.
This function is valid when corresponding bit of DDRF
register is set to input.

TIN3

Reload timer 3 event input pin.
This function is valid when corresponding bit of DDRF
register is set to input.

PF4

General purpose input/output port.
This function is always valid.

DA0

D/A converter 0 output pin.
This function is valid when corresponding bit of PFRD
register is set to peripheral function.

PD0

General purpose input/output port.
This function is valid when corresponding bit of PFRD
register is set to port function.

DA1

D/A converter 1 output pin.
This function is valid when corresponding bit of PFRD
register is set to peripheral function.

PD1

General purpose input/output port.
This function is valid when corresponding bit of PFRD
register is set to port function.

Analog power supply (for A/D, D/A converter) .

AVRH

Analog reference power supply (for A/D, D/A converter) .

GND level input for analog circuit (for A/D, D/A converter) .

MB91230 Series

(Continued)

Pin no.

Pin name

Circuit type

Description

LQFP

FLGA

39 to 46

M4, J6, K5,

M5, L6, K6,

L7, M6

AN0 to AN7

Analog input pin for A/D converter.
This function is valid when corresponding bit of PFRC
register is set to peripheral function.

PC0 to PC7

General purpose input/output port.
This function is valid when corresponding bit of PFRC
register is set to port function.

Power supply pin (GND)

3IO

Power supply pin (analog-shared pin I/O)

49 to 56

L8, J8, M8,

L9, K8, M9,

L10, K9

SEG0 to

SEG7

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFR8
register is set to peripheral function.

P80 to P87

General purpose input/output port.
This function is valid when corresponding bit of PFR8
register is set to port function.

57 to 64

M10, L11, J9,

M11, M12,

K11, K10, L12

SEG8 to

SEG15

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFR9
register is set to peripheral function.

P90 to P97

General purpose input/output port.
This function is valid when corresponding bit of PFR9
register is set to port function.

65 to 72

H9, J11, K12,

J10, H11, J12,

G9, H10

SEG16 to

SEG23

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFRA
register is set to peripheral function.

PA0 to PA7

General purpose input/output port.
This function is valid when corresponding bit of PFRA
register is set to port function.

73, 74

H12, G11

SEG24,

SEG25

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFRB
register is set to peripheral function.

PB0, PB1

General purpose input/output port.
This function is valid when corresponding bit of PFRB
register is set to port function.

G10

Power supply pin (5 V I/O MB91V230/F233)

Power supply pin (3.3 V internal logic, I/O MB91F233L/
MB91233L)

F11

Power supply pin (GND)

77, 78

G12, F9

SEG26,

SEG27

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFRB
register is set to peripheral function.

PB2, PB3

General purpose input/output port.
This function is valid when corresponding bit of PFRB
register is set to port function.

MB91230 Series

(Continued)

Pin no.

Pin name

Circuit type

Description

LQFP

FLGA

79 to 82

F10, E11, E9,

D11

SEG28 to

SEG31

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFR6
register is set to peripheral function.

P64 to P67

General purpose input/output port. (open-drain)
This function is valid when corresponding bit of PFR6
register is set to port function.

83 to 86

E10, D12,

C11, D10

COM0 to

COM3

LCD controller/driver common pins.
This function is valid when corresponding bit of PFR7
register is set to peripheral function.

P70 to P73

General purpose input/output port.
This function is valid when corresponding bit of PFR7
register is set to port function.

87 to 89

C12, B11, D9

MOD2,
MOD1,

MOD0

Mode input pin.

B12

INIT

External reset input.

91 to 94

A12, B10,

C10, A11

V0 to V3

LCD controller/driver reference power supply input
pins.

SIN0

UART0 data input.
When using this function, corresponding bit of DDR0
register is set to input.

P00

General purpose input/output port.
This function is always valid.

SOT0

UART0 data output.
This function is valid when corresponding bit of PFR0
register is set to peripheral function.

P01

General purpose input/output port.
This function is valid when corresponding bit of PFR0
register is set to port function.

A10

SCK0

UART0 clock input/output.
This function is valid when corresponding bit of PFR0
register is set to peripheral function.

P02

General purpose input/output port.
This function is valid when corresponding bit of PFR0
register is set to port function.

SIN1

UART1 data input.
This function is valid when corresponding bit of DDR0
register is set to input.

P03

General purpose input/output port.
This function is always valid.

MB91230 Series

(Continued)

Pin no.

Pin name

Circuit type

Description

LQFP

FLGA

SOT1

UART1 data output.
This function is valid when corresponding bit of PFR0 reg-
ister is set to peripheral function.

P04

General purpose input/output port.
This function is valid when corresponding bit of PFR0 reg-
ister is set to port function.

100

SCK1

UART1 clock input/output.
This function is valid when corresponding bit of PFR0 reg-
ister is set to peripheral function.

P05

General purpose input/output port.
This function is valid when corresponding bit of PFR0 reg-
ister is set to port function.

101

IC0

Input capture input 0.
This function is valid when corresponding bit of DDR0
register is set to input.

P06

General purpose input/output port.
This function is always valid.

102

IC1

Input capture input 1.
This function is valid when corresponding bit of DDR0
register is set to input.

P07

General purpose input/output port.
This function is always valid.

103

INT0

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

P10

General purpose input/output port.
This function is always valid.

104

INT1

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

P11

General purpose input/output port.
This function is always valid.

105

Power supply pin (5 V I/O MB91V230/F233)

Power supply pin (3.3 V internal logic, I/O MB91F233L/
MB91233L)

106

Power supply pin (GND)

107

Main-clock oscillation pin

108

MB91230 Series

(Continued)

Pin no.

Pin name

Circuit type

Description

LQFP

FLGA

109

INT2

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

P12

General purpose input/output port.
This function is always valid.

110

INT3

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

P13

General purpose input/output port.
This function is always valid.

111

INT4

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

P14

General purpose input/output port.
This function is always valid.

112

INT5

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

P15

General purpose input/output port.
This function is always valid.

113

INT6

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

P16

General purpose input/output port.
This function is always valid.

114

INT7

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

P17

General purpose input/output port.
This function is always valid.

115

CKI0

External clock input pin for free-run timer 0.
This function is enabled when corresponding bit of PFR2
register is set to port function and corresponding bit of
DDR2 register is set to input.

OP0

Output compare 0 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

P20

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

MB91230 Series

(Continued)

Pin no.

Pin name

Circuit type

Description

LQFP

FLGA

116

CKI1

External clock input pin for free-run timer 1.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.

OP1

Output compare1 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

P21

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

117

PWI0

Pulse width counter 0 input.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.

OP2

Output compare2 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

P22

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

118

PWI1

Pulse width counter 1 input.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.

OP3

Output compare3 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

P23

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

119

SIN2

UART2 data input.
This function is valid when corresponding bit of DDR2
register is set to input.

P24

General purpose input/output port.
This function is always valid.

120

SOT2

UART2 data output.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

P25

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

(38)

AVRL

Analog reference power supply (for A/D converter)

A5, D6, E12,

F2, F12, M7

Unconnected pin.

MB91230 Series

I/O CIRCUIT TYPE

(Continued)

Type

Circuit type

Remarks

With Pull-up control (50 k

)

CMOS level output
I

4 mA/I

4 mA

CMOS hysteresis input (with standby control)

With Pull-up control (50 k

)

CMOS level output
I

4 mA/I

4 mA

CMOS hysteresis input (with standby control)
Test pin for FLASH

CMOS level output

CMOS hysteresis input (with standby control)

CMOS level output
I

4 mA/I

4 mA

CMOS hysteresis input (with standby control)
Test pin for FLASH

Pull-up control
Output drive Pch

Output drive Nch

Hysteresis input

Standby control

Pull-up control
Output drive Pch

Output drive Nch

Hysteresis input

Standby control

Test pin for FLASH

Analog SW control

Output drive Pch

Output drive Nch

Hysteresis input

Standby control

Output drive Pch

Output drive Nch

Hysteresis input

Standby control

Test pin for FLASH

Analog SW control

MB91230 Series

(Continued)

Type

Circuit type

Remarks

CMOS level output
I

4 mA/I

4 mA

CMOS hysteresis input (with standby control)
Also serving as an analog input

CMOS level output
I

4 mA/I

4 mA

CMOS hysteresis input (with standby control)
Also serving as an analog input

With Pull-up control (50 k

)

CMOS hysteresis input

High withstand-voltage input
CMOS input (hysteresis level)

Output drive Pch

Output drive Nch

Hysteresis input

Standby control

Analog input

Analog SW control

Output drive Pch

Output drive Nch

Hysteresis input

Standby control

Analog input

Analog SW control

Hysteresis input

Low impedance input

High impedance input

High voltage
detection
output

MB91230 Series

HANDLING DEVICES

Preventing Latchup

Latch-up may occur in a CMOS IC if a voltage greater than V

or less than V

is applied to an input or output

pin or if an above-rating voltage is applied between V

and V

A latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an
element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating.

Treatment of Unused Pins

Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pull-
up or pull-down resistor.

About Power Supply Pins

In products with multiple V

or V

pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V

and V

pins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1

F between V

and V

near

this device.

About Crystal Oscillator Circuit

Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that
X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to
the device as possible.

It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane
because stable operation can be expected with such a layout.

Treatment of NC and OPEN Pins

Pins marked as NC and OPEN must be left open-circuit.

About Mode Pins (MD0 to MD2)

These pins should be connected directly to V

or V

To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and V

or V

is as short as possible and the connection impedance is low.

Operation at Start-up

Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up.

Also, in order to provide the oscillation stabilization wait time for the oscillation circuit immediately after start-up,
hold the "L" level input to the INIT pin for the required stabilization wait time. (For INIT via the INIT pin, the
oscillation stabilization wait time setting is initialized to the minimum value) .

About Oscillation Input at Power On

When turning the power on, maintain clock input untill the device is released from the oscillation stabilization
wait state.

MB91230 Series

Clock Control Block

Input the "L" signal to the INIT pin to assure the clock oscillation stabilization wait time.

Switch Shared Port Function

To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR) .

Low Power Consumption Mode

To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR :
timebse counter control register) and be sure to use the following sequence

In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after the
standby returns.

· Please do not do the following when the monitor debugger is used.
· Break point setting for above instruction lines
· Step execution for above instruction lines

Power-on sequence for dual-power-supply model

· Notes on the power-on and power-off sequences

Power-on sequence : Vcc3B, Vcc3

Vcc

Vcc3IO, AVRH, V0-V3

Power-off sequence : Vcc3IO, AVRH, V0-V3 Vcc3

Vcc

Vcc3B, Vcc3

When V

is turned on earlier, a potential difference between V

and V

3 must fall within 3.6 V.

· The LCD power supply V3 must not exceed V

in voltage. Apply V3 after turning on V

· Turn on V

3 before applying the analog power supply AV

or an analog signal.

(LDI

#value_of_standby, R0) : value_of_standby is write data to STCR.

(LDI

#_STCR, R12)

: _STCR is address (481

) of STCR.

STB

R0, @R12

: Writing to standby control register (STCR)

LDUB @R12, R0

: STCR read for synchronous standby

LDUB @R12, R0

: Dummy re-read of STCR

NOP

: NOP

5 for arrangement of timing

NOP

MB91230 Series

Notes on the PS register

As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.

As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.
· The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS

instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event
or emulator menu :

1) The D0 and D1 flags are updated in advance.

2) An EIT handling routine (user interrupt or emulator) is executed.

3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed, and the D0 and D1 flags are updated

to the same values as in 1).

· The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed

to allow the interrupt.

1) The PS register is updated in advance.

2) An EIT handling routine (user interrupt) is executed.

3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the

same value as in 1).

Watchdog Timer

The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time.
The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from
being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on
operating programs until it resets the CPU.

As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
program execution.

For those conditions to which this exception applies, see the function description of watchdog timer.

Step execution of RETI instruction

If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed
repeatedly after step execution. This will prevent the main routine and low-interrupt-level programs from being
executed.

Do not execute step of RETI instruction for escape.

Disable the corresponding interrupt and execute debugger when the corresponding interrupt routine no longer
needs debugging.

Operand Break

Do not apply a data event break to access to the area containing the address of a system stack pointer.

MB91230 Series

BLOCK DIAGRAM

FR60Lite

CPU Core

Bit Search

ROM/FLASH

RAM

Bus Converter

External Memory

I/F

(MB91230 is not

supported)

Adapter

Clock Control

(Clock, Standby,

Reset, Watchdog,

TBT,

Main-Clock-

Stabilization-

Timer)

Clock Monitor

PORT I/F

Watch Timer

Real Time Clock

Interruption

Controller

LCDC, Driver,

Internal Reference

Voltage

External interrupt

0 to 15

UART

0 to 3

U-TIMER

0 to 3

Up/Down Counter

0, 1

Reload Timer

0 to 3

PPG

0 to 5

4 ch Input

10/8-bit A/D 0

4 ch Input

10/8-bit A/D 1

2 ch Output

8-bit D/A 0, 1

Input Capture 0, 1

Free Run Timer 0

Output Compare 0, 1

Free Run Timer 1

Output Compare 2, 3

8-bit PWC 0, 1

: Trriger signal

X0, X1

MD0 to MD2

INIT

X0A, X1A

INT0 to INT15

SIN0 to SIN3

SOT0 to SOT3

SCK0 to SCK3

AN0 to AN3

ADTG

AVRH

AN4 to AN7

ADTG

DA0, DA1

PORTs

CKOT

COM0 to COM3
SEG0 to SEG31

V0 to V3

AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1

TO0 to TO3

PPG0 to PPG5

IC0, IC1

OP0, OP1

CKI0

CKI1

OP2, OP3

PWI0, PWI1

MB91230 Series

MEMORY SPACE

Memory space

The FR60 Lite family has 4 gigabytes of logical address space (2

addresses) available to the CPU by linear

access.

· Direct Addressing Areas

The following address space areas are used as I/O areas.

These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.

The size of directly addressable areas depends on the length of the data being accessed as shown below.

byte data access

: 0 to 0FF

half word data access : 0 to 1FF

word data access

: 0 to 3FF

Memory Map

Note : Do not set the external bus mode in which the MB91230 series cannot operate.

0000 0000

0000 0400

0001 0000

0003 A000

0004 0000

0008 0000

0010 0000

FFFF FFFF

0001 0000

0003 C000

0004 0000

000C 0000

0010 0000

FFFF FFFF

I/O

MB91V230

MB91F233/L, MB91233L

I/O

Direct Addressing
Areas

Access

disallowed

Refer to I/O Map

Access

disallowed

Built-in RAM

24 KB

Access

disallowed

Emulation

SRAM area

512 KB

Access

disallowed

Built-in RAM

16 KB

Access

disallowed

Built-in

FLASH ROM

256 KB

Access

disallowed

MB91230 Series

MODE SETTINGS

The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.

· Mode Pins

The MD2, MD1, and MD0 pins specify how the mode vector fetch and reset vector fetch is performed.

Setting is prohibited other than that shown in the following table.

· Mode data

Data written to the internal mode register (MODR) by a mode vector fetch is called mode data.

After an operation mode has been set in the mode register, the device operates in the operation mode.

The mode data is set by all reset source. User programs cannot set data to the mode register.

Details of mode data description

[bit31 to bit24] Reserved bit

Be sure to set this bit to "00000111".
Operation is not guaranteed when any value other than "00000111" is set.

Note : Mode data set in the mode vector must be placed as byte data at 0x000FFFF8

Use the highest byte from bit31 to bit24 for placement as the FR family uses the big endian for byte
endian.

Mode Pins

Mode name

Reset vector

access area

Remarks

MD2

MD1

MD0

Internal ROM mode vector

Internal

External ROM mode vector

External

Not supported by this model.

bit

Operation mode setting bits

bit

24 23

16 15

8 7

XXXXXXXX

0x000FFFF8

0x000FFFFC

XXXXXXXX

Mode Data

Reset Vector

XXXXXXXX

Incorrect

Correct

MB91230 Series

I/O Map

[How to read the table]

Note : Initial values of register bits are represented as follows :

" 1 " : Initial Value " 1 "
" 0 " : Initial Value " 0 "
" X " : Initial Value " undefined"
" - " : No physical register at this location

Access is barred with an undefined data access attribute.

Address

Register

Block

000000

PDR0 [R/W] B

XXXXXXXX

PDR1 [R/W] B

XXXXXXXX

PDR2 [R/W] B

XXXXXXXX

PDR3 [R/W] B

XXXXXXXX

T-unit

Port data register

Read/write attribute Access unit
(B : byte, H : half word, W : word)

Initial value of register after reset

1...)

Leftmost register address (For word-length access, column 1 of the
register becomes the MSB of the data.)

MB91230 Series

(Continued)

Address

Register

Block

000000

PDR0 [R/W] B

XXXXXXXX

PDR1 [R/W] B

XXXXXXXX

PDR2 [R/W] B

XXXXXXXX

PDR3 [R/W] B

XXXXXXXX

Port data register

000004

PDR4 [R/W] B

XXXXXXXX

PDR5 [R/W] B

XXXXXXXX

PDR6 [R/W] B

XXXX----

PDR7 [R/W] B

----XXXX

000008

PDR8 [R/W] B

XXXXXXXX

PDR9 [R/W] B

XXXXXXXX

PDRA [R/W] B

XXXXXXXX

PDRB [R/W] B

----XXXX

00000C

PDRC [R/W] B

XXXXXXXX

PDRD [R/W] B

------XX

PDRF [R/W]

---XX---

000010

00003C

Unused

000040

EIRR0 [R/W]

B, H, W

00000000

ENIR0 [R/W]

B, H, W

00000000

ELVR0 [R/W] B, H, W

00000000 00000000

External interrupt
(INT0 to 7)

000044

DICR [R/W]

B, H, W

-------0

Delay interrupt

000048

TMRLR0 [W] H, W

XXXXXXXX XXXXXXXX

TMR0 [R] H, W

XXXXXXXX XXXXXXXX

Reload timer 0

00004C

TMCSR0 [R/W] B, H, W

----0000 00000000

000050

TMRLR1 [W] H, W

XXXXXXXX XXXXXXXX

TMR1 [R] H, W

XXXXXXXX XXXXXXXX

Reload timer 1

000054

TMCSR1 [R/W] B, H, W

----0000 00000000

000058

TMRLR2 [W] H, W

XXXXXXXX XXXXXXXX

TMR2 [R] H, W

XXXXXXXX XXXXXXXX

Reload timer 2

00005C

TMCSR2 [R/W] B, H, W

----0000 00000000

000060

SSR0 [R/W]

B, H, W

00001000

SIDR0 [R] B, H, W

SODR0 [W] B, H,

XXXXXXXX

SCR0 [R/W]

B, H, W

00000100

SMR0 [R/W]

B, H, W

00--0-0-

UART0

000064

UTIM0 [R] H (UTIMR0 [W] H)

00000000 00000000

UTIMC0 [R/W] B

0--00001

U-TIMER0

000068

SSR1 [R/W]

B, H, W

00001000

SIDR1 [R] B, H, W

SODR1 [W] B, H,

XXXXXXXX

SCR1 [R/W]

B, H, W

00000100

SMR1 [R/W]

B, H, W

00--0-0-

UART1

00006C

UTIM1 [R] H (UTIMR1 [W] H)

00000000 00000000

UTIMC1 [R/W] B

0--00001

U-TIMER1

MB91230 Series

(Continued)

Address

Register

Block

000070

SSR2 [R/W]

B, H, W

00001000

SIDR2 [R] B, H,

SODR2 [W] B, H,

XXXXXXXX

SCR2 [R/W]

B, H, W

00000100

SMR2 [R/W]

B, H, W

00--0-0-

UART2

000074

UTIM2 [R] H (UTIMR1 [W] H)

00000000 00000000

UTIMC2 [R/W] B

0--00001

U-TIMER2

000078

ADCS0 [R/W] H, W

XXXXXXXX XXXXXXXX

ADCT0 [R/W] H, W

000-0000 -000--00

A/D converter 0
(series-parallel type)

00007C

ADT00 (ADTH0/ADTL0) [R] H, W

000000XX XXXXXXXX

ADT01 (ADTH1/ADTL1) [R] H, W

000000XX XXXXXXXX

000080

ADT02 (ADTH2/ADTL2) [R] H, W

000000XX XXXXXXXX

ADT03 (ADTH3/ADTL3) [R] H, W

000000XX XXXXXXXX

000084

ADCS1 [R/W] H, W

XXXXXXXX XXXXXXXX

ADCT1 [R/W] H, W

000-0000 --000--00

A/D converter 1
(series-parallel type)

000088

ADT10 (ADTH0/ADTL0) [R] H, W

000000XX XXXXXXXX

ADT11 (ADTH1/ADTL1) [R] H, W

000000XX XXXXXXXX

00008C

ADT12 (ADTH2/ADTL2) [R] H, W

000000XX XXXXXXXX

ADT13 (ADTH3/ADTL3) [R] H, W

000000XX XXXXXXXX

000090

DACR1 [R/W]

B, H, W

-------0

DACR0 [R/W]

B, H, W

-------0

D/A converter

000094

DADR1 [R/W]

B, H, W

XXXXXXXX

DADR0 [R/W]

B, H, W

XXXXXXXX

000098

LCDCMR [R/W]

B, H, W

----0000

LCR0 [R/W]

B, H, W

00010000

LCR1 [R/W]

B, H, W

00000000

LCD controller/driver

00009C

VRAM0 [R/W]

B, H, W

XXXXXXXX

VRAM1 [R/W]

B, H, W

XXXXXXXX

VRAM2 [R/W]

B, H, W

XXXXXXXX

VRAM3 [R/W]

B, H, W

XXXXXXXX

0000A0

VRAM4 [R/W]

B, H, W

XXXXXXXX

VRAM5 [R/W]

B, H, W

XXXXXXXX

VRAM6 [R/W]

B, H, W

XXXXXXXX

VRAM7 [R/W]

B, H, W

XXXXXXXX

0000A4

VRAM8 [R/W]

B, H, W

XXXXXXXX

VRAM9 [R/W]

B, H, W

XXXXXXXX

VRAM10 [R/W]

B, H, W

XXXXXXXX

VRAM11 [R/W]

B, H, W

XXXXXXXX

0000A8

VRAM12 [R/W]

B, H, W

XXXXXXXX

VRAM13 [R/W]

B, H, W

XXXXXXXX

VRAM14 [R/W]

B, H, W

XXXXXXXX

VRAM15 [R/W]

B, H, W

XXXXXXXX

0000AC

CKR [R/W]

B, H, W

----0000

Clock monitor

MB91230 Series

(Continued)

Address

Register

Block

0000B0

RCR1 [W]

B, H, W

00000000

RCR0 [W]

B, H, W

00000000

UDCR1 [R]

B, H, W

00000000

UDCR0 [R]

B, H, W

00000000

Up/down counter0, 1

0000B4

CCRH0 [R/W]

B, H, W

00000000

CCRL0 [R/W]

B, H, W

00001000

CSR0 [R/W]

B, H, W

00000000

0000B8

CCRH1 [R/W]

B, H, W

00000000

CCRL1 [R/W]

B, H, W

00001000

CSR1 [R/W]

B, H, W

00000000

0000BC

unused

0000C0

SSR [R/W]

B, H, W

00001000

SIDR 3 [R] B, H,

SODR 3 [W] B, H,

XXXXXXXX

SCR [R/W]

B, H, W

00000100

SMR [R/W]

B, H, W

00--0-0-

UART3

0000C4

UTIM [R] H (UTIMR [W] H)

00000000 00000000

UTIMC [R/W] B

0--00001

U-TIMER3

0000C8

TMRLR3 [W] H, W

XXXXXXXX XXXXXXXX

TMR3 [R] H, W

XXXXXXXX XXXXXXXX

Reload
timer 3

0000CC

TMCSR3 [R/W] B, H, W

---00000 00000000

0000D0

EIRR1 [R/W]

B, H, W

00000000

ENIR1 [R/W]

B, H, W

00000000

ELVR1 [R/W] B, H, W

00000000 00000000

External interrupt
(INT8 to 16)

0000D4

TCDT0 [R/W] H, W

00000000 00000000

TCCS0 [R/W]

B, H, W

00000000

Free-run timer 0

0000D8

TCDT1 [R/W] H, W

00000000 00000000

TCCS1 [R/W]

B, H, W

00000000

Free-run timer 1

0000DC

IPCP1 [R] H, W

XXXXXXXX XXXXXXXX

IPCP0 [R] H, W

XXXXXXXX XXXXXXXX

Input capture

0000E0

ICS01 [R/W]

B, H, W

00000000

0000E4

OCCP1 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP0 [R/W] H, W

XXXXXXXX XXXXXXXX

Output compare

0000E8

OCCP3 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP2 [R/W] H, W

XXXXXXXX XXXXXXXX

0000EC

OCS23 [R/W] B, H, W

---0--00 0000--00

OCS01 [R/W] B, H, W

---0-00 0000--00

MB91230 Series

(Continued)

Address

Register

Block

0000F0

PWCC0 [R/W]

B, H, W

0---00-0

PWCD0 [R]

B, H, W

XXXXXXXX

PWCC1 [R/W]

B, H, W

0---00-0

PWCD1 [R]

B, H, W

XXXXXXXX

PWC0, 1

0000F4

WTDBL [R/W] B

-------0

WTCR [R/W] B, H

00000000 000-00-X

Real-time clock

0000F8

WTBR0 [R/W] B

---XXXXX

WTBR1 [R/W] B

XXXXXXXX

WTBR2 [R/W] B

XXXXXXXX

0000FC

WTHR [R/W]

B, H

---XXXXX

WTMR [R/W]

B, H

--XXXXXX

WTSR [R/W] B

--XXXXXX

000100

000114

Unused

000118

GCN10 [R/W] H

00110010 00010000

GCN20 [R/W] B

00000000

PPG

00011C

Unused

000120

PTMR0 [R] H, W

11111111 11111111

PCSR0 [W] H, W

XXXXXXXX XXXXXXXX

PPG0

000124

PDUT0 [W] H, W

XXXXXXXX XXXXXXXX

PCNH0 [R/W]

B, H, W

00000000

PCNL0 [R/W]

B, H, W

00000000

000128

PTMR1 [R] H, W

11111111 11111111

PCSR1 [W] H, W

XXXXXXXX XXXXXXXX

PPG1

00012C

PDUT1 [W] H, W

XXXXXXXX XXXXXXXX

PCNH1 [R/W]

B, H, W

00000000

PCNL1 [R/W]

B, H, W

00000000

000130

PTMR2 [R] H, W

11111111 11111111

PCSR2 [W] H, W

XXXXXXXX XXXXXXXX

PPG2

000134

PDUT2 [W] H, W

XXXXXXXX XXXXXXXX

PCNH2 [R/W]

B, H, W

00000000

PCNL2 [R/W]

B, H, W

00000000

000138

PTMR3 [R] H, W

11111111 11111111

PCSR3 [W] H, W

XXXXXXXX XXXXXXXX

PPG3

00013C

PDUT3 [W] H, W

XXXXXXXX XXXXXXXX

PCNH3 [R/W]

B, H, W

00000000

PCNL3 [R/W]

B, H, W

00000000

000140

PTMR4 [R] H, W

11111111 11111111

PCSR4 [W] H, W

XXXXXXXX XXXXXXXX

PPG4

000144

PDUT4 [W] H, W

XXXXXXXX XXXXXXXX

PCNH4 [R/W]

B, H, W

00000000

PCNL4 [R/W]

B, H, W

00000000

MB91230 Series

(Continued)

Address

Register

Block

000148

PTMR5 [R] H, W

11111111 11111111

PCSR5 [W] H, W

XXXXXXXX XXXXXXXX

PPG5

00014C

PDUT5 [W] H, W

XXXXXXXX XXXXXXXX

PCNH5 [R/W]

B, H, W

00000000

PCNL5 [R/W]

B, H, W

00000000

000150

0001FC

Unused

000200

0003EC

Unused

0003F0

BSD0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit search

0003F4

BSD1 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8

BSDC [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FC

BSRR [R] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000400

DDR0 [R/W] B

00000000

DDR1 [R/W] B

00000000

DDR2 [R/W] B

00000000

DDR3 [R/W]

B00000000

Data direction
register

000404

DDR4 [R/W] B

00000000

DDR5 [R/W] B

00000000

DDR6 [R/W] B

0000----

DDR7 [R/W] B

----0000

000408

DDR8 [R/W] B

00000000

DDR9 [R/W] B

00000000

DDRA [R/W] B

00000000

DDRB [R/W] B

----0000

00040C

DDRC [R/W] B

00000000

DDRD [R/W] B

------00

DDRF [R/W] B

---00---

000410

00041C

Unused

000420

PFR0 [R/W] B

--00-00-

PFR1 [R/W] B

--------

PFR2 [R/W] B

-00-0000

PFR3 [R/W] B

------00

Port function register

000424

PFR4 [R/W] B

00000000

PFR5 [R/W] B

---00---

PFR6 [R/W] B

0000----

PFR7 [R/W] B

----0000

000428

PFR8 [R/W] B

00000000

PFR9 [R/W] B

00000000

PFRA [R/W] B

00000000

PFRB [R/W] B

----0000

00042C

PFRC [R/W] B

--------

PFRD [R/W] B

------00

PFRF [R/W] B

----0---

000430

00043C

Unused

MB91230 Series

(Continued)

Address

Register

Block

000440

ICR00 [R/W]

B, H, W

---11111

ICR01 [R/W]

B, H, W

---11111

ICR02 [R/W]

B, H, W

---11111

ICR03 [R/W]

B, H, W

---11111

Interrupt control unit

000444

ICR04 [R/W]

B, H, W

---11111

ICR05 [R/W]

B, H, W

---11111

ICR06 [R/W]

B, H, W

---11111

ICR07 [R/W]

B, H, W

---11111

000448

ICR08 [R/W]

B, H, W

---11111

ICR09 [R/W]

B, H, W

---11111

ICR10 [R/W]

B, H, W

---11111

ICR11 [R/W]

B, H, W

---11111

00044C

ICR12 [R/W]

B, H, W

---11111

ICR13 [R/W]

B, H, W

---11111

ICR14 [R/W]

B, H, W

---11111

ICR15 [R/W]

B, H, W

---11111

000450

ICR16 [R/W]

B, H, W

---11111

ICR17 [R/W]

B, H, W

---11111

ICR18 [R/W]

B, H, W

---11111

ICR19 [R/W]

B, H, W

---11111

000454

ICR20 [R/W]

B, H, W

---11111

ICR21 [R/W]

B, H, W

---11111

ICR22 [R/W]

B, H, W

---11111

ICR23 [R/W]

B, H, W

---11111

000458

ICR24 [R/W]

B, H, W

---11111

ICR25 [R/W]

B, H, W

---11111

ICR26 [R/W]

B, H, W

---11111

ICR27 [R/W]

B, H, W

---11111

00045C

ICR28 [R/W]

B, H, W

---11111

ICR29 [R/W]

B, H, W

---11111

ICR30 [R/W]

B, H, W

---11111

ICR31 [R/W]

B, H, W

---11111

000460

ICR32 [R/W]

B, H, W

---11111

ICR33 [R/W]

B, H, W

---11111

ICR34 [R/W]

B, H, W

---11111

ICR35 [R/W]

B, H, W

---11111

000464

ICR36 [R/W]

B, H, W

---11111

ICR37 [R/W]

B, H, W

---11111

ICR38 [R/W]

B, H, W

---11111

ICR39 [R/W]

B, H, W

---11111

000468

ICR40 [R/W]

B, H, W

---11111

ICR41 [R/W]

B, H, W

---11111

ICR42 [R/W]

B, H, W

---11111

ICR43 [R/W]

B, H, W

---11111

00046C

ICR44 [R/W]

B, H, W

---11111

ICR45 [R/W]

B, H, W

---11111

ICR46 [R/W]

B, H, W

---11111

ICR47 [R/W]

B, H, W

---11111

000470

00047C

Unused

MB91230 Series

(Continued)

* : This register is set when the mode vector is fetched. Not user-accessible.

Address

Register

Block

000480

RSRR [R/W]

B, H, W

10000000

STCR [R/W]

B, H, W

00110011

TBCR [R/W]

B, H, W

00XXXX00

CTBR [W]

B, H, W

XXXXXXXX

Clock control

000484

CLKR [R/W]

B, H, W

00000000

WPR [R/W]

B, H, W

XXXXXXXX

DIVR0 [R/W]

B, H, W

00000011

DIVR1 [R/W]

B, H, W

00000000

000488

OSCCR [R/W] B

XXXXXXX0

00048C

WPCR [R/W] B

00---000

Watch timer

000490

OSCR [R/W] B

00---000

Main clock oscillation
stabilization wait timer

000494

0004FC

Unused

000500

PCR1 [R/W] B

00000000

PCR3 [R/W] B

00000000

Pull-up control
register

000504

00051C

Unused

000520

0007F8

Unused

0007FC

MODR*

XXXXXXXX

Operation mode

000800

000AFC

Unused

000B00

000FFC

Unused

001000

001FFC

Unused

MB91230 Series

INTERRUPT VECTOR

(Continued)

Interrupt source

Interrupt number

Interrupt level

Offset

TBR default

address

Reset

3FC

000FFFFC

Mode vector

3F8

000FFFF8

System reserved

3F4

000FFFF4

System reserved

3F0

000FFFF0

System reserved

3EC

000FFFEC

System reserved

3E8

000FFFE8

System reserved

3E4

000FFFE4

Coprocessor absent trap

3E0

000FFFE0

Coprocessor error trap

3DC

000FFFDC

INTE instruction

3D8

000FFFD8

Instruction break exception

3D4

000FFFD4

Operand break trap

3C0

000FFFD0

Step trace trap

3CC

000FFFCC

NMI request (tool)

3C8

000FFFC8

Undefined instruction exception

3C4

000FFFC4

NMI request
(This model has no NMI request)

15 (F

) fixed

3C0

000FFFC0

External interrupt 0

ICR00

3BC

000FFFBC

External interrupt 1

ICR01

3B8

000FFFB8

External interrupt 2

ICR02

3B4

000FFFB4

External interrupt 3

ICR03

3B0

000FFFB0

External interrupt 4

ICR04

3AC

000FFFAC

External interrupt 5

ICR05

3A8

000FFFA8

External interrupt 6

ICR06

3A4

000FFFA4

External interrupt 7

ICR07

3A0

000FFFA0

Reload timer 0

ICR08

39C

000FFF9C

Reload timer 1

ICR09

398

000FFF98

Reload timer 2

ICR10

394

000FFF94

UART0(Reception completed)

ICR11

390

000FFF90

UART0 (Transmission completed)

ICR12

38C

000FFF8C

UART1 (Reception completed)

ICR13

388

000FFF88

UART1 (Transmission completed)

ICR14

384

000FFF84

UART2 (Reception completed)

ICR15

380

000FFF80

UART2 (Transmission completed)

ICR16

37C

000FFF7C

MB91230 Series

(Continued)

Interrupt source

Interrupt number

Interrupt level

Offset

TBR default

address

UART3 (Reception completed)

ICR17

378

000FFF78

UART3 (Transmission completed)

ICR18

374

000FFF74

A/D ch0

ICR19

370

000FFF70

A/D ch1

ICR20

36C

000FFF6C

External interrupt8

ICR21

368

000FFF68

External interrupt9

ICR22

364

000FFF64

External interrupt 10

ICR23

360

000FFF60

External interrupt 11

ICR24

35C

000FFF5C

External interrupt 12

ICR25

358

000FFF58

External interrupt 13

ICR26

354

000FFF54

External interrupt 14

ICR27

350

000FFF50

External interrupt 15

ICR28

34C

000FFF4C

Real-time clock

ICR29

348

000FFF48

Main clock oscillation
stabilization wait timer

ICR30

344

000FFF44

Timebase timer 0 overflow

ICR31

340

000FFF40

Reload timer 3

ICR32

33C

000FFF3C

Watch timer

ICR33

338

000FFF38

UD Counter 0

ICR34

334

000FFF34

UD Counter 1

ICR35

330

000FFF30

PPG 0/1

ICR36

32C

000FFF2C

PPG 2/3

ICR37

328

000FFF28

PPG 4/5

ICR38

324

000FFF24

Free-run timer 0

ICR39

320

000FFF20

Free-run timer 1

ICR40

31C

000FFF1C

ICU 0 (capture)

ICR41

318

000FFF18

ICU 1 (capture)

ICR42

314

000FFF14

OCU 0 (match)

ICR43

310

000FFF10

OCU 1 (match)

ICR44

30C

000FFF0C

OCU 2 (match)

ICR45

308

000FFF08

OCU 3 (match)

ICR46

304

000FFF04

Delay interrupt source bit

ICR47

300

000FFF00

System reserved (Used by REALOS)

2FC

000FFEFC

System reserved (Used by REALOS)

2F8

000FFEF8

System reserved

2F4

000FFEF4

MB91230 Series

(Continued)

Interrupt source

Interrupt number

Interrupt level

Offset

TBR default

address

System reserved

2F0

000FFEF0

System reserved

2EC

000FFEEC

System reserved

2E8

000FFEE8

System reserved

2E4

000FFEE4

System reserved

2E0

000FFEE0

System reserved

2DC

000FFEDC

System reserved

2D8

000FFED8

System reserved

2D4

000FFED4

System reserved

2D0

000FFED0

System reserved

2CC

000FFECC

System reserved

2C8

000FFEC8

System reserved

2C4

000FFEC4

System reserved

2C0

000FFEC0

Used by INT instruction

80
to

255

50
to

2BC

000

000FFEBC

000FFC00

MB91230 Series

PIN STATUS IN EACH CPU STATE

Terms used as the status of pins mean as follows.

· Input enabled

Indicates that the input function can be used.

· Input 0 fixed

Indicates that the input level has been internally fixed to be "0" to prevent leakage when the input is released.

· Output Hi-Z

Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving.

· Output is maintained

Indicates the output in the output state existing immediately before this mode is established. If the device
enters this mode with an internal output peripheral operating or while serving as an output port, the output is
performed by the internal peripheral or the port output is maintained, respectively.

· State existing immediately before is maintained

When the device serves for output or input immediately before entering this mode, the device maintains the
output or is ready for the input, respectively.

MB91230 Series

Pin Status List

(Continued)

Pin

no.

Pin

name

Port

name

Specified function

name

At initializing

At sleep

mode

At Stop mode

Remarks

Input

Output

Input/

Output

Function

name

Reset

initializa-

tion

HIZ

P26/
SCK2

P26

SCK2 P26

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

P27/
SIN3

P27

SIN3

P27

P30/
SOT3

P30

SOT3

P30

Pull-up
options
can be
selected

P31/
SCK3

P31

SCK3 P31

Pull-up
options
can be
selected

P32/
AIN0

P32

AIN0

P32

Pull-up
options
can be
selected

P33/
BIN0

P33

BIN0

P33

Pull-up
options
can be
selected

P34/
ZIN0

P34

ZIN0

P34

Pull-up
options
can be
selected

P35/
AIN1

P35

AIN1

P35

Pull-up
options
can be
selected

P36/
BIN1

P36

BIN1

P36

Pull-up
options
can be
selected

P37/
ZIN1

P37

ZIN1

P37

Pull-up
options
can be
selected

P40/
PPG0

P40

PPG
0

P40

P41/
PPG1

P41

PPG
1

P41

MB91230 Series

Note : P : Port selected, F : Specified function selected

(Continued)

Pin

no.

Pin

name

Port

name

Specified function

name

At initializing

At sleep

mode

At Stop mode

Remarks

Input

Output

Input/

Output

Function

name

Reset

initialization

HIZ

13 X0A

14 X1A

3B/

16 V

17 V

P42/
PPG2

P42

PPG2

P42

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

P43/
PPG3

P43

PPG3

P43

P44/
TOT0

P44

TOT0

P44

P45/
TOT1

P45

TOT1

P45

P46/
TOT2

P46

TOT2

P46

P47/
CKOT

P47

CKOT

P47

P50/
INT8

P50

INT8

P50

P :

Retention
of the
immediately
prior state

F :

Input
enabled

P :

Output
Hi-Z

F :

Input
enabled

P51/
INT9

P51

INT9

P51

P52/
INT10

P52

INT10

P52

P53/
INT11/
PPG4

P53

INT11 PPG4

P53

P54/
INT12/
PPG5

P54

INT12 PPG5

P54

P55/
INT13/
TIN2

P55

INT13
TIN2

P55

P56/
INT14/
TIN1

P56

INT14
TIN1

P56

MB91230 Series

Note : P : Port selected, F : Specified function selected

(Continued)

Pin

no.

Pin

name

Port

name

Specified function

name

At initializing

At sleep

mode

At Stop mode

Re-

marks

Input

Output

Input/

Output

Function

name

Reset

initialization

HIZ

P57/
INT15/
TIN0/
ADTG0

P57

INT15
TIN0
ADTG0

P57

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

P :

Retention
of the
immediately
prior state

F :

Input
enabled

P :
Output
Hi-Z

F :
Input 0
enabled

PF3/
TOT3

PF3

TOT3

PF3

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

PF4/
TIN3/
ADTG1

PF4

TIN3
ADTG1

PF4

PD0/
DA0

PD0

DA0

PD0

PD1/
DA1

PD1

DA1

PD1

36 AV

37 AVRH

38 AV

PC0/
AN0

PC0

AN0

PC0

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

PC1/
AN1

PC1

AN1

PC1

PC2/
AN2

PC2

AN2

PC2

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

PC3/
AN3

PC3

AN3

PC3

PC4/
AN4

PC4

AN4

PC4

PC5/
AN5

PC5

AN5

PC5

PC6/
AN6

PC6

AN6

PC6

PC7/
AN7

PC7

AN7

PC7

MB91230 Series

Note : P : Port selected, F : Specified function selected

(Continued)

Pin

no.

Pin

name

Port

name

Specified function

name

At initializing

At sleep

mode

At Stop mode

Re-

marks

Input

Output

Input/

Output

Function

name

Reset

initialization

HIZ

47 V

48 V

3IO

P80/
SEG0

P80

SEG0

P80

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

P :

Output
Hi-Z/
Input 0
fixed

F :

Retention
of the
immediately
prior state

P81/
SEG1

P81

SEG1

P81

P82/
SEG2

P82

SEG2

P82

P83/
SEG3

P83

SEG3

P83

P84/
SEG4

P84

SEG4

P84

P85/
SEG5

P85

SEG5

P85

P86/
SEG6

P86

SEG6

P86

P87/
SEG7

P87

SEG7

P87

P90/
SEG8

P90

SEG8

P90

P91/
SEG9

P91

SEG9

P91

P92/
SEG10

P92

SEG10

P92

P93/
SEG11

P93

SEG11

P93

P94/
SEG12

P94

SEG12

P94

P95/
SEG13

P95

SEG13

P95

P96/
SEG14

P96

SEG14

P96

MB91230 Series

Note : P : Port selected, F : Specified function selected

(Continued)

Pin

no.

Pin

name

Port

name

Specified function

name

At initializing

At sleep

mode

At Stop mode

Re-

marks

Input

Output

Input/

Output

Function

name

Reset

initialization

HIZ

P97/
SEG15

P97

SEG15

P97

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

P :

Output
Hi-Z/
Input 0 fixed

F :

Retention
of the
immediately
prior state

PA0/
SEG16

PA0

SEG16

PA0

PA1/
SEG17

PA1

SEG17

PA1

PA2/
SEG18

PA2

SEG18

PA2

PA3/
SEG19

PA3

SEG19

PA3

PA4/
SEG20

PA4

SEG20

PA4

PA5/
SEG21

PA5

SEG21

PA5

PA6/
SEG22

PA6

SEG22

PA6

PA7/
SEG23

PA7

SEG23

PA7

PB0/
SEG24

PB0

SEG24

PB0

PB1/
SEG25

PB1

SEG25

PB1

75 V

76 V

PB2/
SEG26

PB2

SEG26

PB2

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

P :

Output
Hi-Z/
Input 0
fixed

F :

Retention
of the
immediately
prior state

PB3/
SEG27

PB3

SEG27

PB3

P64/
SEG28

P64

SEG28

P64

open-
drain
pin,
I

20 mA

MB91230 Series

Note : P : Port selected, F : Specified function selected

(Continued)

Pin

no.

Pin

name

Port

name

Specified function

name

At initializing

At sleep

mode

At Stop mode

Re-

marks

Input

Output

Input/

Output

Function

name

Reset

initialization

HIZ

P65/
SEG29

P65

SEG29

P65

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

P :

Output
Hi-Z/
Input 0 fixed

F :

Retention
of the
immediately
prior state

open-
drain
pin,
I

20 mA

P66/
SEG30

P66

SEG30

P66

open-
drain
pin,
I

20 mA

P67/
SEG31

P67

SEG31

P67

open-
drain
pin,
I

20 mA

P70/
COM0

P70

COM0

P70

P71/
COM1

P71

COM1

P71

P72/
COM2

P72

COM2

P72

P73/
COM3

P73

COM3

P73

87 MOD2

88 MOD1

89 MOD0

90 INIT

91 V0

92 V1

93 V2

94 V3

MB91230 Series

Note : P : Port selected, F : Specified function selected

(Continued)

Pin

no.

Pin

name

Port

name

Specified function

name

At initializing

At sleep

mode

At Stop mode

Remarks

Input

Output

Input/

Output

Function

name

Reset

initialization

HIZ

P00/
SIN0

P00

SIN0

P00

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

P01/
SOT0

P01

SOT0

P01

P02/
SCK0

P02

SCK0 P02

P03/
SIN1

P03

SIN1

P03

P04/
SOT1

P04

SOT1

P04

100

P05/
SCK1

P05

SCK1 P05

101

P06/
IC0

P06

IC0

P06

102

P07/
IC1

P07

IC1

P07

103

P10/
INT0

P10

INT0

P10

P :

Retention
of the
immediately
prior state

F : Input

enabled

P : Output

Hi-Z

F : Input

enabled

Pull-up
options
can be
selected

104

P11/
INT1

P11

INT1

P11

Pull-up
options
can be
selected

105 V

106 V

107 X1

108 X0

MB91230 Series

(Continued)

Note : P : Port selected, F : Specified function selected

Pin

no.

Pin

name

Port

name

Specified function

name

At initializing

At sleep

mode

At Stop mode

Remarks

Input

Output

Input/

Output

Function

name

Reset

initialization

HIZ

109

P12/
INT2

P12

INT2

P12

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

P :

Retention
of the
immediately
prior state

F :

Input
enabled

P :

Output
Hi-Z

F :

Input
enabled

Pull-up
options
can be
selected

110

P13/
INT3

P13

INT3

P13

Pull-up
options
can be
selected

111

P14/
INT4

P14

INT4

P14

Pull-up
options
can be
selected

112

P15/
INT5

P15

INT5

P15

Pull-up
options
can be
selected

113

P16/
INT6

P16

INT6

P16

Pull-up
options
can be
selected

114

P17/
INT7

P17

INT7

P17

Pull-up
options
can be
selected

115

P20/
CKI0/
OP0

P20

CKI0 OP0

P20

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

116

P21/
CKI1/
OP1

P21

CKI1 OP1

P21

117

P22/
PWI0/
OP2

P22

PWI0 OP2

P22

118

P23/
PWI1/
OP3

P23

PWI1 OP3

P23

119

P24/
SIN2

P24

SIN2

P24

120

P25/
SOT2

P25

SOT2

P25

MB91230 Series

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

MB91F233, MB91V230

* : This parameter is based on V

0.0 V.

MB91F233L, MB91233L

* : This parameter is based on V

0.0 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter

Symbol

Rating

Unit

Remarks

Min

Max

Power supply voltage*

0.5

6.0

0.5

4.0

3IO

0.5

4.0

Analog power supply voltage*

0.5

4.0

Input voltage*

0.5

Input voltage* (open-drain)

VIND

0.5

Analog pin input voltage*

VIA

0.5

Output voltage*

0.5

Operating ambient temperature

Storage temperature

Tstg

125

Parameter

Symbol

Rating

Unit

Remarks

Min

Max

Power supply voltage*

0.5

4.0

0.5

4.0

3IO

0.5

4.0

Analog power supply voltage*

0.5

4.0

Input voltage*

0.5

Input voltage* (open-drain)

VIND

0.5

Analog pin input voltage*

VIA

0.5

Output voltage*

0.5

Operating ambient temperature

Storage temperature

Tstg

125

MB91230 Series

Recommended Operating Conditions

MB91F233, MB91V230

0.0 V)

MB91F233L, MB91233L

0.0 V)

*1 : The standard power-supply voltage varies with the model of product.

*2 : Only for backup. Set V

3IO.

*3 : V3 must not exceed V

*4 : For the relationships between V

3 and operating frequencies, see section "4. AC Characteristics (4) Operation

Assurance Range".
For the MB91V230, please inquire separately.

Note : For normal use, set V

3IO.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

Parameter

Symbol

Value

Unit

Remarks

Min

Max

Operating ambient temperature

Power supply voltage

4.00

5.25

3.00

3.60

3.00

3.60

2.20

3.60

3IO

3.00

3.60

Analog power supply voltage

3.00

3.60

LCD reference voltage

5.25

Parameter

Symbol

Value

Unit

Remarks

Min

Max

Operating ambient temperature

Power supply voltage

3.00

3.60

3.00

3.60

3.00

3.60

2.20

3.60

3IO

3.00

3.60

Analog power supply voltage

3.00

3.60

LCD reference voltage

3.60

MB91230 Series

DC Characteristics

MB91V230, MB91F233
(V

4.0 V to 5.25 V, V

3IO

3.0 V to 3.6 V, V

0.0 V, Ta

C to

(Continued)

Parameter

Symbol Pin name

Conditions

Value

Unit

Remarks

Min

Typ

Max

Power supply
current

FLASH model normal
operation,
Ta

33 MHz,

CPP

16.5 MHz

FLASH model normal
operation,
Ta

33 MHz,

CPP

33 MHz

CCT

RTC mode,
@Ta

32 kHz

Watch timer,
RTC, LCDC
V

2.4 V

CCH

STOP mode,
@Ta

0 kHz

CCS

SLEEP mode
F

33 MHz,

CPP

16.5 MHz

SLEEP mode
F

33 MHz,

CPP

33 MHz

"H" level input
voltage

0.8

X0A

2.2 V to 3.6 V

0.8

When external
clock is used

"L" level input
voltage

0.2

X0A

2.2 V to 3.6 V

0.4

When external
clock is used

"H" level output
voltage

4 mA

0.5

"L" level output
voltage

4 mA

0.4

P64 to 67 I

20 mA

Input leakage
current

Open-drain output
leakage current

Ileak

MB91230 Series

(Continued)

4.0 V to 5.25 V, V

3IO

3.0 V to 3.6 V, V

0.0 V, Ta

C to

Parameter

Symbol Pin name

Conditions

Value

Unit

Remarks

Min

Typ

Max

LCD division
resistance

LCD

V0 - V1,
V1 - V2,

V2 - V3

100

200

COM0 to COM3
output impedance

VCOM

COM0 to

COM3

V1 to V3

5.0 V

2.5

SEG00 to SEG31
output impedance

VSEG

SEG00 to

SEG31

LCDC leakage
current

LCDC

V0 to V3,

COM0 to

COM3,

SEG00 to

SEG31

MB91230 Series

MB91F233L, MB91233L

3IO

3.0 V to 3.6 V, V

0.0 V, Ta

C to

(Continued)

Parameter

Symbol

Pin

name

Conditions

Value

Unit

Remarks

Min

Typ

Max

Power supply
current

Vcc3

FLASH model normal
operation,
Ta

33 MHz,

CPP

16.5 MHz

FLASH model normal
operation,
Ta

33 MHz,

CPP

33 MHz

ROM model normal
operation,
Ta

33 MHz,

CPP

16.5 MHz

ROM model normal
operation,
Ta

33 MHz,

CPP

33 MHz

CCT

RTC mode,
@Ta

32 kHz

Watch timer,
RTC, LCDC
V

2.4 V

CCH

STOP mode,
@Ta

0 MHz

CCS

SLEEP mode
F

33 MHz,

CPP

16.5 MHz

SLEEP mode
F

33 MHz,

CPP

33 MHz

"H" level input
voltage

0.8

X0A

2.2 V to 3.6 V

0.8

When external
clock is used

"L" level input
voltag

0.15

X0A

2.2 V to 3.6 V

0.4

When external
clock is used

"H" level output
voltage

3.3 V,

2 mA

0.5

MB91230 Series

(Continued)

3IO

3.0 V to 3.6 V, V

0.0 V, Ta

C to

Parameter

Symbol

Pin

name

Conditions

Value

Unit

Remarks

Min

Typ

Max

"L" level output
voltage

2 mA

0.4

P64 to 67 I

10 mA

Input leakage
current

Open-drain output
leakage current

Ileak

LCD division
resistance

LCD

V0 - V1,
V1 - V2,

V2 - V3

100

200

COM0 to COM3
output impedance

VCOM

COM0 to

COM3

V1 to V3

5.0 V

2.5

SEG00 to SEG31
output impedance

VSEG

SEG00 to

SEG31

LCDC leakage
current

LCDC

V0 to V3,

COM0 to

COM3,

SEG00 to

SEG31

MB91230 Series

AC Characteristics

(1) Main clock input standard

(MB91V230, MB91F233 : V

4.0 V to 5.25 V, V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

(MB91F233L, MB91233L : V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

Parameter

Sym-

bol

Pin

name

Condi-

tions

Value

Unit

Remarks

Min

Typ

Max

Input frequency

3.6

4.2

MHz

Input clock cycle

CYL

250

Input clock pulse width

CYL

Input clock rise time
and fall time

At external clock

Internal operating
clock frequency

33.6

MHz

Internal operating
clock cycle time

29.7

Peripheral clock
frequency

CPP

33.6

MHz

Peripheral clock
is derived from
internal operat-
ing clock divided
by 1/1 to 1/16.

Peripheral clock cycle
time

CYCP

29.7

0.8

0.4

0.8

CYL

MB91230 Series

(2) Subclock input standard

(MB91V230, MB91F233 : V

4.0 V to 5.25 V, V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

(MB91F233L, MB91233L : V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

Parameter

Sym-

bol

Pin

name

Condi-

tions

Value

Unit

Remarks

Min

Typ

Max

Input frequency

X0A

32.768

kHz

28.571

32.768

35.714

At external

clock

Input clock cycle

LCYL

28.0

35.0

Input clock pulse width

WLH

LCYL

WLL

LCYL

Input clock rise time
and fall time

LCYL

At external

clock

X0A

0.8

0.4

0.8

LCYL

WLH

WLL

MB91230 Series

(4) PLL oscillation stabilization time (LOCK UP time)

(MB91V230, MB91F233 : V

4.0 V to 5.25 V, V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

(MB91F233L, MB91233L : V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

(5) Reset input standards

(MB91V230, MB91F233 : V

4.0 V to 5.25 V, V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

(MB91F233L, MB91233L : V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

*1 : When turning the power on, keep INIT input until the oscillation circuit provides stable oscillation.

*2 : t

indicates cycle time of CPU operating clock.

Parameter

Symbol

value

Unit

Remarks

Min

Max

PLL oscillation stabilization
(LOCK UP time)

LOCK

500

Time from when the PLL
starts operating to when its
oscillation becomes stable

Parameter

Symbol

Pin

name

Condi-

tions

Value

Unit

Remarks

Min

Max

Reset input time
(at power-on)

INITX

INIT

Reset input time
(other than at power-on)

INITX

INIT

MB91230 Series

(6)UART timing

(MB91V230, MB91F233 : V

4.0 V to 5.25 V, V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

(MB91F233L, MB91233L : V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

* : t

CYCP

represents the cycle time of peripheral operating clock.

Note : This specification applies to clock synchronous mode operation.

Parameter

Symbol

Pin name

Conditions

Value

Unit Remarks

Min

Max

Serial clock cycle time

SCYC

SCK0 to SCK2

Internal shift clock
operation

8 t

CYCP

SCK

SOT delay time

SLOV

SCK0 to SCK2,

SOT0 to SOT2

Valid SIN

SCK

IVSH

SCK0 to SCK2,

SIN0 to SIN2

100

SCK

Valid SIN hold time

SHIX

SCK0 to SCK2,

SIN0 to SIN2

Serial clock "H" pulse width

SHSL

SCK0 to SCK2

External shift clock
operation

4 t

CYCP

Serial clock "L" pulse width

SLSH

SCK0 to SCK2

4 t

CYCP

SCK

SOT delay time

SLOV

SCK0 to SCK2,

SOT0 to SOT2

150

Valid SIN

SCK

IVSH

SCK0 to SCK2,

SIN0 to SIN2

SCK

Valid SIN hold time

SHIX

SCK0 to SCK2,

SIN0 to SIN2

MB91230 Series

(7) Free-run timer clock, Reload timer event input, Up/down counter input, Input capture input,

Interrupt input timing

(MB91V230, MB91F233 : V

4.0 V to 5.25 V, V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

(MB91F233L, MB91233L : V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

* : t

CYCP

indicates peripheral clock cycle time.

(8) A/D trigger, PWI (PWC) input timing

(MB91V230, MB91F233 : V

4.0 V to 5.25 V, V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

(MB91F233L, MB91233L : V

3IO

3.0 V to 3.6 V, V

0.0 V,

C to

* : t

CYCP

indicates peripheral clock cycle time.

Parameter

Symbol

Pin name

Condi-

tions

Value

Unit

Re-

marks

Min

Max

Input pulth width

TIWH

TIWL

CKI0, CKI1

TIN0, TIN1, TIN2

IC0, IC1

AIN0, AIN1
BIN0, BIN1

ZIN0, ZIN1

CYCP

INT0 to INT15

CYCP

Parameter

Symbol

Pin name

Condi-

tions

Value

Unit

Remarks

Min

Max

A/D trigger input (falling)

TADTG

ADTG0
ADTG1

CYCP

PWI (PWC) input (rising)

PWI

PWI0, PWI1

CYCP

TIWH

TIWL

TADTG

TPWI

MB91230 Series

Electrical Characteristics for the A/D Converter

3IO

3.0 V to 3.6 V, V

0.0 V, AVRH

3.0 V to 3.6 V, Ta

C to

*1 : Measured in the CPU sleep state

*2 : It depends on the clock cycle supplied to peripheral resources.

*3 : AVRL pin is only for FLGA package product. AVRL pin is connected to AV

inside the IC on QFP package

product.

*4 : The current when the CPU is in stop mode and the A/D converter is not operaring.

Parameter

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

3.3 V,

At AVRH

3.3 V

At CPU sleep mode

Total error*

5.0

LSB

Nonlinear error*

3.5

LSB

Differential linear error*

2.5

LSB

Zero transition voltage*

2.0

1.0

6.0

LSB

Full transition voltage*

AVRH

5.5

AVRH

1.0

AVRH

3.0

LSB

Conversion time

1.69*

Power supply voltage
(analog

digital)

3.6

Reference power supply current
(between AVRH and AVRL)

470

AVRH

3.0 V,

At AVRL

0.0 V*

At power-down*

Analog input capacitance

Inter-channel disparity

LSB

MB91230 Series

·
·
·
·

About the external impedance of the analog input and its sampling time

A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting
A/D conversion precision.

To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.

If the sampling time cannot be sufficient, connect a capacitor of about 0.1

F to the analog input pin.

About errors

As |AVRH

| becomes smaller, values of relative errors grow larger.

·
·
·
·

Analog input circuit model

Comparator

During sampling : ON

Analog input

Note : The values are reference values.

MB91233L

0.18 k

(Max)

63.0 pF (Max)

MB91F233

0.18 k

(Max)

39.0 pF (Max)

MB91F233L

0.18 k

(Max)

39.0 pF (Max)

100

MB91F233
MB91F233L

MB91233L

(External impedance

0 k

to 100 k

)

Minimum sampling time (

External impedance (k

)

MB91F233
MB91F233L

MB91233L

(External impedance

0 k

to 20 k

)

Minimum sampling time (

External impedance (k

)

·
·
·
·

The relationship between the external impedance and minimum sampling time

MB91230 Series

Electrical Characteristics for the D/A Converter

3IO

3.0 V to 3.6 V, V

0.0 V, Ta

C to

* : The current consumption by this D/A converter varies with input digital code.

This standard value indicates the current consumed when the digital code that maximizes the current consumption
is input.

Flash Memory Write/Erase Characteristics

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at

C).

Parameter

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Nonlinear error

2.0

LSB

When the output is unloaded

Differential linear error

1.0

LSB

When the output is unloaded

Conversion speed

0.6

When load capacitance
(C

) = 20 pF

3.0

When load capacitance
(C

) = 100 pF

Output impedance

2.0

2.9

3.8

Analog current

s conversion, when the

output is unloaded

460*

When the input digital code is
fixed at 7A

or 85

0.1

At power-down

Parameter

Conditions

Value

Unit

Remarks

Min

Typ

Max

Sector erase time

Vcc

5.0 V

Excludes 00

programming

prior erasure

Chip erase time

Vcc

5.0 V

Excludes 00

programming

prior erasure

Byte write time

Vcc

5.0 V

3,600

Not including system-level
overhead time.

Chip write time

Vcc

5.0 V

2.1

Not including system-level
overhead time.

Erase/write cycle

10,000

cycle

Flash data retention time Average Ta

year

MB91230 Series

(Continued)

120-pin Plastic LQFP

(FPT-120P-M05)

Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.

Dimensions in mm (inches) .
Note : The values in parentheses are reference values.

2003 FUJITSU LIMITED F120006S-c-4-5

0.07(.003)

INDEX

16.00±0.20(.630±.008)SQ

14.00±0.10(.551±.004)SQ

120

LEAD No.

(Stand off)

0.10±0.10

(.004±.004)

0.25(.010)

(.024±.006)

0.60±0.15

(.020±.008)

0.50±0.20

(Mounting height)

0~8

Details of "A" part

1.50

+0.20
0.10

+.008
.004

.059

"A"

0.40(.016)

0.16±0.03

(.006±.001)

0.145±0.055

(.006±.002)

0.08(.003)

MB91230 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party's
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0410

2004 FUJITSU LIMITED Printed in Japan

Document Outline

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Document Outline

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