DS07-16504-3E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-Bit Proprietary Microcontroller

CMOS

FR60 MB91350A Series

MB91F355A/F356B/355A/354A/V350A

DESCRIPTION

The FR families are lines of standard single-chip microcontrollers each based on a 32-bit high-performance RISC
CPU, incorporating a variety of I/O resources and bus control features for embedded control applications which
require high CPU performance for

This FR60 family is based on FR30 and FR40 families and enhanced is bus access. The FR60 family is a line of
single-chip oriented microcontrollers incorporating a wealth of peripheral resources.

The FR60 family is optimized for embedded control applications requiring high processing power of the CPU,
such as DVD player, navigation, high performance Fax machine, and printer controls.

FEATURES

FR CPU

· 32-bit RISC, load/store architecture with a five-stage pipeline
· Maximum operating frequency: 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz)
· 16-bit fixed length instructions (basic instructions), 1 instruction per cycle
· Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift

etc.

· Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store in-

structions

(Continued)

PACKAGE

C license

Purchase of Fujitsu I

C components conveys a license under the Philips I

C Patent Rights to use, these components in an I

C system

provided that the system conforms to the I

C Standard Specification as defined by Philips.

176-pin plastic LQFP

(FPT-176P-M02)

MB91350A Series

· Register interlock functions: Facilitating coding in assemblers
· On-chip multiplier supported at the instruction level.

Signed 32-bit multiplication: 5 cycles.
Signed 16-bit multiplication: 3 cycles

· Interrupt (PC, PS save): 6 cycles, 16 priority levels
· Harvard architecture allowing program access and data access to be executed simultaneously
· FR family instruction compatible

Bus Interface

· Maximum operating frequency: 25 MHz
· Capable of up to 24-bit address full output (16 MB of space)
· 8,16-bit data output
· Built-in pre-fetch buffer
· Non-used data and address pin are usable as general I/O port.
· Capable of chip-select signal output for completely independent four areas settable in 64 KB minimum
· Support for various memory interfaces:

SRAM, ROM/Flash,
page mode Flash ROM, page mode ROM

· Basic bus cycle: 2 cycles
· Programmable automatic wait cycle generator capable of inserting wait cycles for each area
· RDY input for external wait cycles
· Support for fly-by transfer for DMA, which enables wait control of independent I/O

Mounted Memory

DMAC (DMA Controller)

· Capable of simultaneous operation of up to 5 channels (3 channels for external

external operation)

· Three transfer sources (external pin, internal peripheral, software) selectable by software. (Transfer can be

started from UART0/1/2.)

· Addressing using 32-bit full addressing mode (increment, decrement, fixed)
· Transfer modes (demand transfer, burst transfer, step transfer, block transfer)
· Support for fly-by transfer (between external I/O and memory)
· Selectable transfer data size: 8, 16, or 32-bit
· Multi-byte transfer enabled (by software)
· DMAC descriptor in IO areas (200

to 240

, 1000

to 1024

)

Bit Search Module (for REALOS)

· Search for the position of the bit 1/0-changed first in 1 word from the MSB

Various Timers

· 4 channels of 16-bit reload timer (including 1 channel for REALOS):

Internal clock frequency selectable from among divisions by 2/8/32 (division by 64/128 selectable only for ch3)

· 16-bit free-running timer: 1 channel.

Output compare module: 8 channels. Input capture module: 4 channels

· 16-bit PPG timer 6 channels

UART

· UART Full duplex double buffer 5 channel
· Selectable parity On/Off
· Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable

(Continued)

Memory

MB91V350A

MB91F355A

MB91F356B

MB91355A

MB91354A

ROM

512 KB

256 KB

512 KB

384 KB

RAM (stack)

16 KB

8 KB

RAM (executable)

16 KB

8 KB

MB91350A Series

(Continued)

· Internal timer for dedicated baud rate
· External clock can be used as transfer clock
· Assorted error detection functions (for parity, frame, and overrun errors)
· 115 Kbps support

SIO

· 3 channels for 8-bit data serial transfer
· Shift clock selectable from among internal three and external one
· Shift direction selectable (transfer from LSB or MSB) selectable

Interrupt Controller

· Total of 17 external interrupt lines (1 nonmaskable interrupt pin and 16 normal interrupt pins available for Wake

Up from STOP)

· interrupt from internal peripheral
· Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt

10. D/A Converter

· 8-bit resolution. 3 channels

11. A/D Converter

· 10-bit resolution. 12 channels
· Casting time for serial/parallel conversion: 1.48

· Conversion mode (single conversion mode, continuous conversion mode)
· Activation source (software, external trigger, peripheral interrupt)

12. Other Interval Timer/Counter

· 8/16-bit up/down counter
· 16-bit PPG timer 5 channels
· Watch dog timer

13.

Bus Interface (400 Kbps supported)

· 1channel master/slave sending and receiving
· Arbitration and clock synchronization

14. I/O Port

· 3 V I/O ports (16 ports shared for external interrupts support 5 V input.)
· Max 126 ports

15. Other Features

· Internal oscillator circuit as clock source, allowing PLL multiplication to be selected
· Provided with INIT as a reset pin (The CPU operates without oscillation stabilization wait interval when the

INIT pin is reset.)

· others, watch-dog timer reset, software reset enable
· Support for stop and sleep modes for low power consumption, capable of saving power during CPU operation

at 32 kHz.

· Gear function
· Built-in time base timer
· Package: LQFP-176 (lead pitch: 0.50 mm)
· CMOS technology(0.35

· Power supply voltage: 3.3 V

0.3 V

MB91350A Series

PIN ASSIGNMENT

(TOP VIEW)

(FPT-176P-M02)

133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176

PG5/SCK5

NMI

X1A

X0A

MD2
MD1
MD0

INIT

PC0/DREQ2

PC1/DACK2

PC2/DSTP2/DEOP2

PB0/DREQ0

PB1/DACK0

PB2/DSTP0/DEOP0

PB3/DREQ1

PB4/DACK1

PB5/DSTP1/DEOP1

PB6/IOWR

PB7/IORD

PA0/CS0
PA1/CS1
PA2/CS2
PA3/CS3

P80/IN0/RDY

P81/IN1/BGRNT

P82/IN2/BRQ

P83/RD

P84/WR0

P85/IN3/WR1

P90/SYSCLK

P91

P92/MCLK

P93

P94/AS

20/D16

21/D17

22/D18

23/D19

24/D20

25/D21

26/D22

27/D23

30/D24

31/D25

32/D26

33/D27

34/D28

35/D29

36/D30

37/D31

P40/A00

P41/A01

P42/A02

P43/A03

P44/A04

P45/A05

P46/A06

P47/A07

P50/A08

P51/A09

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

P60/A16

P61/A17

P62/A18

P63/A19

P64/A20

P65/A21

P66/A22

P67/A23

PG4/SO5

PG3/SI5

PG2/SCK4

PG1/SO4

PG0/SI4

PH5/SCK3

PH4/SO3

PH3/SI3

PH2/SCK2

PH1/SO2

PH0/SI2

PI5/SCK1

PI4/SO1

PI3/SI1

PI2/SCK0

PI1/SO0

PI0/SI0

PJ7/INT15

PJ6/INT14

PJ5/INT13

PJ4/INT12

PJ3/INT11

PJ2/INT10

PJ1/INT9

PJ0/INT8

PK7/INT7/ATG

PK6/INT6/FRCK

PK5/INT5

PK4/INT4

PK3/INT3

PK2/INT2

PK1/INT1

PK0/INT0

PL1/SCL

PL0/SDA

VSS

PM5/SCK7/ZIN1/TRG

PM4/SO7/BIN1/TRG4

PM3/SI7/AIN1/TRG3

PM2/SCK6/ZIN0/TRG

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

PM1/SO6/BIN0/TRG1
PM0/SI6/AIN0/TRG0
PN5/PPG5
PN4/PPG4
PN3/PPG3
PN2/PPG2
PN1/PPG1
PN0/PPG0
V

PO7/OC7
PO6/OC6
PO5/OC5
PO4/OC4
PO3/OC3
PO2/OC2
PO1/OC1
PO0/OC0
PP3/TOT3
PP2/TOT2
PP1/TOT1
PP0/TOT0
V

/AVRL

AVRH
AV

AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
DA2
DA1
DA0
DA

88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45

MB91350A Series

PIN DESCRIPTION

(Continued)

Pin no.

Pin name

Circuit

type

Description

1 to 8

D16 to D23

External data bus bit 16 to bit 23. Enabled in external bus mode.

P20 to P27

Available as a port in external bus 8-bit mode.

9 to 16

D24 to D31

external data bus bit 24 to bit 31. Enabled in external bus mode.

P30 to P37

Usable as port at single chip mode.

19 to 26

A00 to A07

Bits 0 to 7 of external address bus. Enabled in external bus mode.

P40 to P47

Usable as port at single chip mode.

27 to 34

A08 to A15

Bits 8 to 15 of external address bus. Enabled in external bus mode.

P50 to P57

Usable as port at single chip mode.

37 to 41

A16 to A20

Bits 16 to 20 of external address bus. Enabled in external bus mode.

P60 to P64

Available as a port either in single chip mode or with no external address bus in
use.

42 to 44

A21 to A23

Bits 21 to 23 of external address bus. Enabled in external bus mode.

P65 to P67

Available as a port either in single chip mode or with no external address bus in
use.

47 to 48

DA0, DA1

D/A converter output pin.

DA2

D/A converter output pin.

50 to 57 AN0 to AN7

Analog input pin.

58 to 61

AN8 to AN11

Analog input pin.

67 to 70

TOT0 to TOT3

Reload timer output port. This function is enabled when timer output is enabled.

PP0 to PP3

General purpose input/output port. This function is enabled when the timer out-
put function is disabled.

OC0

Output compare pin.

PO0

General purpose I/O. This function is available as a port when the output com-
pare output is not in use.

OC1

Output compare pin.

PO1

General purpose I/O. This function is available as a port when the output com-
pare output is not in use.

OC2

Output compare pin.

PO2

General purpose I/O. This function is available as a port when the output com-
pare output is not in use.

74 to 78

OC3 to OC7

Output compare pin.

PO3 to PO7

General purpose I/O. This function is available as a port when the output com-
pare output is not in use.

PPG0

PPG timer output pin.

PN0

General purpose I/O. This function is available as a port when the PPG timer out-
put is not in use.

MB91350A Series

(Continued)

Pin no.

Pin name

Circuit

type

Description

PPG1

PPG timer output pin.

PN1

General purpose I/O. This function is available as a port when the PPG timer out-
put is not in use.

PPG2

PPG timer output pin.

PN2

General purpose I/O. This function is available as a port when the PPG timer out-
put is not in use.

PPG3

PPG timer output pin.

PN3

General purpose I/O. This function is available as a port when the PPG timer out-
put is not in use.

PPG4

PPG timer output pin.

PN4

General purpose I/O. This function is available as a port when the PPG timer out-
put is not in use.

PPG5

PPG timer output pin.

PN5

General purpose I/O. This function is available as a port when the PPG timer out-
put is not in use.

SI6

Data input for serial I/O6. Since this input is used as required when serial I/O 6 is
in input operation, the port output must remain off unless intentionally turned on.

AIN0

8/16-bit up/down counter input. Since this input is used as required when en-
abled, the port output must remain off unless intentionally turned on.

TRG0

External trigger input for PPG timer0. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.

PM0

General purpose I/O. This function is available a port when the serial I/O, 8/16-
bit up/down counter, and PPG timer outputs are not in use.

SO6

Data output for serial I/O 6. This function is enabled when the serial I/O6 data out-
put is enabled.

BIN0

8/16-bit up/down counter input. Since this input is used as required when en-
abled, the port output must remain off unless intentionally turned on.

TRG1

External trigger input for PPG timer1. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.

PM1

General purpose I/O. This function is available a port when the serial I/O, 8/16-
bit up/down counter, and PPG timer outputs are not in use.

SCK6

Clock input/output for serial I/O 6. This function is enabled when serial I/O6 is us-
ing the external shift clock mode, or serial I/O5 clock output function is enabled.

ZIN0

8/16-bit up/down counter input. Since this input is used as required when en-
abled, the port output must remain off unless intentionally turned on.

TRG2

External trigger input for PPG timer2. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.

PM2

General purpose I/O. This function is available a port when the serial I/O, 8/16-
bit up/down counter, and PPG timer outputs are not in use.

MB91350A Series

(Continued)

Pin no.

Pin name

Circuit

type

Description

SI7

Data input for serial I/O 7. Since this input is used as required when serial I/O 7
is in input operation, the port output must remain off unless intentionally turned
on.

AIN1

8/16-bit up/down counter input. Since this input is used as required when en-
abled, the port output must remain off unless intentionally turned on.

TRG3

External trigger input for PPG timer 3. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.

PM3

General purpose I/O. This function is available a port when the serial I/O, 8/16-
bit up/down counter, and PPG timer outputs are not in use.

SO7

Data output for serial I/O 7. This function is enabled when the serial I/O 7 data
output is enabled.

BIN1

8/16-bit up/down counter input. Since this input is used as required when en-
abled, the port output must remain off unless intentionally turned on.

TRG4

External trigger input for PPG timer 4. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.

PM4

General purpose I/O. This function is available a port when the serial I/O, 8/16-
bit up/down counter, and PPG timer outputs are not in use.

SCK7

Clock input/output for serial I/O5. This function is enabled when serial I/O 7 is us-
ing the external shift clock mode, or serial I/O 5 clock output function is enabled.

ZIN1

8/16-bit up/down counter input. Since this input is used as required when en-
abled, the port output must remain off unless intentionally turned on.

TRG5

External trigger input for PPG timer 5. Since this input is used as required when
enabled, the port output must remain off unless intentionally turned on.

PM5

General purpose I/O. This function is available a port when the serial I/O, 8/16-
bit up/down counter, and PPG timer outputs are not in use.

SDA

Clock input/output pin for I

C bus. This function is enabled when the I

C system

is enabled for operation in standard mode. The port output must remain off unless
intentionally turned on. (Open drain input)

PL0

General purpose input/output port. This function is available as a port when the
I

C system is disabled for operation. (Open drain input)

SCL

Clock input/output pin for I

C bus. This function is enabled when the I

C system

is enabled for operation in standard mode. The port output must remain off unless
intentionally turned on. (Open drain input)

PL1

General purpose input/output port. This function is available as a port when the
I

C system is disabled for operation. (Open drain input)

98 to 103

INT0 to

INT5

External interrupt input. Since this input is used as required when the correspond-
ing external interrupt is enabled, the port output must remain off unless intention-
ally turned on.

PK0 to PK5

General purpose input/output port.

MB91350A Series

(Continued)

Pin no.

Pin name

Circuit

type

Description

104

INT6

External interrupt input. Since this input is used as required when the correspond-
ing external interrupt is enabled, the port output must remain off unless intention-
ally turned on.

FRCK

External clock input pin for freerun timer. Since this input is used as required
when selected as the external clock input for the free running timer, the port out-
put must remain off unless intentionally turned on.

PK6

General purpose input/output port.

105

INT7

External interrupt input. Since this input is used as required when the correspond-
ing external interrupt is enabled, the port output must remain off unless intention-
ally turned on.

ATG

External trigger input for A/D converter. Since this input is used as required when
selected as an A/D activation source, the port output must remain off unless in-
tentionally turned on.

PK7

General purpose input/output port.

106 to

113

INT8 to

INT15

External interrupt input. Since this input is used as required when the correspond-
ing external interrupt is enabled, the port output must remain off unless intention-
ally turned on.

PJ0 to PJ7

General purpose input/output port.

116

SI0

UART0 data input. Since this input is used as required when UART0 is in input
operation, the port output must remain off unless intentionally turned on.

PI0

General purpose input/output port.

117

SO0

UART0 data output. This function is enabled when the UART0 data output is en-
abled.

PI1

General purpose input/output port. This function is enabled when the data output
function of UART0 is disabled.

118

SCK0

UART0 clock input/output pin. This function is enabled either when clock output
enabled or when UART0 inputs the external clock signal.

PI2

General purpose input/output port. This function is enabled when UART0 is not
using the external clock signal with the UART0 clock output function disabled.

119

SI1

UART1 data input. Since this input is used as required when UART1 is in input
operation, the port output must remain off unless intentionally turned on.

PI3

General purpose input/output port.

120

SO1

UART1 data outpu. This function is enabled when the UART1 data output is en-
abled.

PI4

General purpose input/output port. This function is enabled when the data output
function of UART1 is disabled.

121

SCK1

UART1 clock input/output pin. This function is enabled either when clock output
enabled or when UART1 inputs the external clock signal.

PI5

General purpose input/output port. This function is enabled when UART1 is not
using the external clock signal with the UART1 clock output function disabled.

MB91350A Series

(Continued)

Pin no.

Pin name

Circuit

type

Description

122

SI2

UART2 data input. Since this input is used as required when UART2 is in input
operation, the port output must remain off unless intentionally turned on.

PH0

General purpose input/output port.

123

SO2

UART2 data outpu. This function is enabled when the UART2 data output is en-
abled.

PH1

General purpose input/output port. This function is enabled when the data output
function of UART2 is disabled.

124

SCK2

UART2 clock input/output pin. This function is enabled either when the UART2
clock output is enabled or when UART2 inputs the external clock signal.

PH2

General purpose input/output port. This function is enabled when UART2 is not
using the external clock signal with the UART2 clock output function disabled.

125

SI3

UART3 data input. Since this input is used as required when UART3 is in input
operation, the port output must remain off unless intentionally turned on.

PH3

General purpose input/output port.

126

SO3

UART3 data outpu. This function is enabled when the UART3 data output is en-
abled.

PH4

General purpose input/output port. This function is enabled when the data output
function of UART3 is disabled.

127

SCK3

UART0 clock input/output pin. This function is enabled either when the UART3
clock output is enabled or when UART3 inputs the external clock signal.

PH5

General purpose input/output port. This function is enabled when UART3 is not
using the external clock signal with the UART3 clock output function disabled.

128

SI4

UART4 data input. Since this input is used as required when UART4 is in input
operation, the port output must remain off unless intentionally turned on.

PG0

General purpose input/output port.

129

SO4

UART4 data output. This function is enabled when the UART4 data output is en-
abled.

PG1

General purpose input/output port. This function is enabled when the data output
function of UART4 is disabled.

130

SCK4

UART4 clock input/output pin. This function is enabled either when the UART4
clock output is enabled or when UART4 inputs the external clock signal.

PG2

General purpose input/output port. This function is enabled when UART4 is not
using the external clock signal with the UART4 clock output function disabled.

131

SI5

Data input for serial I/O5. Since this input is used as required when serial I/O5 is
in input operation, the port output must remain off unless intentionally turned on.

PG3

General purpose input/output port.

132

SO5

Data output for serial I/O5. This function is enabled when the serial I/O5 data out-
put is enabled.

PG4

General purpose input/output port. This function is enabled when the I/O5 data
output function is disabled.

MB91350A Series

(Continued)

Pin no.

Pin name

Circuit

type

Description

133

SCK5

Clock innput/output for serial I/O5. This function is enabled when serial I/O5 is
using the external shift clock mode, or serial I/O5 clock output function is en-
abled.

PG5

General purpose input/output port. This function is enabled when serial I/O5 is
not using the external shift clock mode with the serial I/O5 clock output function
disabled.

134

NMI

NMI (Non Maskable Interrupt) input

135

X1A

Output clock cycle time. Sub clock

137

X0A

Input clock cycle time. Sub clock

138 to

140

MD2 to

MD0

H, J

2 to 0Mode Pins. The levels applied to these pins set the basic operating mode.
Connect VCC or VSS.
Input circuit configuration:

The production model (masked-ROM model) is type "H".
The Flash ROM model is type "J".

141

Input clock cycle time. Main clock

143

Output clock cycle time. Main clock

144

INIT

External reset input

147

DREQ2

External input for DMA transfer requests. Since this input is used as required
when selected as a DMA start source, the port output must remain off unless in-
tentionally turned on.

PC0

General purpose input/output port.

148

DACK2

External acknowledge output for DMA transfer requests. This function is enabled
when the transfer request acceptance output for DMA is enabled.

PC1

General purpose input/output port. This function is enabled when the transfer re-
quest acceptance output for DMA is enabled.

149

DEOP2

Completion output for DMA external transfer. This function is enabled when the
external transfer end output for DMA is enabled.

DSTP2

Stop input for DMA external transfer. This function is enabled when the external
transfer stop input for DMA is enabled.

PC2

General purpose input/output port. This function is enabled when the external
transfer end output and external transfer stop input for DMA are disabled.

150

DREQ0

External input for DMA transfer requests. Since this input is used as required
when selected as a DMA start source, the port output must remain off unless in-
tentionally turned on.

PB0

General purpose input/output port.

151

DACK0

External acknowledge output for DMA transfer requests. This function is enabled
when the transfer request acceptance output for DMA is enabled.

PB1

General purpose input/output port. This function is enabled when the transfer re-
quest acceptance output for DMA is disabled.

MB91350A Series

(Continued)

Pin no.

Pin name

Circuit

type

Description

152

DEOP0

Completion output for DMA external transfer. This function is enabled when the
external transfer end output for DMA is enabled.

DSTP0

Stop input for DMA external transfer. This function is enabled when the external
transfer stop input for DMA is enabled.

PB2

General purpose input/output port. This function is enabled when the external
transfer end output and external transfer stop input for DMA are disabled.

153

DREQ1

External input for DMA transfer requests. Since this input is used as required
when selected as a DMA start source, the port output must remain off unless in-
tentionally turned on.

PB3

General purpose input/output port.

154

DACK1

External acknowledge output for DMA transfer requests. This function is enabled
when the transfer request acceptance output for DMA is enabled.

PB4

General purpose input/output port. This function is enabled when the external
transfer request acceptance output for DMA is disabled.

155

DEOP1

Completion output for DMA external transfer. This function is enabled when the
external transfer end output for DMA is enabled.

DSTP1

Stop input for DMA external transfer. This function is enabled when the external
transfer stop input for DMA is enabled.

PB5

General purpose input/output port. This function is enabled when the external
transfer end output and external transfer stop input for DMA are disabled.

156

IOWR

Write strobe output for DMA fly-by transfer. This function is enabled when the
DMA fly-by transfer write strobe output is enabled.

PB6

General purpose input/output port. This function is enabled when the DMA fly-by
transfer write strobe output is disabled.

157

IORD

Read storobe output for DMA fly-by transfer. This function is enabled when the
DMA fly-by transfer read strobe output is enabled.

PB7

General purpose input/output port. This function is enabled when the DMA fly-by
transfer read strobe output is disabled.

158

CS0

Chip select 0 output. Enable at external bus mode

PA0

General purpose input/output port. This is enabled at single chip mode.

159

CS1

Chip select 1 output. This function is enabled when the chip select 1 output is en-
abled.

PA1

General purpose input/output port. This function is enabled when the chip select
1 output is disabled.

160

CS2

Chip select 2 output. This function is enabled when the chip select 2 output is en-
abled.

PA2

General purpose input/output port. This function is enabled when the chip select
2 output is disabled.

MB91350A Series

(Continued)

Pin no.

Pin name

Circuit

type

Description

161

CS3

Chip select 3 output. This function is enabled when the chip select 3 output is en-
abled.

PA3

General purpose input/output port. This function is enabled when the chip select
3 output is disabled.

164

RDY

External ready input. The pin has this function when external ready input is en-
abled.

IN0

Input capture input pin. Since this input is used as required when selected as an
input capture input, the port output must remain off unless intentionally turned on.

P80

General purpose input/output port. This function is enabled when external ready
signal input is disabled.

165

BGRNT

Acknowledge output for external bus release. Outputs "L" when the external bus
is released. The pin has this function when output is enabled.

IN1

Input capture input pin. Since this input is used as required when selected as an
input capture input, the port output must remain off unless intentionally turned on.

P81

General purpose input/output port. This function is enabled when external bus re-
lease acknowledge output is disabled.

166

BRQ

External bus release request input. Input "1" to request release of the external
bus. The pin has this function when input is enabled.

IN2

Input capture input pin. Since this input is used as required when selected as an
input capture input, the port output must remain off unless intentionally turned on.

P82

General purpose input/output port. The pin has this function when the external
bus release request input is disabled.

167

External bus read strobe output. It is available in the external bus mode.

P83

General purpose input/output port. This is enabled at single chip mode.

168

WR0

External bus write strobe output. It is available in the external bus mode.

P84

General purpose input/output port. This is enabled at single chip mode.

169

WR1

External bus write strobe output. This function is enabled when WR1 output is en-
abled in external bus mode.

IN3

Input capture input pin. Since this input is used as required when selected as an
input capture input, the port output must remain off unless intentionally turned on.

P85

General purpose input/output port. The pin has this function when the external
bus write-enable output is disabled.

170

SYSCLK

System clock output The pin has this function when system clock output is en-
abled. This outputs the same clock as the external bus operating frequency. (Out-
put halts in stop mode.)

P90

General purpose input/output port. The pin has this function when system clock
output is disabled.

171

P91

General purpose input/output port.

MB91350A Series

(Continued)

Power supply and GND pins

Pin no.

Pin name

Circuit

type

Description

172

MCLK

Memory clock output. This function is enabled when the memory clock output is
enabled. This outputs the same clock as the external bus operating frequency.
(Output halts in sleep/stop mode.)

P92

General purpose input/output port. This function is enabled when the memory
clock output is disabled.

173

P93

General purpose input/output port.

174

Address strobe output. This function is enabled when address strobe output is
enabled.

P94

General purpose input/output port. This function is enabled when address load
output is disabled.

Pin no.

Pin name

Description

17, 35, 65, 79, 93, 96,

114, 136, 145, 162, 175

GND pins. Apply equal potential to all of the pins.

18, 36, 66, 80, 97, 115,

142, 146, 163, 176

3.3 V power supply pin. Apply equal potential to all of the pins.

GND pin for D/A converter

Power supply pin for D/A converter

Analog power supply pin for A/D converter

AVRH

Reference power supply pin for A/D converter

/AVRL

Analog GND pin for A/D converter

MB91350A Series

I/O CIRCUIT TYPE

(Continued)

Type

Circuit type

Remarks

· Oscillation feedback resistance:

approx. 1 M

· Oscillation feedback resistance for

low speed (subclock oscillation):
approx. 7 M

· CMOS level output
· CMOS level input

With standby control

With Pull-up control

Pull-up resistance

approx. 50 k

(Typ)

8 mA

· CMOS level output
· CMOS level hysteresis input

With standby control

With Pull-up control

Pull-up resistance

approx. 50 k

(Typ)

4 mA

Standby control

Clock input

X1A

Standby control

X0A

Clock input

Standby control

Digital input

Digital output

Pull-up control

Standby control

Digital input

Digital output

Pull-up control

MB91350A Series

(Continued)

Type

Circuit type

Remarks

· CMOS level output
· CMOS level hysteresis input

With stand voltage of 5 V

4 mA

· Nch open drain output
· CMOS level hysteresis input

with standby control

With stand voltage of 5 V

15 mA

· Analog input with switch

· CMOS level hysteresis input

with pull-up resistor

Pull-up resistance

approx. 50 k

(Typ)

Digital input

Digital output

Standby control

Digital input

Digital output

Control

Analog input

Digital input

MB91350A Series

HANDLING DEVICES

· Preventing Latchup

Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output
pin or if an above-rating voltage is applied between VCC and VSS. A latchup,if it occurs, significantly increases
the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very
careful not to exceed the maximum rating.

· Treatment of Unused Input Pins

Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pull-
up or pull-down resistor.

· About power supply pins

In products with multiple V

or V

pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to an external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V

and V

pins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1

F between V

and V

near

this device.

· About Crystal oscillator circuit

Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the circuit board so that
X0, X1, X0A, X1A, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located
as close to the device as possible.

It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by
ground plane because stable operation can be expected with such a layout.

· Notes on Using External Clock

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. However, in this case the stop mode(oscillator stop mode) must not be used.
(This is because the X1 pin stops at High level output in STOP mode.)

Using an external clock (normal)

· Clock control block

Take the oscillation stabilization wait time during Low level input to the INIT pin.

Note: STOP mode (oscillation stop mode) cannot be used.

MB91350A Series

· Notes on not using the sub clock

When no oscillator is connected to the X0A and X1A pins, pull down the X0A pin and open the X1A pin.

· Treatment of NC and OPEN pins

Pins marked as NC and OPEN must be left open-circuit.

· Mode pins (MD0 to MD2)

These pins should be connected directly to V

or V

To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and V

or V

is as short as possible and the connection impedance is low.

· Operation at start-up

The INIT pin must be at Low level when the power supply is turned on.

Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the settling time
required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit. (For INIT
via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.)

· About oscillation input at power on

When turning the power on, maintain clock input until the device is released from the oscillation stabilization
wait state.

· Caution on Operations during PLL Clock Mode

Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the
microcontroller may continue to operate at the free-running frequency of the PLL's internal self-oscillating oscil-
lator circuit. Performance of this operation, however, cannot be guaranteed.

· External bus setting

This model guarantees an external bus frequency of 25 MHz.

Setting the base clock frequency to 50 MHz with DIVR1 (external bus base clock division setting register)
initialized sets the external bus frequency also to 50 MHz. Before changing the base clock frequency, set the
external bus frequency not exceeding 25 MHz.

· MCLK and SYSCLK

MCLK and SYSCLK has a difference that MCLK stops in SLEEP/STOP mode but SYSCLK stops only in STOP
mode. Use either depending on each application.

Upon initialization, MCLK becomes invalid (PORT) and SYSCLK becomes valid. To use MCLK, set the port
function register (PFR) to select the use of that clock.

· Pull-up control

Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the "

ELECTRICAL

CHARACTERISTICS 4. AC Characteristics (4) Normal Bus Access Read/Write Operation, (5) Multiplex Bus
Access Read/Write operation and (7) Hold Timing".

Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standby
mode.

MB91350A

OPEN

MB91350A Series

· Sub clock select

Immediately after switching from main clock mode to subclock mode for the clock source, insert at least one
NOP instruction.

· Bit Search Module

The BSD0, BSD1, and BDSC registers are accessed only in words.

· D-bus memory

Do not allocate the code area in memory on the D-bus because no instruction fetch takes place to the D-bus.

Executing an instruction fetch to the D-bus area causes wrong data to be interpreted as code, possibly letting
the device to run out of control.

· Low Power Consumption Mode

To enter the sleep or stop mode, be sure to read the standby control register (STCR) immediately after writing to it.

Precisely, use the following sequence.

Set the I flag, ILM, and ICR to, after returning from standby mode, branch to the interrupt handler having caused
the device to return.

· Switch shared port function

To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR). Note,
however, that bus pins are switched depending on external bus settings.

· Pre-fetch

When accessing a prefetch-enabled little endian area, be sure to use word access (in 32-bit, word length) only.

Byte or halfword access results in wrong data read.

· I/O port access

Ports are accessed only in bytes.

· Built-in RAM

Immediately after a reset is canceled, the internal RAM allocation restricting function is still working, allowing
only 4 KB to be used for data and for program execution irrespective of the on-chip RAM capacity.

(ldi

#0x0b, r0)

(ldi

#_CLKR, r12)

stb

r0, @r12

// sub-clock mode

nop

// Must insert NOP instruction

(ldi

#value_of_standby, r0)

(ldi

#_STCR, r12)

stb

r0, @r12

// set STOP/SLEEP bit

ldub

@r12, r0

// Must read STCR

ldub

@r12, r0

// after reading, go into standby
mode

nop

// Must insert NOP *5

nop

MB91350A Series

· Flash memory

In programming mode, Flash memory cannot be used as an interrupt vector table. A reset is possible.

· Notes on the PS register

As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.

As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.

1. The following operations are performed when the instruction followed by a DIVOU/DIVOS instruction results in:

(a) acceptance of a user interrupt or NMI, (b) single-stepping, or (c) a break at a data event or emulator menu.

The D0 and D1 flags are updated in advance.

An EIT handling routine (user interrupt, NMI, or emulator) is executed.

Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as in (1).

2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed.

The PS register is updated in advance.

An EIT handling routine (user interrupt, NMI, or emulator) is executed.

Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in (1).

MB91350A Series

[Note on debugger]

· Step execution of RETI command

If an interrupt occurs frequently during single-stepping, the corresponding interrupt handling routine is executed
repeatedly. This will prevent the main routine and low-interrupt-level programs from being executed. (Whenever
RETI is single-stepped when interrupts by the timebase timer have been enabled, for example, the timebase
timer routine causes a break at the beginning.)

Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debug-
ging.

· Break function

If the address at which to cause a hardware break (including a event break) is set to the address currently
contained in the system stack pointer or in the area containing the stack pointer, the user program causes a
break after execution of one instruction.

To prevent this, do not set (word) access to the area containing the address in the system stack pointer as the
target of a hardware break (including an event break).

· Internal ROM area

Do not set an area of internal ROM as a DMAC transfer destination.

· Simultaneous occurrences of a software break (INTE instruction) and a user interrupt/NMI

When an INTE instruction and a user interrupt/NMI are accepted simultaneously, the emulator debugger reacts
as follows.

The emulator debugger stops while indicating a location in the user program, which is not a user-specified
breakpoint. (It stops with the beginning of the user interrupt/NMI handling routine indicated.)

The user program cannot be re-executed correctly.

To prevent this problem, follow the instructions below.

When a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may react as
follows.
· The debugger stops pointing to a location other than the programmed breakpoints.
· The halted program is not re-executed correctly.

If this symptom occurs, use a hardware break in place of a hardware break. When using a monitor debugger,
do not set a break at the relevant location.

· A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data

event break to access to the area containing the address of a system stack pointer.

MB91350A Series

BLOCK DIAGRAM

DMAC 5 channels

PORT I/F

1 channel

FR CPU

Bus

Converter

Adapter

ROM/Flash

RAM (Executable)

5 channels

UART

5 channels

U-Timer

X0, X1

MD0 to MD2

INIT

INT0 to INT15

NMI

SI0 to SI4

SO0 to SO4

SCK0 to SCK4

SI5 to SI7

SO5 to SO7

SCK5 to SCK7

DA0 to DA2

, DA

12 channels

A/D

AN0 to AN11

ATG

AVRH, AV

/AVRL

DREQ0 to DREQ2

DACK0 to DACK2

DEOP0/DSTP0 to DEOP2/DSTP2

IOWR

IORD

A23 to A00

D31 to D16

WR1, WR0

RDY

BRQ

BGRNT

SYSCLK

PORT

TRG0 to TRG5
PPG0 to PPG5

FRCK

IN0 to IN3

OC0 to OC7

AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1

SDA
SCL

TOT0 to TOT3

3 channels

SIO

X0A, X1A

Bit search

RAM (Stack)

Clock

control

Interrupt

DMAC (DMA

Controller)

16 channels

External interrupt

3 channels

D/A

8 channels

output compare

4 channels

input capture

16-bit free-run

timer

2 channels

8/16-bit up/down

counter

4 channels

reload timer

6 channels

PPG

External

memory

I/F

Clock timer

MB91F355A

MB91F356B

MB91355A

MB91354A

ROM/Flash

512 KB (Flash)

256 KB (Flash)

512 KB

384 KB

RAM (Stack)

16 KB

RAM (Executable)

8 KB

MB91350A Series

CPU AND CONTROL UNIT

Internal architecture

The FR family CPU is a high performance core based on a RISC architecture while incorporating advanced
instructions for embedded controller applications.

Features

· RISC architecture employed. Basic instructions: Executed at 1 instruction per cycle

· General-purpose registers: 32-bit

16 registers

· 4GB linear memory space
· Multiplier integrated.

32-bit x 32-bit multiplication: 5 cycles.
16-bit x 16-bit multiplication: 3 cycles

· Enhanced interrupt servicing.

Fast response speed (6 cycles).
Multiple interrupts supported.
Level masking (16 levels)

· Enhanced I/O manipulation instructions.

Memory-to-memory transfer instructions, Bit manipulation instructions

· High code efficiency. Basic instruction word length: 16-bit
· Low-power consumption. Sleep mode and stop mode
· Gear function

MB91350A Series

Internal architecture

The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated.

The 32-bit/16-bit bus converter is connected to a 32-bit bus (F-bus), providing an interface between the CPU
and peripheral resources. The Harvard-Princeton bus converter is connected to both of the I-bus and D-bus,
providing an interface between the CPU and the bus controller.

FR CPU

Data

RAM

32-bit

16-bit

bus converter

Harvard

Princeton

bus

converter

D-bus

I-bus

D address

I address

External address

External data

D data

Address

Data

I data

R-bus

F-bus

Peripherals resource

Internal I/O

bus controller

MB91350A Series

Register

General purpose registers

Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory
access pointers for CPU operations.

Of these 16 registers, the registers listed below are intended for special applications, for which some instructions
are enhanced.

R13 : Virtual accumulator
R14 : frame pointer
R15 : Stack pointer

The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 0000 0000

(SSP value).

· PS (Program Status)

This register holds the program status and is divided into the ILM, SCR, and CCR.

The undefined bits in the following illustration are all reserved bits. Reading these bits always returns "0". Writing
to them has no effect.

R12

R13

R14

R15

XXXX XXXX

0 0 0 0 0 0 0 0

32-bit

Initial Value:

Bit position

ILM

SCR

CCR

MB91350A Series

· CCR (Condition Code Register )

· SCR (System Condition code Register )

Flag for step dividing

Stores intermediate data for stepwise multiplication operations.

Step trace trap flag

A flag specifying whether the step trace trap function is enabled or not.
Emulator use step trace trap function. The function cannot be used by the user program when using
the emulator.

· ILM

This register stores the interrupt level mask value. The value in the ILM register is used as the level mask.
Initialized to "15" (01111

) by a reset.

· PC (Program Counter)

The program counter contains the address of the instruction currently being executed.
The initial value after a reset is indeterminate.

: Stack flag. Cleared to "0" by a reset.

: Interrupt enable flag. Cleared to "0" by a reset.

: Negative flag. The initial value after a reset is indeterminate.

: Zero flag. The initial value after a reset is indeterminate.

: Overflow flag. The initial value after a reset is indeterminate.

: Carry flag. The initial value after a reset is indeterminate.

Initial Value:

- - 00XXXX

CCR

Initial Value:

XX0

SCR

Initial Value:

01111

ILM

ILM4 ILM3 ILM2 ILM1 ILM0

Initial Value:

XXXXXXXX

MB91350A Series

· TBR (Table Base Register)

The table base register contains the start address of the vector table used for servicing EIT events.
The initial value after a reset is 000FFC00

· RP (Return Pointer)

The return pointer contains the address to which to return from a subroutine.
When the CALL instruction is executed, the value in the PC is transferred to the RP.
When the RET instruction is executed, the value in the RP is transferred to the PC.
The initial value after a reset is indeterminate.

· SSP (System Stack Pointer)

The SSP is the system stack pointer and functions as R15 when the S flag is "0".
The SSP can be explicitly specified.
The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event
occurs.
The initial value after a reset is 00000000

· USP (User Stack Pointer)

The USP is the user stack pointer and functions as R15 when the S flag is "1".
The SSP can be explicitly specified.
The initial value after a reset is indeterminate.
This pointer cannot be used by the RETI instruction.

Initial Value:

0 0 0 FFC0 0

TBR

Initial Value:

XXXXXXXX

Initial Value:

0 0 0 0 0 0 0 0

SSP

Initial Value:

XXXXXXXX

USP

MB91350A Series

MODE SETTINGS

The FR family uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode.

Mode Pins

The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.

Values other than those listed in the table are prohibited.

Mode Register (MODR)

The data written to the mode register at 000F FFF8

using mode vector fetch is called mode data.

After an operation mode has been set in the mode register (MODR), the device operates in the operation mode.

The mode register is set by any reset source. User programs cannot write data to the mode register.

Note : Conventionally the FR family has nothing at addresses (0000 07FF

) in the mode register.

<Register description>

[bit 7 to bit 3] Reserved bit

Be sure to set this bit to "00000". Operation is not guaranteed when any value other than "00000" is set.

[bit 2] ROMA (internal ROM enable bit)

The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas.

Mode Pins

Mode name

Reset vector

access area

Remarks

MD2 MD1 MD0

Internal ROM mode vector

Internal

External ROM mode vector

External

The bus width is specified by the mode register.

ROMA

function

Remarks

External ROM mode

Internal F-bus RAM is valid; the area (80000

to 100000

) of internal ROM is used

as an external area.

Internal ROM mode Internal F-bus RAM and F-bus ROM become valid.

MODR

Initial Value

000F FFF8

XXXXXXXX

ROMA

WTH1

WTH0

Operation mode setting bits

MB91350A Series

MEMORY SPACE

Memory space

The FR family has 4 GB of logical address space (2

addresses) available to the CPU by linear access.

· Direct Addressing Areas

The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The size of directly addressable areas depends on the length of the data being accessed as shown below.

byte data access

: 000

to 0FF

half word data access : 000

to 1FF

word data access

: 000

to 3FF

Memory Map

Memory map of MB91F355A/MB91355A

· Each mode is set depending on the mode vector fetch after INIT is negated.
· The MB91V350A uses the area of 512 KB of internal ROM as emulation RAM in the MB91355A memory map.

The internal RAM (Instruction) has been expanded from 8 KB to 16 KB.

· The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the

available area is updated, the instruction must be followed by at least 1 NOP instruction.

0008 0000

0000 0000

0000 0400

0001 0000

0003 E000

0004 0000

0004 4000

0005 0000

0010 0000

FFFF FFFF

I/O

Single chip mode

Internal ROM

external bus mode

Access

disallowed

Direct
addressing area

Refer to "3. I/O Map"

Built-in RAM 8 KB

(Executable)

Built-in RAM

512 KB

Access

disallowed

Access

disallowed

Built-in RAM 8 KB

(

Executable

)

Built-in RAM

512 KB

External area

Access

disallowed

Built-in RAM 8 KB

(Executable)

External area

Built-in RAM 16 KB

(Stack)

Access

disallowed

External ROM

external bus mode

External area

Access

disallowed

Access

disallowed

Built-in RAM 16 KB

(Stack)

Built-in RAM 16 KB

(Stack)

MB91350A Series

Memory Map of MB91354A

· Each mode is set depending on the mode vector fetch after INIT is negated.
· The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the

available area is updated, the instruction must be followed by at least 1 NOP instruction.

0008 0000

0000 0000

0000 0400

0001 0000

0003 E000

0004 0000

0004 2000

0005 0000

0010 0000

FFFF FFFF

I/O

000A 0000

Single chip mode

Internal ROM

external bus mode

Access

disallowed

Direct
addressing area

Refer to "3. I/O Map"

Built-in RAM 8 KB

(Executable)

Built-in ROM

384 KB

Access

disallowed

Access

disallowed

Built-in RAM 8 KB

(Executable)

Built-in ROM

384 KB

External area

Access

disallowed

Built-in RAM 8 KB

(Executable)

External area

Built-in RAM 8 KB

(Stack)

Access

disallowed

External ROM

external bus mode

External area

Access

disallowed

Access

disallowed

Built-in RAM 8 KB

(Stack)

Built-in RAM 8 KB

(Stack)

Access

disallowed

MB91350A Series

Memory Map of MB91356B

· Each mode is set depending on the mode vector fetch after INIT is negated.
· The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the

available area is updated, the instruction must be followed by at least 1 NOP instruction.

0008 0000

0000 0000

0000 0400

0001 0000

0003 E000

0004 0000

0004 4000

0005 0000

0010 0000

FFFF FFFF

I/O

000C 0000

Single chip mode

Internal ROM

external bus mode

Access

disallowed

Direct
addressing area

Refer to "3. I/O Map"

Built-in RAM 8 KB

(Executable)

Built-in ROM

256 KB

Access

disallowed

Access

disallowed

Built-in RAM 8 KB

(Executable)

Built-in ROM

256 KB

External area

Access

disallowed

Built-in RAM 8 KB

(Executable)

External area

Built-in RAM 16 KB

(Stack)

Access

disallowed

External ROM

external bus mode

External area

Access

disallowed

Access

disallowed

Built-in RAM 16 KB

(Stack)

Built-in RAM 16 KB

(Stack)

Access

disallowed

MB91350A Series

I/O Map

This shows the location of the various peripheral resource registers in the memory space.

(How to read the table)

Note : Initial values of register bits are represented as follows :

(Continued)

"1" : Initial value is "1".

"0" : Initial Value: "0".

"X" : Initial value is "X".

" : No physical register at this location

Address

Register

Block

diagram

000000

PDR2 [R/W] B

XXXXXXXX

PDR3 [R/W] B

XXXXXXXX

T-unit

Port Data

000004

PDR4 [R/W] B

XXXXXXXX

PDR5 [R/W] B

XXXXXXXX

PDR6 [R/W] B

XXXXXXXX

000008

PDR8 [R/W] B

- - XXXXXX

PDR9 [R/W] B

- - - XXXXX

PDRA [R/W] B

- - - - XXXX

PDRB [R/W] B

XXXXXXXX

00000C

PDRC [R/W] B

- - - - - XXX

000010

PDRG[R/W] B

- - XXXXXX

PDRH [R/W] B

- - XXXXXX

PDRI [R/W] B

- - XXXXXX

PDRJ [R/W] B

XXXXXXXX

R-bus

Port Data

000014

PDRK [R/W] B

XXXXXXXX

PDRL [R/W] B

- - - - - - XX

PDRM [R/W] B

- - XXXXXX

PDRN [R/W] B

- - XXXXXX

000018

PDRO [R/W] B

XXXXXXXX

PDRP [R/W] B

- - - - XXXX

00001C

000020

Reserved

000024

SMCS5 [R/W] B, H*

00000010 - - - - 00 - -

SES5 [R/W] B*

- - - - - - 00

SDR5 [R/W] B*

XXXXXXXX

SIO 5*

Address

Register

Block diagram

000000

PDR0 [R/W] B

XXXXXXXX

PDR1 [R/W] B

XXXXXXXX

PDR2 [R/W] B

XXXXXXXX

PDR3 [R/W] B

XXXXXXXX

T-unit

Port Data Register

Read/write attribute, Access unit

(B : Byte, H : Half Word, W : Word)

Initial value after a reset

Location of left-most register (When using word access, the register in column
1 is in the MSB side of the data.)

MB91350A Series

(Continued)

Address

Register

Block

diagram

000028

SMCS6 [R/W] B, H

00000010 - - - - 00 - -

SES6 [R/W] B

- - - - - - 00

SDR6 [R/W] B

XXXXXXXX

SIO 6

00002C

SMCS7 [R/W] B, H

00000010 - - - - 00 - -

SES7 [R/W] B

- - - - - - 00

SDR7 [R/W] B

XXXXXXXX

SIO 7

000030

CDCR5 [R/W] B

0---1111

SIO Prescaler

000034

CDCR6 [R/W] B

0 - - - 1111

CDCR7 [R/W] B

0 - - - 1111

SIO Prescaler

6, 7

000038

SRCL5 [W] B

- - - - - - - -

SRCL6 [W] B

- - - - - - - -

SRCL7 [W] B

- - - - - - - -

SIO5 to SIO7

00003C

Reserved

000040

EIRR0 [R/W] B, H, W

00000000

ENIR0 [R/W] B, H, W

00000000

ELVR0 [R/W] B, H, W

00000000

Ext int

(INT0 to INT7)

000044

DICR [R/W] B, H, W

- - - - - - - 0

HRCL [R/W] B, H, W

0 - - 11111

DLYI/I-unit

000048

TMRLR [W] H, W

XXXXXXXX XXXXXXXX

TMR [R] H, W

XXXXXXXX XXXXXXXX

Reload Timer 0

00004C

TMCSR [R/W] B, H, W

- - - - 0000 00000000

000050

TMRLR [W] H, W

XXXXXXXX XXXXXXXX

TMR [R] H, W

XXXXXXXX XXXXXXXX

Reload Timer 1

000054

TMCSR [R/W] B, H, W

- - - - 0000 00000000

000058

TMRLR [W] H, W

XXXXXXXX XXXXXXXX

TMR [R] H, W

XXXXXXXX XXXXXXXX

Reload Timer 2

00005C

TMCSR [R/W] B, H, W

- - - - 0000 00000000

000060

SSR [R/W] B, H, W

00001000

SIDR/SODR [R/W]

B, H, W

XXXXXXXX

SCR [R/W] B, H, W

00000100

SMR [R/W] B, H, W

00 - - 0 - - -

UART0

000064

UTIM [R] H (UTIMR [W] H)

00000000 00000000

DRCL [W] B

- - - - - - - -

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 0

000068

SSR [R/W] B, H, W

00001000

SIDR/SODR [R/W]

B, H, W

XXXXXXXX

SCR [R/W] B, H, W

00000100

SMR [R/W] B, H, W

00 - - 0 - - -

UART1

00006C

UTIM [R] H (UTIMR [W] H)

00000000 00000000

DRCL [W] B

- - - - - - - -

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 1

000070

SSR [R/W] B, H, W

00001000

SIDR/SODR [R/W]

B, H, W

XXXXXXXX

SCR [R/W] B, H, W

00000100

SMR [R/W] B, H, W

00 - - 0 - - -

UART2

000074

UTIM [R] H (UTIMR [W] H)

00000000 00000000

DRCL [W] B

- - - - - - - -

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 2

MB91350A Series

(Continued)

Address

Register

Block

diagram

000078

ADCS2 [R/W]B, H, W

X000XX00

ADCS1 [R/W]B, H, W

000X0000

ADCT [R/W] H, W

XXXXXXXX_XXXXXXXX

A/D

converter:

Successive

approxima-

tion

00007C

ADTH0 [R] B, H, W

XXXXXXXX

ADTL0 [R] B, H, W

000000XX

ADTH1 [R] B, H, W

XXXXXXXX

ADTL1 [R] B, H, W

000000XX

000080

ADTH2 [R] B, H, W

XXXXXXXX

ADTL2 [R] B, H, W

000000XX

ADTH3 [R] B, H, W

XXXXXXXX

ADTL3 [R] B, H, W

000000XX

000084

DACR2 [R/W] B, H, W

- - - - - - - 0

DACR1 [R/W] B, H, W

- - - - - - - 0

DACR0 [R/W] B, H, W

- - - - - - - 0

D/A

Converter

000088

DADR2 [R/W] B, H, W

XXXXXXXX

DADR1 [R/W] B, H, W

XXXXXXXX

DADR0 [R/W] B, H, W

XXXXXXXX

00008C

Reserved

000090

Reserved

000094

IBCR [R/W] B, H, W

00000000

IBSR [R] B, H, W

00000000

ITBA [R/W] B, H, W

- - - - - - 00 00000000

interface

000098

ITMK [R/W] B, H, W

00 - - - - 11 11111111

ISMK [R/W] B, H, W

01111111

ISBA [R/W] B, H, W

- 0000000

00009C

IDAR [R/W] B, H, W

00000000

ICCR [R/W] B, H, W

0 - 011111

IDBL [R/W] B, H, W

- - - - - - - 0

0000A0

Reserved

0000A4

0000A8

TMRLR [W] H, W

XXXXXXXX XXXXXXXX

TMR [R] H, W

XXXXXXXX XXXXXXXX

Reload

Timer 3

0000AC

TMCSR [R/W] B, H, W

- - - - 0000 00000000

0000B0

RCR1 [W] B, H, W

00000000

RCR0 [W] B, H, W

00000000

UDCR1 [R] B, H, W

00000000

UDCR0 [R] B, H, W

00000000

8/16-bit

Up/Down

Counter

0, 1

0000B4

CCRH0 [R/W] B, H, W

00001000

CCRL0 [R/W] B, H, W

00001000

CSR0 [R/W] B, H, W

00000000

0000B8

CCRH1 [R/W] B, H, W

00001000

CCRL1 [R/W] B, H, W

00001000

CSR1 [R/W] B, H, W

00000000

0000BC

Reserved

0000C0

SSR [R/W] B, H, W

00001000

SIDR/SODR [R/W]

B, H, W

XXXXXXXX

SCR [R/W] B, H, W

00000100

SMR [R/W] B, H, W

00 - - 0 - - -

UART3

0000C4

UTIM [R] H (UTIMR [W] H)

00000000 00000000

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 3

0000C8

SSR [R/W] B, H, W

00001000

SIDR/SODR [R/W]

B, H, W

XXXXXXXX

SCR [R/W] B, H, W

00000100

SMR [R/W] B, H, W

00 - - 0 - - -

UART4

MB91350A Series

(Continued)

Address

Register

Block

diagram

0000CC

UTIM [R] H (UTIMR [W] H)

00000000 00000000

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 4

0000D0

EIRR1 [R/W] B, H, W

00000000

ENIR1 [R/W]B, H, W

00000000

ELVR1 [R/W] B, H, W

00000000

Ext int

(INT8-15)

0000D4

TCDT [R/W] H, W

00000000 00000000

TCCS [R/W] B, H, W

00000000

16-bit

Free run

Timer

0000D8

IPCP1 [R] H, W

XXXXXXXX XXXXXXXX

IPCP0 [R] H, W

XXXXXXXX XXXXXXXX

16-bit ICU

0000DC

IPCP3 [R] H, W

XXXXXXXX XXXXXXXX

IPCP2 [R] H, W

XXXXXXXX XXXXXXXX

0000E0

ICS23 [R/W] B, H, W

00000000

ICS01 [R/W] B, H, W

00000000

0000E4

OCCP1 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP0 [R/W] H, W

XXXXXXXX XXXXXXXX

16-bit

OCU

0000E8

OCCP3 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP2 [R/W] H, W

XXXXXXXX XXXXXXXX

0000EC

OCCP5 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP4 [R/W] H, W

XXXXXXXX XXXXXXXX

0000F0

OCCP7 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP6 [R/W] H, W

XXXXXXXX XXXXXXXX

0000F4

OCS23 [R/W] B, H, W

1110110 00001100

OCS01 [R/W] B, H, W

1110110 00001100

0000F8

OCS67 [R/W] B, H, W

1110110 00001100

OCS45 [R/W] B, H, W

1110110 00001100

0000FC

Reserved

000100

000114

Reserved

000118

GCN10 [R/W] H

00110010_00010000

GCN20 [R/W] B

00000000

PPG

Control 0

00011C

Reserved

000120

PTMR0 [R] H, W

11111111_11111111

PCSR0 [W] H, W

XXXXXXXX_XXXXXXXX

PPG0

000124

PDUT0 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH0 [R/W] B, H, W

00000000

PCNL0 [R/W] B, H, W

00000000

000128

PTMR1 [R] H, W

11111111_11111111

PCSR1 [W] H, W

XXXXXXXX_XXXXXXXX

PPG1

00012C

PDUT1 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH1 [R/W] B, H, W

00000000

PCNL1 [R/W] B, H, W

00000000

MB91350A Series

(Continued)

Address

Register

Block

diagram

000130

PTMR2 [R] H, W

11111111_11111111

PCSR2 [W] H, W

XXXXXXXX_XXXXXXXX

PPG2

000134

PDUT2 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH2 [R/W] B, H, W

00000000

PCNL2 [R/W] B, H, W

00000000

000138

PTMR3 [R] H, W

11111111_11111111

PCSR3 [W] H, W

XXXXXXXX_XXXXXXXX

PPG3

00013C

PDUT3 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH3 [R/W] B, H, W

00000000

PCNL3[R/W] B, H, W

00000000

000140

PTMR4 [R] H, W

11111111_11111111

PCSR4 [W] H, W

XXXXXXXX_XXXXXXXX

PPG4

000144

PDUT4 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH4 [R/W] B, H, W

00000000

PCNL4 [R/W] B, H, W

00000000

000148

PTMR5 [R] H, W

11111111_11111111

PCSR5 [W] H, W

XXXXXXXX_XXXXXXXX

PPG5

00014C

PDUT5 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH5 [R/W] B, H, W

00000000

PCNL5 [R/W] B, H, W

00000000

000150

0001FC

Reserved

000200

DMACA0 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMAC

000204

DMACB0 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000208

DMACA1 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

00020C

DMACB1 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000210

DMACA2 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

000214

DMACB2 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000218

DMACA3 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

00021C

DMACB3 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000220

DMACA4 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

000224

DMACB4 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000228

MB91350A Series

(Continued)

Address

Register

Block

diagram

00022C

00023C

Reserved

000240

DMACR [R/W] B

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

DMAC

000244

00027C

Reserved

000280

FRLR [R/W] B, H, W

- - - - - - 01*

F-bus RAM

capacity limit

000284

00038C

Reserved

000390

DRLR [R/W] B, H, W

- - - - - - 01*

D-bus RAM

capacity limit

000394

0003EC

Reserved

0003F0

BSD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search

Module

0003F4

BSD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8

BSDC [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FC

BSRR [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000400

DDRG[R/W] B

- - 000000

DDRH [R/W] B

- - 000000

DDRI [R/W] B

- - 000000

DDRJ [R/W] B

00000000

R-bus

Data

Direction

000404

DDRK [R/W] B

00000000

DDRL [R/W] B

- - - - - - 00

DDRM [R/W] B

- - 000000

DDRN [R/W] B

- - 000000

000408

DDRO [R/W] B

00000000

DDRP [R/W] B

- - - - 0000

00040C

000410

PFRG [R/W] B

- - 00 - 00 -

PFRH [R/W] B

- - 00 - 00 -

PFRI [R/W] B

- - 00 - 00 -

R-bus

Port Function

000414

________

PFRL [R/W] B

- - - - - - 00

PFRM [R/W] B

- - 00 - 00 -

PFRN [R/W] B

- - 000000

000418

PFRO [R/W] B

00000000

PFRP [R/W] B

- - - - 0000

00041C

Reserved

MB91350A Series

(Continued)

Address

Register

Block

diagram

000420

PCRG [R/W] B

- - 000000

PCRH [R/W] B

- - 000000

PCRI [R/W] B

- - 000000

R-bus

Pull-up

Control

000424

PCRM [R/W] B

- - 000000

PCRN [R/W] B

- - 000000

000428

PCRO [R/W] B

00000000

PCRP [R/W] B

- - - - 0000

00042C

00043C

Reserved

000440

ICR00 [R/W] B, H, W

- - - 11111

ICR01 [R/W] B, H, W

- - - 11111

ICR02 [R/W] B, H, W

- - - 11111

ICR03 [R/W] B, H, W

- - - 11111

Interrupt

Control unit

000444

ICR04 [R/W] B, H, W

- - - 11111

ICR05 [R/W] B, H, W

- - - 11111

ICR06 [R/W] B, H, W

- - - 11111

ICR07 [R/W] B, H, W

- - - 11111

000448

ICR08 [R/W] B, H, W

- - - 11111

ICR09 [R/W] B, H, W

- - - 11111

ICR10 [R/W] B, H, W

- - - 11111

ICR11 [R/W] B, H, W

- - - 11111

00044C

ICR12 [R/W] B, H, W

- - - 11111

ICR13 [R/W] B, H, W

- - - 11111

ICR14 [R/W] B, H, W

- - - 11111

ICR15 [R/W] B, H, W

- - - 11111

000450

ICR16 [R/W] B, H, W

- - - 11111

ICR17 [R/W] B, H, W

- - - 11111

ICR18 [R/W] B, H, W

- - - 11111

ICR19 [R/W] B, H, W

- - - 11111

000454

ICR20 [R/W] B, H, W

- - - 11111

ICR21 [R/W] B, H, W

- - - 11111

ICR22 [R/W] B, H, W

- - - 11111

ICR23 [R/W] B, H, W

- - - 11111

000458

ICR24 [R/W] B, H, W

- - - 11111

ICR25 [R/W] B, H, W

- - - 11111

ICR26 [R/W] B, H, W

- - - 11111

ICR27 [R/W] B, H, W

- - - 11111

00045C

ICR28 [R/W] B, H, W

- - - 11111

ICR29 [R/W] B, H, W

- - - 11111

ICR30 [R/W] B, H, W

- - - 11111

ICR31 [R/W] B, H, W

- - - 11111

000460

ICR32 [R/W] B, H, W

- - - 11111

ICR33 [R/W] B, H, W

- - - 11111

ICR34 [R/W] B, H, W

- - - 11111

ICR35 [R/W] B, H, W

- - - 11111

000464

ICR36 [R/W] B, H, W

- - - 11111

ICR37 [R/W] B, H, W

- - - 11111

ICR38 [R/W] B, H, W

- - - 11111

ICR39 [R/W] B, H, W

- - - 11111

000468

ICR40 [R/W] B, H, W

- - - 11111

ICR41 [R/W] B, H, W

- - - 11111

ICR42 [R/W] B, H, W

- - - 11111

ICR43 [R/W] B, H, W

- - - 11111

00046C

ICR44 [R/W] B, H, W

- - - 11111

ICR45 [R/W] B, H, W

- - - 11111

ICR46 [R/W] B, H, W

- - - 11111

ICR47 [R/W] B, H, W

- - - 11111

000470

00047C

000480

RSRR [R/W] B, H, W

10000000

STCR [R/W] B, H, W

00110011

TBCR [R/W] B, H, W

00XXXX00

CTBR [W] B, H, W

XXXXXXXX

Clock

Control unit

000484

CLKR [R/W] B, H, W

00000000

WPR [W] B, H, W

XXXXXXXX

DIVR0 [R/W] B, H, W

00000011

DIVR1 [R/W] B, H, W

00000000

000488

OSCCR [R/W] B

XXXXXXX0

MB91350A Series

(Continued)

Address

Register

Block

diagram

00048C

WPCR [R/W] B

00 - - - 000

Clock timer

000490

OSCR [R/W] B

000 - - XX0

Main oscillation

stabilization

timer

000494

RSTOP0 [W] B

00000000

RSTOP1 [W] B

00000000

RSTOP2 [W] B

00000000

RSTOP3 [W] B

- - - - - 000

Peripheral stop

control

000498

Reserved

00049C

0005FC

Reserved

000600

DDR2 [R/W] B

00000000

DDR3 [R/W] B

00000000

T-unit

Data Direction

000604

DDR4 [R/W] B

00000000

DDR5 [R/W] B

00000000

DDR6 [R/W] B

00000000

000608

DDR8 [R/W] B

- - 000000

DDR9 [R/W] B

- - - 00000

DDRA [R/W] B

- - - - 0000

DDRB [R/W] B

00000000

00060C

DDRC [R/W] B

- - - - - 000

000610

T-unit

Port Function

000614

PFR6 [R/W] B

11111111

000618

PFR8 [R/W] B

- - 1 - - 0 - -

PFR9 [R/W] B

- - - 010 - 1

PFRA [R/W] B

- - - - 1111

PFRB1 [R/W] B

00000000

00061C

PFRB2 [R/W] B

00 - - - - 00

PFRC [R/W] B

- - - 00000

000620

PCR2 [R/W] B

00000000

PCR3 [R/W] B

00000000

T-unit

Pull-up Control

000624

PCR4 [R/W] B

00000000

PCR5 [R/W] B

00000000

PCR6 [R/W] B

00000000

000628

PCR8 [R/W] B

--000000

PCR9 [R/W] B

00000000

PCRA [R/W] B

00000000

PCRB [R/W] B

00000000

00062C

PCRC [R/W] B

-----000

000630

00063C

Reserved

000640

ASR0 [R/W] H, W

00000000 00000000

ACR0 [R/W] B, H, W

1111XX00 00000000

T-unit

000644

ASR1 [R/W] H, W

00000000 00000000

ACR1 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000648

ASR2 [R/W] H, W

00000000 00000000

ACR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

MB91350A Series

(Continued)

Address

Register

Block

diagram

00064C

ASR3 [R/W] H, W

00000000 00000000

ACR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

T-unit

000650

ASR4 [R/W] H, W

00000000 00000000

ACR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000654

ASR5 [R/W] H, W

00000000 00000000

ACR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000658

ASR6 [R/W] H, W

00000000 00000000

ACR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

00065C

ASR7 [R/W] H, W

00000000 00000000

ACR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000660

AWR0 [R/W] B, H, W

01111111 11111111

AWR1 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000664

AWR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000668

AWR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

00066C

AWR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000670

000674

000678

IOWR0 [R/W] B, H, W

XXXXXXXX

IOWR1 [R/W] B, H, W

XXXXXXXX

IOWR2 [R/W] B, H, W

XXXXXXXX

00067C

000680

CSER [R/W] B, H, W

00000001

TCR [W] B, H, W

0000XXXX

000684

000AFC

Reserved

000B00

ESTS0 [R/W]

X0000000

ESTS1 [R/W]

XXXXXXXX

ESTS2 [R]

1XXXXXXX

DSU

(Evalua-
tion chip

only)

000B04

ECTL0 [R/W]

0X000000

ECTL1 [R/W]

00000000

ECTL2 [W]

000X0000

ECTL3 [R/W]

00X00X11

000B08

ECNT0 [W]

XXXXXXXX

ECNT1 [W]

XXXXXXXX

EUSA [W]
XXX00000

EDTC [W]

0000XXXX

MB91350A Series

(Continued)

Address

Register

Block

diagram

000B0C

EWPT [R]

00000000 00000000

DSU

(Evaluation

chip only)

000B10

EDTR0 [W]

XXXXXXXX XXXXXXXX

EDTR1 [W]

XXXXXXXX XXXXXXXX

000B14

000B1C

000B20

EIA0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B24

EIA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B28

EIA2 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B2C

EIA3 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B30

EIA4 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B34

EIA5 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B38

EIA6 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B3C

EIA7 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B40

EDTA [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B44

EDTM [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B48

EOA0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B4C

EOA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B50

EPCR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B54

EPSR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B58

EIAM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B5C

EIAM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B60

EOAM0/EODM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

MB91350A Series

(Continued)

Address

Register

Block

diagram

000B64

EOAM1/EODM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DSU

(Evaluation

chip only)

000B68

EOD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B6C

EOD1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B70

000BFC

Reserved

000C00

Interrupt

Control unit

000C04

000C14

R-bus test

000C18

000FFC

Reserved

001000

DMASA0 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMAC

001004

DMADA0 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001008

DMASA1 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

00100C

DMADA1 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001010

DMASA2 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001014

DMADA2 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001018

DMASA3 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

00101C

DMADA3 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001020

DMASA4 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001024

DMADA4 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001028

001FFC

Reserved

MB91350A Series

(Continued)

*1 : Test register access barred

*2 : The lower 16-bit (DTC(15: 0)) of DMACA0 to DMACA4 cannot be accessed in byte.

*3 : The available area of internal RAM is restricted by the function described in 6-209 immediately after a reset is

canceled. When the setting of the available area is updated, the instruction must be followed by at least 1 NOP
instruction.

Address

Register

Block

diagram

007000

FLCR [R/W]

0110X000

Flash

memory

007004

FLWC [R/W]

00010011

007008

00700C

007010

007014

0070FF

Reserved

MB91350A Series

VECTOR TABLE

(Continued)

Interrupt source

Interrupt

number

Interrupt

level

Offset

TBR default

address

Reset

3FC

000FFFFC

Mode vector

3F8

000FFFF8

System reserved

3F4

000FFFF4

System reserved

3F0

000FFFF0

System reserved

3EC

000FFFEC

System reserved

3E8

000FFFE8

System reserved

3E4

000FFFE4

Coprocessor absent trap

3E0

000FFFE0

Coprocessor error trap

3DC

000FFFDC

INTE instruction

3D8

000FFFD8

Instruction break exception

3D4

000FFFD4

Operand break trap

3D0

000FFFD0

Step trace trap

3CC

000FFFCC

NMI request (tool)

3C8

000FFFC8

Undefined instruction exception

3C4

000FFFC4

NMI request

15 (F

)

fixed15

3C0

000FFFC0

External interrupt 0

ICR00

3BC

000FFFBC

External interrupt 1

ICR01

3B8

000FFFB8

External interrupt 2

ICR02

3B4

000FFFB4

External interrupt 3

ICR03

3B0

000FFFB0

External interrupt 4

ICR04

3AC

000FFFAC

External interrupt 5

ICR05

3A8

000FFFA8

External interrupt 6

ICR06

3A4

000FFFA4

External interrupt 7

ICR07

3A0

000FFFA0

Reload timer 0

ICR08

39C

000FFF9C

Reload timer 1

ICR09

398

000FFF98

Reload timer 2

ICR10

394

000FFF94

UART(Reception completed)

ICR11

390

000FFF90

UART(Reception completed)

ICR12

38C

000FFF8C

UART(Reception completed)

ICR13

388

000FFF88

UART0 (RX completed)

ICR14

384

000FFF84

UART1 (RX completed)

ICR15

380

000FFF80

UART2 (RX completed)

ICR16

37C

000FFF7C

MB91350A Series

(Continued)

Interrupt source

Interrupt

number

Interrupt

level

Offset

TBR default

address

DMAC0 (end, error)

ICR17

378

000FFF78

DMAC1 (end, error)

ICR18

374

000FFF74

DMAC2 (end, error)

ICR19

370

000FFF70

DMAC3 (end, error)

ICR20

36C

000FFF6C

DMAC4 (end, error)

ICR21

368

000FFF68

A/D

ICR22

364

000FFF64

ICR23

360

000FFF60

UART4 (Reception completed)

ICR24

35C

000FFF5C

SIO 5

ICR25

358

000FFF58

SIO 6

ICR26

354

000FFF54

SIO 7

ICR27

350

000FFF50

UART3 (Reception completed)

ICR28

34C

000FFF4C

UART3 (RX completed)

ICR29

348

000FFF48

Reload timer 3/main oscillation stabilization
wait timer

ICR30

344

000FFF44

Timebase timer overflow

ICR31

340

000FFF40

External interrupt: FPINT(8-15)

ICR32

33C

000FFF3C

Clock counter

ICR33

338

000FFF38

U/D Counter0

ICR34

334

000FFF34

U/D Counter1

ICR35

330

000FFF30

PPG 0/1

ICR36

32C

000FFF2C

PPG 2/3

ICR37

328

000FFF28

PPG 4/5

ICR38

324

000FFF24

16-bit free-run timer

ICR39

320

000FFF20

ICU2/3 (capture)

ICR40

31C

000FFF1C

ICU1 (capture)/UART4 (transmission
complete)

ICR41

318

000FFF18

ICU0 (capture)

ICR42

314

000FFF14

OCU0/1 (match)

ICR43

310

000FFF10

OCU2/3 (match)

ICR44

30C

000FFF0C

OCU4/5 (match)

ICR45

308

000FFF08

OCU6/7 (match)

ICR46

304

000FFF04

Interrupt delay source bit

ICR47

300

000FFF00

System reserved (Used by REALOS)

2FC

000FFEFC

System reserved (Used by REALOS)

2F8

000FFEF8

MB91350A Series

(Continued)

Interrupt source

Interrupt

number

Interrupt

level

Offset

TBR default

address

System reserved

2F4

000FFEF4

System reserved

2F0

000FFEF0

System reserved

2EC

000FFEEC

System reserved

2E8

000FFEE8

System reserved

2E4

000FFEE4

System reserved

2E0

000FFEE0

System reserved

2DC

000FFEDC

System reserved

2D8

000FFED8

System reserved

2D4

000FFED4

System reserved

2D0

000FFED0

System reserved

2CC

000FFECC

System reserved

2C8

000FFEC8

System reserved

2C4

000FFEC4

System reserved

2C0

000FFEC0

Used by INT instruction

80
to

255

50
to

2BC

000

000FFEBC

000FFC00

MB91350A Series

PERIPHERAL RESOURCES

Interrupt controller

(1)Description

The interrupt controller manages interrupt reception and arbitration.

· Hardware configuration

This module consists of the following components:
· ICR register
· Interrupt priority determination circuit
· Interrupt level and interrupt number (vector) generator
· HOLD request cancellation request generator

· Main function

This module has the following major functions:
· Detect NMI and interrupt requests
· Prioritize interrupts (according to level and number)
· Notify interrupt level of selected interrupt request (to CPU)
· Notify interrupt number of selected interrupt request (to CPU)
· Request (to the CPU) to return from stop mode in response to an NMI or interrupt request with interrupt level

other than "11111"

· Hold request cancellation request issued to the bus master

(2)Register list

(Continued)

ICR register

ICR00

ICR4

ICR3

ICR2

ICR1

ICR0

ICR01

ICR4

ICR3

ICR2

ICR1

ICR0

ICR02

ICR4

ICR3

ICR2

ICR1

ICR0

ICR03

ICR4

ICR3

ICR2

ICR1

ICR0

ICR04

ICR4

ICR3

ICR2

ICR1

ICR0

ICR05

ICR4

ICR3

ICR2

ICR1

ICR0

ICR06

ICR4

ICR3

ICR2

ICR1

ICR0

ICR07

ICR4

ICR3

ICR2

ICR1

ICR0

ICR08

ICR4

ICR3

ICR2

ICR1

ICR0

ICR09

ICR4

ICR3

ICR2

ICR1

ICR0

ICR10

ICR4

ICR3

ICR2

ICR1

ICR0

ICR11

ICR4

ICR3

ICR2

ICR1

ICR0

ICR12

ICR4

ICR3

ICR2

ICR1

ICR0

ICR13

ICR4

ICR3

ICR2

ICR1

ICR0

ICR14

ICR4

ICR3

ICR2

ICR1

ICR0

ICR15

ICR4

ICR3

ICR2

ICR1

ICR0

MB91350A Series

(Continued)

Hold request cancel request resister (HRCL)

ICR16

ICR4

ICR3

ICR2

ICR1

ICR0

ICR17

ICR4

ICR3

ICR2

ICR1

ICR0

ICR18

ICR4

ICR3

ICR2

ICR1

ICR0

ICR19

ICR4

ICR3

ICR2

ICR1

ICR0

ICR20

ICR4

ICR3

ICR2

ICR1

ICR0

ICR21

ICR4

ICR3

ICR2

ICR1

ICR0

ICR22

ICR4

ICR3

ICR2

ICR1

ICR0

ICR23

ICR4

ICR3

ICR2

ICR1

ICR0

ICR24

ICR4

ICR3

ICR2

ICR1

ICR0

ICR25

ICR4

ICR3

ICR2

ICR1

ICR0

ICR26

ICR4

ICR3

ICR2

ICR1

ICR0

ICR27

ICR4

ICR3

ICR2

ICR1

ICR0

ICR28

ICR4

ICR3

ICR2

ICR1

ICR0

ICR29

ICR4

ICR3

ICR2

ICR1

ICR0

ICR30

ICR4

ICR3

ICR2

ICR1

ICR0

ICR31

ICR4

ICR3

ICR2

ICR1

ICR0

ICR32

ICR4

ICR3

ICR2

ICR1

ICR0

ICR33

ICR4

ICR3

ICR2

ICR1

ICR0

ICR34

ICR4

ICR3

ICR2

ICR1

ICR0

ICR35

ICR4

ICR3

ICR2

ICR1

ICR0

ICR36

ICR4

ICR3

ICR2

ICR1

ICR0

ICR37

ICR4

ICR3

ICR2

ICR1

ICR0

ICR38

ICR4

ICR3

ICR2

ICR1

ICR0

ICR39

ICR4

ICR3

ICR2

ICR1

ICR0

ICR40

ICR4

ICR3

ICR2

ICR1

ICR0

ICR41

ICR4

ICR3

ICR2

ICR1

ICR0

ICR42

ICR4

ICR3

ICR2

ICR1

ICR0

ICR43

ICR4

ICR3

ICR2

ICR1

ICR0

ICR44

ICR4

ICR3

ICR2

ICR1

ICR0

ICR45

ICR4

ICR3

ICR2

ICR1

ICR0

ICR46

ICR4

ICR3

ICR2

ICR1

ICR0

ICR47

ICR4

ICR3

ICR2

ICR1

ICR0

HRCL

MHALT1

LVL4

LVL3

LVL2

LVL1

LVL0

MB91350A Series

External interrupt/NMI control

(1)Description

The external interrupt control unit is the block that controls external interrupt requests input to NMI and INT0 to
INT15.

The level can be selected from "H", "L", rising edge, or falling edge (except for NMI).

(2)Register list

(3)blockdiagram

External interrupt enable register (ENIR)

External interrupt request register (EIRR)

Request level setting register (ELVR)

The above registers (for 8 channels) are available in two sets; there are a total of 16 channels.

EN6

EN7

EN5

EN4

EN3

EN2

EN1

EN0

ER6

ER7

ER5

ER4

ER3

ER2

ER1

ER0

LA7

LB7

LB6

LA6

LB5

LA5

LB4

LA4

LA3

LB3

LB2

LA2

LB1

LA1

LB0

LA0

INT0 to INT15
NMI

R-bus

Interrupt

request

Interrupt enable register

Gate

Request F/F

Edge detection

circuit

Interrupt source register

Interrupt level setting register

MB91350A Series

8/16-bit up/down counter

(1)Description

This block is the up/down counter consisting of 6 event input pins, an 8/16-bit up/down counter, an 8-bit reload/
compare register, and their control circuit.

The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 2 channels of 8/16-bit up/down
counter in this block.

This module has the following features.
· 8-bit count register enabling counting from (0)d to (255)d (enabling counting from (0)d to (65535)d in "16-bit

x 1 operation mode" ).

· Four different count modes available with selectable count clocks

· Capable of selecting a count clock signal in timer mode, from among the inputs from two internal clocks and

an internal circuit

· Capable of selecting the detection edge of the external pin input signal in up/down counter mode

· Phase difference count mode suitable for counting for an encoder such as a motor, capable of easily counting

the rotation angle and the number of revolutions at high precision by inputting the phase-A, phase-B, and
phase-Z outputs of the encoder

· ZIN pin available for two functions selectable (valid in all modes)

· Compare and reload functions available not only separately but also in combination for up/down counting at

an arbitrary width

· Count direction flag used to identify the preceding count direction
· Capable of controlling the independent generations of interrupts at a compare match, reload (underflow),

overflow, or at a count direction change

Count mode

Timer mode

Up/down counter mode

Phase difference count mode (2 multiplication)

Phase difference count mode (4 multiplication)

Count clock

80 ns (12.5 MHz : 2-frequency division)

(When operating at 25 MHz )

320 ns (3.125 Hz : 8-frequency division)

Detection edge

Falling Edge detection

Rising Edge detection

Detection at rising edge, falling edge, or both edges

Edge detection disabled

ZIN Pin

Counter clear function

Gate function

Compare/reload function

Compare function (comparison interrupt request output)

Compare function (comparison interrupt request output and counter clear)

Reload function (underflow interrupt request output and reload)

Compare/reload function(Comparison interrupt request output and counter
clear; underflow interrupt request output and reload)

Compare/reload disabled

MB91350A Series

(2)Register list

· Up/down count resister (UDCR)
Up/down count resister ch0 (UDCR0)

Up/down count resister ch1 (UDCR1)

· Reload compare resister (RCR)
Reload compare resister ch0 (RCR0)

Reload compare resister ch1 (RCR1)

· Counter status register (CSR)
Counter status register ch(0, 1) (CSR0, 1)

· Counter control resister (CCRL)
Counter control resister ch(0, 1) (CCRL0, 1)

· Counter control resister (CCRH)
Counter control resister ch0 (CCRH0)

· Counter control resister ch1 (CCRH1)

D06

D07

D05

D04

D03

D02

D01

D00

D14

D15

D13

D12

D11

D10

D09

D08

D06

D07

D05

D04

D03

D02

D01

D00

D14

D15

D13

D12

D11

D10

D09

D08

CIT

CST

UDI

OVF

CTU

RLD

CGS

CGE

Reserved

CDC

M16

CFI

CLK

CES

CDC

CFI

CLK

CES

Reserved

MB91350A Series

16-bit Reload Timer

(1)Description

The 16-bit timer consists of a 16-bit down counter, 16-bit reload register, internal clock, clock generation prescaler,
and control register.

The clock source can be selected from among three internal clocks (prepared by frequency dividing the machine
clock by 2/8/32, and also by 64/128 only for ch3) and an external event.

The interrupt can be used to initiate DMA transfer.

The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 4 channels of this timer.

(2)Register list

Control status register (TMCSR)

16-bit timer register(TMR)

16-bit reload register(TMRLR)

(ch3 only)

CSL2

CSL1

CSL0

Reserved

Reserved Reserved

OUTL

RELD

INTE

CNTE

TRG

Reserved

MB91350A Series

PPG (Programable Pulse Generator)

The PPG can efficiently output highly precise PWM waveforms.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 6 channels of PPG timer.

(1)Description

Each channel consists of a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare
register with duty ratio setting buffer, and pin control unit.
The count clocks for the 16-bit down counter can be selected from the following 4 types :(peripheral clock

/16,

/64)

The counter is initialized to "FFFF

" at a reset or counter borrow.

PPG outputs (PPG0 to PPG5) are provided for each channel.

(2)Register list

(3)Block diagram (overall configuration for 1 channel)

15 0

General control register 10 (GCN10)

General control register 20 (GCN20)

Timer register (PTMR0 to 5)

Cycle setting register (PCSR0 to 5)

Duty setting register (PDUT0)

PPG0

PPG4

PPG2

PPG1

PPG5

PPG3

16-bit reload timer ch0

16-bit reload timer ch1

General D/A control

ICR register 20

General D/A control

ICR register 10

(resource select)

TRG input
PPG timer ch4

TRG input
PPG timer ch2

External TRG0 to

TRG3

TRG input
PPG timer ch1

TRG input
PPG timer ch3

TRG input
PPG timer ch5

TRG input
PPG timer ch0

External TRG4

External TRG5

MB91350A Series

U-Timer (16-bit timer for UART baud rate generation)

(1) Description

The U-Timer is a 16-bit timer for generating the baud rate for the UART. An arbitrary baud rate can be set
depending on the combination of the chip operating frequency and U-Timer reload value.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5 channels of this timer.

(2) Register list

(3) Block diagram

15 8 7 0

U-Timer Register (UTIM)

Reload Register (UTIMR)

U-Timer Control Register (UTIMC)

UTIMR (reload register)

UTIM (U-timer)

clock

load

underflow

to UART

control

f.f.

(Peripheral clock)

MB91350A Series

UART

(1) Description

The UART is a serial I/O port for asynchronous (start-stop) or CLK synchronous communication. This module
has the features listed below. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5
channels of UART.

· Full duplex double buffer
· Asynchronous (start-stop synchronized) or CLK synchronized transmission
· Supports multi-processor mode
· Completely programmable baud rate.

Arbitrary baud rate set by built-in timer (See the section for "U-Timer".)

· Variable baud rate can be input from an external clock.
· Error detection functions(parity, framing, overrun)
· Transmission signal format is NRZ
· UART Ch0 to Ch2 can start DMA transfer using interrupts (Ch3 and Ch4 cannot start DMA transfer).
· Capable of clearing DMAC interrupt source by writing to DRCL register

(2)Register list

Serial input register/serial output register (SIDR/SODR)

Serial status register(SSR)

Serial mode register

Serial control register(SCR)

DECL register (DRCL)

ORE

FRE

RDRF

TDRE

BDS

RIE

TIE

MD0

MD1

CS0

PEN

SBL

A/D

REC

RXE

TXE

MB91350A Series

(3) Block diagram

MD1
MD0

CS0

PEN
P
SBL
CL
A

REC
RXE
TXE

PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE

R - bus

SIDR

SODR

Control signal

From U-Timer

External clock
SCK

Clock

selection

circuit

Receive status
decision circuit

For DMA
received error generating
signal (to DMAC)

Reception clock

Reception control

circuit

Start bit

detection circuit

Received bit

Counter

Received parity

Counter

RX shifter

RX
complete

Transmission clock

RX interrupt
(to CPU)

TX interrupt
(to CPU)

Transmission

control circuit

Transmission

start circuit

Sending bit

Counter

Sending parity

Counter

TX shifter

Start
transmis-
sion

SMR

Control signal

SCR

SSR

SCK (clock)

SI (Receive data)

SO (Send data)

MB91350A Series

Extended I/O Serial Interface (SIO)

(1) Description

This block is a serial I/O interface that allows data transfer using clock synchronization. It is composition of a
single 8-bit

1 channel.

LSB-first or MSB-first transfer mode can be selected for data transfer.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 3 channels of this SIO.

The serial I/O interface operates in 2 modes:
· Internal shift clock mode: Transfer data in synchronization with the internal clock.
· External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK).

By manipulating the general-purpose port sharing the external pin (SCK) in this
mode, data can also be transferred by a CPU instruction.

(2) Register list

Serial mode control status register (SMCS)

SIO test resister(SES)

SDR (Serial Data Register)

SIO prescaler control register (CDCR)

DMAC interrupt source clear register (SRCL)

SMD1

SMD2

SMD0

SIE

SIR

BUSY

STOP

STRT

MODE

BDS

TST1

TST0

DIV3

DIV2

DIV1

DIV0

MB91350A Series

10. 16-bit free-run timer

(1)Description

The 16-bit free-running timer consists of a 16-bit up counter, control register, and status register. The count
values of this timer are used as the base timer for the output compares and input capture modules.
· Four count clock frequencies are available.
· An interrupt can be generated at a counter overflow.
· The counter can be initialized upon a match with compare register 0 of the output compare unit, depending

on the mode.

(2)Register list

(3)Block diagram

Timer data register (upper) (TCDT)

Timer data register (lower) (TCDT)

Timer control status register (lower) (TCCS)

T14

T15

T13

T12

T11

T10

T06

T07

T05

T04

T03

T02

T01

T00

IVF

ECLK

IVFE

STOP

MODE

CLR

CLK1

CLK0

ECLK

IVF

IVFE

STOP

MODE

CLR

CLK1

CLK0

FRCK

R-b

Interrupt

Timer data register

(TCDT)

Divider

Clock

select

to internal circuit (T15 to T00)

Comparator 0

Clock

MB91350A Series

11. Input Capture

(1) Description

This module detects a rising or falling edge or both edges of an external input signal and stores the 16-bit free-
running timer value in a register.

This module stores the 16-bit free-running timer value in a register. In addition, the module can generate an
interrupt upon detection of an edge.

The input capture module consists of input capture data registers and a control register.

Each input capture unit has a corresponding external input pin.

· The detection edge of an external input can be selected from among 3 types.

Rising edge

Falling edge

Both edges

· An interrupt can be generated upon detection of a valid edge of an external input.

(2) Register list

Input capture data register (upper) (IPCP)

Input capture data register (lower) (IPCP)

Capture control register (ICS23)

Capture control register (ICS01)

CP14

CP15

CP13

CP12

CP11

CP10

CP09

CP08

CP06

CP07

CP05

CP04

CP03

CP02

CP01

CP00

ICP2

ICP3

ICE3

ICE2

EG31

EG30

EG21

EG20

ICP0

ICP1

ICE1

ICE0

EG11

EG10

EG01

EG00

MB91350A Series

12. Output Compare

(1) Description

The output compare module consists of 16-bit compare registers, compare output latch, and control register.
When the 16-bit free-running timer value matches the compare register value, the output level is inverted and
an interrupt is issued.
The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 8 channels of this block.

This module has the features listed below.
· Capable of using the 8 compare registers independently. Output pins and interrupt flags corresponding to the

compare registers

· A pair of compare registers can be used to control output pins. Using tow compare registers to invert output pins
· Capable of setting the initial value for each output pin.
· Interrupts can be generated upon a compare match.
· The ch0 compare register is used as the compare clear register for the 16-bit free-running timer.

(2)Register list

Output compare register(upper) (OCCP)

Output compare register(lower) (OCCP)

Output control register(upper) (OCS)

Output control register(lower) (OCS)

C14

C15

C13

C12

C11

C10

C09

C08

C06

C07

C05

C04

C03

C02

C01

C00

CMOD

OTD1

OTD0

ICP0

ICP1

ICE1

ICE0

CST1

CST0

MB91350A Series

13. I

C Interface

(1) Description

The I

C interface is a serial I/O port supporting the Inter-IC bus, operating as a master/slave device on the I

bus. It has the following features
· Master/slave sending and receiving
· Arbitration function
· Clock sync function
· Slave address and general call address detection function
· Ditecting function of transmitting direction
· Repeated start condition generation and detection function
· Bus error detection function
· 10-bit/7-bit slave address
· Slave address receive acknowledge control when in master mode
· Support for composite slave addresses
· Capable of interruption when a transmission or bus error occurs
· Standard mode (Max 100K bps)/High speed mode (Max 400K bps) supported

MB91350A Series

(2)Register list

Bus control register(IBCR)

Bus status register(IBSR)

10-bit slave address resister (ITBA)

10-bit slave address mask resister(ITMK)

7-bit slave address resister (ISBA)

7-bit slave address mask resister (ISMK)

Data register (IDAR)

Clock control register (ICCR)

Clock disable register (IDBL)

BER

BEIE

SCC

MSS

ACK GCAA INTE

INT

RSC

LRB

TRX

AAS

GCA

ADT

TA9

TA8

TA7

TA6

TA5

TA4

TA3

TA2

TA1

TA0

ENTB

RAL

TM9

TM8

TM7

TM6

TM5

TM4

TM3

TM2

TM1

TM0

SA6

SA5

SA4

SA3

SA2

SA1

SA0

ENSB

SM6

SM5

SM4

SM3

SM2

SM1

SM0

TEST

CS4

CS3

CS2

CS1

CS0

DBL

MB91350A Series

(3) Block diagram

ICCR

IDBL

DBL

ICCR

IBSR

RSC

LRB

Last Bit

TRX

ADT

IBCR

BER

BEIE

INTE

INT

IBCR

SCC

MSS

ACK

GCAA

IBSR

ISMK

ITMK

IDAR

AAS

GCA

FNSB

ENTB

RAL

ITBA

ITMK

ISBA

ISMK

CS4

CS3

CS2

CS1

CS0

2 3 4 5

Sync

CLKP

First Byte

IRQ

SCLI
SCLO

SDA
SDAO

Operation enable

Clock enable

Clock divide 2

Clock selector2 (1/12)

Bus busy

Start

Sending/
receiving

Start stop condition

generation

Arbitration lost detection

Interrupt request

Start

Master

ACK enable

Slave

Global call

Slave address

compare

End

Error

Shift clock edge
changing timing

Start stop condition

detection

Generating shift clock

R-bus

MB91350A Series

14. A/D Converter

(1) Description

The A/D converter converts the analog input voltage into a digital value. It has the following features:
· Conversion time: 1.48

s minimum per channel

· Employing serial/parallel conversion type for sample & hold circuit
· 10-bit resolution (switchable between 8 and 10 bits)
· Program selection of the analog input from among 12 channels
· Conversion mode

Single conversion mode : Convert 1 selected channel
Scan conversion mode

: Scan up to 4 channels.

· Converted data is stored in the data buffer.
· An interrupt request to the CPU can be generated upon completion of A/D conversion. The interrupt can be

used to start DMA transfer.

· The startup source can be selected from among software, external trigger (falling edge), and reload timer ch2

(rising edge).

(2) Register list

ADCS1

ADCS2

ADTL0

ADTH0

ADTL2

ADTL1

ADTH1

ADTH2

ADTL3

ADTH3

8 7

Control status register (ADCS2/ADSC1)

Conversion time setting resister (ADCT)

Converted data register 0 (ADTH0/ADTL0)

Converted data register 1 (ADTH1/ADTL1)

Converted data register 2 (ADTH2/ADTL2)

Converted data register 3 (ADTH3/ADTL3)

MB91350A Series

15. 8-bit D/A Converter

(1) Description

This block contains 2 channels of 8-bit D/A converters. The D/A converter register can be used to control the
independent output of each channel. The block has the following features.
· Power saving function
· 3.3 V Interface

(2) Register list

(3) Block diagram

D/A data register 0 to 2(DADR0 to DADR2)

D/A control register 0 to 2 (DACR0 to DACR2)

DA6

DA7

DA5

DA4

DA3

DA2

DA1

DA0

DAE

DAE0

R-bus

DAE1

STOP

D/A

DAE2

STOP

D/A

D/A control

D/A

converter

D/A

converter

D/A output 0

D/A output 1

D/A

converter

D/A output 2

MB91350A Series

16. DMAC (DMA Controller)

(1) Description

This module realize direct memory access (DMA) transfer with the FR family device.
DMA transfer controlled by this module enables many types of data transfer to be performed at high speed
without CPU intervention, thereby improving system performance.

· Hardware configuration

This model consists mainly of the following components:
· Independent DMA channels

5 channels

· 5 channels independent access control circuits
· 32-bit address register (Supports reloading: 2 per channel)
· 16-bit transfer count register (Supports reloading: 1 per channel)
· 4-bit block count register (1 per channel)
· External transfer request input pins: DREQ0, DREQ1, DREQ2 (ch0, ch1, ch2 only)
· External transfer request acceptance output pins: DACK0, DACK1, DACK2 (ch0, ch1,ch2 only)
· DMA end output pins: DEOP0, DEOP1, DEOP2 (ch0, ch1, ch2 only)
· (ch3 only) fly-by transfer (memory to I/O, I/O to memory)
· 2-cycle transfer

· Main function

This module has the following major functions for data transfer:
· Supports independent data transfer for multiple channels (5 channels)

(1) Priority order (ch0

ch1

ch2

ch3

ch4)

(2) Order can be reversed for ch0 and ch1

(3) DMAC activation triggers

· External dedicated pin input (edge detection/level detection: ch0 to ch2 only)
· Internal peripheral request (Interrupt request sharing, including external interrupts)
· Software request (register write)

(4) Transmission mode

· Demand transfer, burst transfer, step transfer, or block transfer
· Addressing mode: 32-bit full addressing (increment, decrement, or fixed)

(address increment can be in the range - 255 to + 255)

· Data length: Byte, halfword, or word
· Single-shot or reload operation selectable

MB91350A Series

(2) Register Description

31 16 15 0

Ch0 control/status

Ch1 control/status

Ch2 control/status

Ch3 control/status

Ch4 control/status

Overall control register

(DMACR)

Ch0 transfer source address register

(DMASA0)

(DMADA0)

Ch1 transfer source address register

(DMASA1)

(DMADA1)

Ch2 transfer source address register

(DMASA2)

(DMADA2)

Ch3 transfer source address register

(DMASA3)

(DMADA3)

Ch4 transfer source address register

(DMASA4)

(DMADA4)

MB91350A Series

(3) Block diagram

Read
Write

DDNO

BLK register

DDNO register

DTCR

DSS [3:0]

ERIR, EDIR

TYPE, MOD, WS

IRQ
[4:0]

MCLREQ

X-bus

DADM, DASZ [7:0] DADR

SADM, SASZ [7:0] SADR

DMA transfer request

to bus controller

Read/write

control

bus

con-

troller

Bus control block

Access

Address

Address counter

Counter buffer

ounter buffer

Selector

Write back

Selector

Buffer

Counter

Selector

Write

back

DTC two-stage register

Buffer

Counter

Selector

DMA start

source select

circuit & request

acceptance

control

Priority

circuit

Status

transition

circuit

DMA control

DSAD two-stage register

DDAD two-stage register

Bus control block

Peripheral start request/

Stop input

External pin start

request/stop input

To interrupt controller

Clear peripheral interrupt

5-channel DMAC block diagram

Write back

MB91350A Series

ELECTRICAL CHARACTERISTICS

Abusolute Maximum Rating

*1 : The parameter is based on V

0 V.

*2 : V

must not be lower than V

- 0.3 V.

*3 : Be careful not to exceed "V

+ 0.3 V", for example, when the power is turned on.

*4 : The maximum output current is the peak value for a single pin.

*5 : The average output current is the average current for a single pin over a period of 100 ms.

*6 : The total average output current is the average current for all pins over a period of 100 ms.

Parameter

Symbol

Rating

Unit

Remarks

Min

Max

Power supply voltage*

0.5

4.0

Analog power supply voltage*

0.5

4.0

Analog power supply voltage*

0.5

4.0

Analog reference voltage*

AVRH

0.5

4.0

Input voltage*

0.5

Input voltage (Nch open-drain) *

IND

0.5

5.5

Analog pin input voltage*

0.5

Output voltage*

0.5

Maximum clamp current

CLAMP

2.0

Total maximum clamp current

CLAMP

"L" level maximum output current

"H" level maximum output current
(Nch open-drain)

OLND

"L" level average output current

OLAV

"H" level average output current
(Nch open-drain)

OLAVND

"L" level total maximum output
current

100

"L" level total average output
current

OLAV

"H" level maximum output current

"H" level average output current

OHAV

"H" level total maximum output
current

"H" level total average output
current

OHAV

Power consumption

850

Operating temperature

Storage temperature

STG

125

MB91350A Series

*7 :

Relevant pins: Port2, 3, 4, 5, 6, 8, 9, A, B, C, G, H, I, J, K, M, N, O, P, and AN (A/D input)

Use within recommended operating conditions.

Use at DC voltage (current).

The + B signal should always be applied a limiting resistance placed between the + B signal and

the microcontroller.

The value of the limiting resistance should be set so that when the + B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

Note that, when the microcontroller drive current is low as in low power consumption mode, the + B input

potential can increase the potential at the V

pin via a protective diode, possibly affecting other devices.

Note that, if the + B input exists when the microcontroller is off (not fixed at 0 V), power is supplied through

the pin, possibly causing the microcontroller to operate imperfectly.

Note that, if the + B input exists when the power supply is turned on, power is supplied through the pin,

possibly resulting in a power-supply voltage at which a power-on reset does not work.

Be careful not to let the + B input pin open.

Note that the analog I/O pins (such as the LCD drive and comparator input pins) other than the A/D input pin

cannot input + B.

Sample recommended circuits:

*8: V

should not exceed the specified ratings. However, if the maximum current to/from an input is limited by some

means with external components, the I

CLAMP

rating supersedes the V

rating.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

· Input/output equivalent circuits

Vcc

Pch

Nch

Protective diode

Limiting
resistance

+ B input (0 V to 16 V)

MB91350A Series

Recommended Operating Conditions

0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

Parameter

Symbol

Value

Unit

Remarks

Min

Max

Power supply voltage

3.0

3.6

At normal operating

3.0

3.6

hold RAM status at stop

Analog power supply voltage

0.3

3.6

0.3

3.6

Analog reference voltage

AVRH

Operating temperature

MB91350A Series

DC Characteristics

3.0 V to 3.6 V, V

0 V, Ta

C to

(Continued)

Parameter

Sym-

bol

Pin

Conditions

Value

Unit

Remarks

Min

Typ

Max

"H" level
input voltage

Port 2, 3, 4,

5, 6, 9, A, B,

0.65

0.3

IHS

Port 8, G, H,

I, M, N, O, P,

MD0, MD1,

MD2, INIT,

NMI

0.8

0.3

Hysteresis
input

IHST

Port J, K, L

0.8

5.25

Hysteresis input
with stand
voltage of 5 V

"L" level
input voltage

Port 2, 3, 4,

5, 6, 9, A, B,

0.25

ILS

Port 8, G, H,

I, M, N, O, P,

MD0, MD1,

MD2, INIT,

NMI

0.2

Hysteresis input

ILST

Port J, K, L

0.2

Hysteresis input
with stand
voltage of 5 V

"H" level
output voltage

Port 2, 3, 4,

5, 6, 8, 9, A,
B, C, G, H, I,

J, K, M, N,

O, P

3.0 V

4.0 mA

0.5

"L" level
output voltage

OL1

Port 2, 3, 4,

5, 6, 8, 9, A,
B, C, G, H, I,

J, K, M, N,

O, P

3.0 V

4.0 mA

0.4

OL2

Port L

3.0 V

15.0 mA

0.4

Nch open-drain

Input leak
current
(High-Z
output Leak-
age current)

All input pin

3.6 V

0<V

Pull-up
resistance

setting pin

INIT, Pull up

3.6 V

0.45 V

200

MB91350A Series

(Continued)

3.0 V to 3.6 V, V

0 V, Ta

C to

Parameter

Sym-

bol

Pin

Conditions

Value

Unit

Remarks

Min

Typ

Max

Power
supply
current

12.5 MHz

3.3 V

160

220

Multiply by 4
CLKB : 50 MHz
CLKT : 25 MHz
When operating at
25 MHz

CCS

12.5 MHz

3.3 V

100

140

Sleep
When operating at
25 MHz

CCH

3.3 V

100

at stop

CCL

32.768 kHz

3.3 V

0.3

3.0

Sub RUN
CLKB : 32.768 kHz
CLKT : 32.768 kHz
When operating at
32.768 kHz

CCLS

32.768 kHz

3.3 V

0.2

2.0

Sub sleep
When operating at
32.768 kHz

CCT

32.768 kHz

3.3 V

120

at watch mode
operating
(Main Off, STOP)

Input
capacitance

Other than

, V

, AV

, DA

MB91350A Series

AC Characteristics

(1) Clock timing

3.0 V to 3.6 V, V

0 V, Ta

C to

* : The values assume a gear cycle of 1/16.

Parameter

Sym-

bol

Pin

Conditions

Value

Unit

Remarks

Min

Typ

Max

Clock
frequency

X0
X1

12.5

MHz

Main PLL
(When operating at
max internal frequency
(50 MHz)

12.5 MHz

self-oscillation with

PLL)

Clock cycle time

X0
X1

100

Clock
frequency

X0
X1

MHz

Main self-oscillation
(frequency-halved
input)

Internal operating
clock frequency

When a minimum
value of 12.5 MHz
is input as the X0
clock frequency
and

4 multiplica-

tion is set for the
PLL of the oscillator
circuit

2.94*

MHz CPU

CPP

2.94*

MHz Peripheral

CPT

2.94*

MHz External bus

Internal operating
clock cycle time

340*

CPU

CPP

340*

Peripheral

CPT

340*

External bus

Clock
frequency

X0A
X1A

32.768

kHz

SUB
self-oscillation

Clock cycle time

X0A
X1A

28.6

30.51

33.3

Input clock palse
width

X0
X1

/tc

Internal operating
clock frequency

CPP

CPT

When a standard
value of 32.768 kHz
is input as the X0A
clock frequency

kHz

Internal operating
clock cycle time

CPP

CPT

30.51

500*

MB91350A Series

(2)Clock output timing

3.0 V to 3.6 V, V

0 V, Ta

C to

*1 : t

CYC

is the frequency of one clock cycle after gearing.

*2 : The following ratings are for the gear ratio set to

1. For the ratings when the gear ratio is set to between 1/2,

1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation.

n )

CYC

*3 : The following rating are for the gear ratio set to

Note : t

CPT

indicates the internal operating clock cycle time. See "(1) Clock timing".

In the following AC ratings, MCLK is equivalent to SYSCLK.

(3) Reset and hardware standby ratings

3.0 V to 3.6 V, V

0 V, Ta

C to

Note : t

indicates the clock cycle time. See "(1) Clock timing".

Parameter

Symbol

Pin

Condi-

tions

Value

Unit

Remarks

Min

Max

Cycle time

CYC

MCLK,

SYSCLK

CPT

SYSCLK

CHCL

MCLK,

SYSCLK

CYC

SYSCLK

CLCH

MCLK,

SYSCLK

CYC

Parameter

Symbol

Pin

Condi-

tions

Value

Unit

Remarks

Min

Max

INIT input time
(at power-on)

INTL

INIT

INIT input time
(other than at power-on)

MCLK
SYSCLK

CYC

CLCH

CHCL

INIT

0.2 V

INTL

MB91350A Series

(4) Normal bus access read/write operation

3.0 V to 3.6 V, V

0 V, Ta

C to

*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (t

CYC

the number of

cycles added for the delay) to this rating.

*2 : The following ratings are for the gear ratio set to

1. For the ratings when the gear ratio is set to between 1/2 to

1/16, substitute 1/2 to 1/16 for n in the following equation.

Calculation expression: 3/(2n)

CYC

*3 : AWRxL : Area Wait Register

Note : t

CYC

indicates the cycle time. See "(2) Clock output timing".

Parameter

Symbol

Pin

Conditions

Value

Unit

Remarks

Min

Max

CS0 to CS3 setup

CSLCH

MCLK,

CS0 to CS3

AWRxL*

: W02

CSDLCH

AWR0L : W02

CS0 to CS3 hold

CHCSH

CYC

Address setup

ASCH

MCLK,

A23 to A00

ASWL

WR0, WR1,

A23 to A00

ASRL

RD,

A23 to A00

Address hold

CHAX

MCLK,

A23 to A00

CYC

WHAX

WR0, WR1,

A23 to A00

RHAX

RD,

A23 to A00

Valid address

Valid data input time

AVDV

A23 to A00,

D31 to D16

3 / 2

CYC

*1
*2

WR0, WR1 delay time

CHWL

MCLK,

WR0, WR1

WR0, WR1 delay time

CHWH

WR0, WR1 minimum
pulse width

WLWH

WR0, WR1

CYC

Data setup

WRx

DSWH

WR0, WR1,

D31 to D16

CYC

WRx

Data hold time

WHDX

RD delay time

CHRL

MCLK,

RD delay time

CHRH

Valid data input time

RLDV

RD,

D31 to D16

CYC

Data setup

Time

DSRH

Data hold time

RHDX

RD minimum pulse width

RLRH

CYC

AS setup

ASLCH

MCLK,

AS hold

CHASH

CYC

MB91350A Series

(5) Multiplex bus access read/write operation

3.0 V to 3.6 V, V

0 V, Ta

C to

Notes :

This rating is not guaranteed when the CS

RD/WR, and setup delay setting by AWR: bit 1 is "0".

Beside This rating, normal bus interface ratings are applicable.

CYC

indicates the cycle time. See "(2) Clock output timing".

Parameter

Symbol

Pin

Condi-

tions

Value

Unit

Remarks

Min

Max

AD15 to AD0 Address
AUDI setup time

MCLK

ASCH

MCLK,

D31 to D16

MCLK

AD15 to AD0 Address
AUDI Hold Time

CHAX

CYC

AD15 to AD0 Address
AUDI setup time

ASASH

AS,

D31 to D16

AD15 to AD0 Address
AUDI Hold Time

ASHAX

CYC

MCLK

D31 to D16

ASCH

CHAX

ASASH

ASHAX

CYC

BA1

MB91350A Series

(7) Hold timing

3.0 V to 3.6 V, V

0 V, Ta

C to

* : These are applied to only the case that SREN bit of area select register (ACR) is set to "1".

Notes :

It takes 1 cycle or more from when BRQ is captured until BGRNT changes.

CYC

indicates the cycle time. See "(2) Clock output timing".

Parameter

Symbol

Pin

Conditions

Value

Unit

Remarks

Min

Max

BRQ setup time

MCLK

BRQS

MCLK,

BRQ

MCLK

BRQ

AUDI Hold Time

BRQH

BGRNT delay time

CHBGL

MCLK,

BGRNT

CYC

BGRNT delay time

CHBGH

CYC

Pin floating

BGRNT

time

XZBGL

BGRNT,

D31 to D16,

A23 to A00,

CS3 to CS0*

CYC

BGRNT

Pin valid time

BGHXV

CYC

MCLK

CHBGL

CHBGH

BRQ

BGRNT

CYC

BGHXV

XZBGL

BRQS

BRQH

D31 to D16,
A23 to A00,
CS3 to CS0 *

High-Z

* : These are applied to only the case that SREN bit of area select register (ACR) is set to "1".

MB91350A Series

(8) UART, SIO timing

3.0 V to 3.6 V, V

0 V, Ta

C to

Notes :

Above rating is for CLK synchronous mode.

CPP

indicates the peripheral clock cycle time. See "(1) Clock timing".

Parameter

Symbol

Pin

Conditions

Value

Unit

Remarks

Min

Max

Serial clock cycle time

SCYC

SCK0 to SCK7

Internal shift
clock
mode

8 t

CPP

SCK

BGRNT delay time

SLOV

SCK0 to SCK7,

SO0 to SO7

Valid SI

SCK

IVSH

SCK0 to SCK7,

SI0 to SI7

100

SCK

valid SIN hold

time

SHIX

SCK0 to SCK7,

SI0 to SI7

Serial clock H Pulse Width

SHSL

SCK0 to SCK7

External
shift clock
mode

4 t

CPP

Serial clock L Pulse Width

SLSH

SCK0 to SCK7

4 t

CPP

SCK

SO delay time

SLOV

SCK0 to SCK7,

SO0 to SO7

150

Valid SI

SCK

IVSH

SCK0 to SCK7,

SI0 to SI7

SCK

valid SI hold

time

SHIX

SCK0 to SCK7,

SI0 to SI7

· Internal shift clock mode

· External shift clock mode

SCK0 to SCK7

SO0 to SO7

SI0 to SI7

SCYC

SLOV

IVSH

SHIX

SCK0 to SCK7

SO0 to SO7

SI0 to SI7

SLOV

SLSH

SHSL

IVSH

SHIX

MB91350A Series

(9) Free-run timer clock, PPG timer input timing

3.0 V to 3.6 V, V

0 V, Ta

C to

Note : t

CPP

indicates the peripheral clock cycle time. See "(1) Clock timing".

(10) Trigger input timing

3.0 V to 3.6 V, V

0 V, Ta

C to

Note : t

CPP

indicates the peripheral clock cycle time. See "(1) Clock timing".

Parameter

Symbol

Pin

Conditions

Value

Unit

Remarks

Min

Max

Input pulse width

TIWH

TIWL

FRCK,

TRG0 to TRG5,

AIN0 to AIN1,
BIN0 to BIN1,

ZIN0 to ZIN1

2 t

CPP

Parameter

Symbol

Pin

Conditions

Value

Unit

Remarks

Min

Max

A/D activation trigger input
time

ATGX

ATG

5 t

CPP

input capture
input trigger

INP

IN0 to IN3

5 t

CPP

TIWH

TIWL

ATG,
IN0 to IN3

ATGX

, t

INP

MB91350A Series

(11)DMA controller timing
· For edge detection (block/step transfer mode,burst transfer mode)

3.0 V to 3.6 V, V

0 V, Ta

C to

* : t

CYC

becomes t

when f

CPT

is greater than f

· For level detection (demand transfer mode)

3.0 V to 3.6 V, V

0 V, Ta

C to

· Common operation mode

3.0 V to 3.6 V, V

0 V, Ta

C to

* : AWRxL: Area Wait Register.

Note : t

CYC

indicates the cycle time. See "(2) Clock output timing".

Parameter

Symbol

Pin

Conditions

Value

Unit

Remarks

Min

Max

DREQ Input pulse width

DRWL

DREQ 0 to DREQ2

2 t

CYC

DREQ Input pulse width

DSWH

DSTP 0 to DSTP2

2 t

CYC

Parameter

Symbol

Pin

Condi-

tions

Value

Unit Remarks

Min

Max

DREQ setup time

DRS

MCLK, DREQ 0 to DREQ2

DREQ Hold Time

DRH

MCLK, DREQ 0 to DREQ2

0.0

DSTP setup time

DSTPS

MCLK, DSTP 0 to DSTP2

DSTP Hold Time

DSTPH

MCLK,DSTP 0 to DSTP2

0.0

Parameter

Symbol

Pin

Condi-

tions

Value

Unit

Remarks

Min

Max

DACK delay time

DALCH

MCLK,

DACK 0 to

DACK2

AWRxL* :

W02

CS timing

FR30 compatible

DADLCH

AWR0L :

W02

CS timing

FR30 compatible

CHDAH

CYC

CS timing

FR30 compatible

DEOP delay time

DELCH

MCLK,

DEOP 0 to

DEOP2

AWR0L :

W02

CS timing

FR30 compatible

DEDLCH

AWRxL* :

W02

CS timing

FR30 compatible

CHDEH

CYC

CS timing

FR30 compatible

IORD delay time

CHIRL

MCLK,

IORD

CHIRH

IOWR delay time

CHIWL

MCLK,

IOWR

CHIWH

IORD minimum pulse width

IRLIRH

IORD

IOWR minimum pulse width

IWLIWH

IOWR

MB91350A Series

(12) I

C Timing

3.0 V to 3.6 V, V

0 V, Ta

C to

*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t

HDDAT

only has to be met if the device does not stretch the "L" width (t

LOW

) of the SCL signal.

*3 : A Fast-mode I

C-bus device can be used in a Standard-mode I

C-bus system, but the requirement

SUDAT

250 ns must then be met.

*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.

Parameter

Symbol

Condition

Standard-mode

Fast-mode*

Unit

Min

Max

Min

Max

SCL clock frequency*

SCL

1.0 k

50 pF*

100

400

kHz

Hold time (repeated) START condition
SDA

SCL

HDSTA

4.0

0.6

"L" width of the SCL clock

LOW

4.7

1.3

"H" width of the SCL clock

HIGH

4.0

0.6

Set-up time for a repeated START condition
SCL

SDA

SUSTA

4.7

0.6

Data hold time
SCL

SDA

HDDAT

3.45*

0.9*

Data set-up time
SDA

SCL

SUDAT

250

100

Set-up time for STOP condition
SCL

SDA

SUSTO

4.0

0.6

Bus free time between a STOP and START
condition

BUS

4.7

1.3

SDA

SCL

LOW

SUDAT

HDSTA

BUS

HDSTA

HDDAT

HIGH

SUSTA

SUSTO

MB91350A Series

100

Electrical Characteristics for the A/D Converter

3.0 V to 3.6 V, V

0 V, AVRH

3.0 V to 3.6 V, Ta

C to

*1: Measured in the CPU sleep state

*2: When the peripheral resource clock frequency is 25.0 MHz, set the Conversion Time Setting Register (ADCT)

to a value equal to or greater than 5334

Set each bit as follow :

Sampling time

: SAMP3 to SAMP0

Conversion time a : CV03 to CV0

Conversion time b : CV13 to CV0

Conversion time c : CV23 to CV0

Parameter

Symbol

Pin

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Total error*

5.0

LSB

AVcc

3.3 V,

AVRH

3.3 V

Nonlinear error*

3.5

LSB

Differential linear error*

2.5

LSB

Zero transition voltage*

AN11

to AN0

AVRL

2.0

AVRL

1.0

AVRL

6.0

LSB

Full-transition voltage*

AN11

to AN0

AVRH

5.5

AVRH

1.5

AVRH

3.0

LSB

Conversion time

1.48*

300

Analog power supply current
(analog + digital)

At stop

Reference power supply
current
(between AVRH and AVRL)

AVRH

470

AVRH

3.0 V,

AVRL

0.0 V

At stop

Analog input capacitance

AN11

to AN0

Interchannel disparity

AN11

to AN0

LSB

MB91350A Series

101

About the external impedance of the analog input and its sampling time

· A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.

· To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.

· If the sampling time cannot be sufficient, connect a capacitor of about 0.1

F to the analog input pin.

About errors

As |AVRH-AV

| becomes smaller, values of relative errors grow larger.

Analog input

Comparator

Analog input circuit model

During Sampling : ON

Note : The values are reference values.

MB91355A

0.18 k

(Max)

63.0 pF (Max)

MB91F355A

0.18 k

(Max)

39.0 pF (Max)

MB91F356B

0.18 k

(Max)

39.0 pF (Max)

100

MB91F355A/MB91F356B

MB91355A

MB91F355A/MB91F356B

MB91355A

(External impedance

0 k

to 100 k

)

External impedance [k

]

Minimum sampling time [

(External impedance

0 k

to 20 k

)

External impedance [k

]

Minimum sampling time [

The relationship between the external impedance and minimum sampling time

MB91350A Series

102

Definition of A/D Converter Terms

· Resolution

Analog variation that is recognized by an A/D converter.

· Linearity error

Zero transition point ( "0000000000" - "0000000001") and full-scale transition point

Difference between the line connected ("1111111110" - "1111111111") and actual conversion characteristics.

· Differential linear error

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

: A voltage at which digital output transitions from (N - 1) to N.

Linear error in digital output N

{1 LSB'

}

1 LSB'

[LSB]

Differential linear error in digital output N

1) T

1 LSB'

1 [LSB]

1 LSB

FST

1022

[V]

FST

: A voltage at which digital output transitions from (3FE)

to (3FF)

3FF

3FE

3FD

004

003

002

001

AVRH

{1 LSB' (N

}

AVRH

Linearity error

Differential linear error

Digital output

Actual conversion

characteristic

FST

(measure-

ment value)

(measurement value)

Actual conversion
characteristic

Ideal characteristics

(measurement value)

Analog input

Ideal characteristics

Actual conversion

characteristic

(N+1)T

(measurement
value)

(measurement value)

Actual conversion characteristic

: A voltage at which digital output transitions from (000)

to (001)

MB91350A Series

103

· Total error

This error indicates the difference between actual and ideal values, including the zero transition error/full-scale
transition error/linearity error.

3FF

3FE

3FD

004

003

002

001

AVRH

1.5 LSB'

0.5 LSB'

{1 LSB' (N

0.5 LSB'}

Total error

Digital output

Actual conversion

characteristic

(measurement

value)

Analog input

Total error of digital output N

{1 LSB'

{0.5 LSB'}

1 LSB'

'(Ideal value)

{0.5 LSB' [V]

FST

'(Ideal value)

AVRH

1.5 LSB' [V]

: A voltage at which digital output transitions from (N + 1) to (N).

1LS' (Ideal value) 1

AVRH

1024

[V]

Actual
characteristics

Ideal characteristics

MB91350A Series

104

Electrical Characteristics for the D/A Converter

3.0 V

3.6 V, V

0 V, Ta

C to

* : This D/A converter varies in current consumption depending on each input digital code.

This rating indicates the current consumption when the digital code that maximizes current consumption is input.

Parameter

Symbol

Pin

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Nonlinear error

2.0

LSB

When the output is unloaded

Differential linear error

1.0

LSB

When the output is unloaded

Convertion speed

0.6

When load capacitance (C

) = 20 pF

3.0

When load capacitance (C

) = 100 pF

Output high impedance

DA0 to

DA2

2.0

2.9

3.8

Analog current

s conversion when the output is

unloaded

ADA

460*

Input digital code
When fixed at 7A

or 85

ADAH

0.1

At power-down

MB91350A Series

105

FLASH MEMORY WRITE/ERASE CHARACTERISTICS

*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at

C).

Parameter

Condition

Value

Unit

Remarks

Min

Typ

Max

Sector erase time

3.3 V

Excludes 00

programming

prior erasure.

Chip erase time

Excludes 00

programming

prior erasure.

Half word (16-bit
width) writing time

3,600

Excludes system-level
overhead.

Write/erase cycle

10,000

cycle

Flash data retention
time

Average

year

MB91350A Series

106

EXAMPLE CHARACTERISTICS

(Continued)

(1) "H" level output voltage

(2) "L" level output voltage

(3) "L" level output voltage (Nch open-drain)

(4) Input leak current

(5) Pull-up resistance

2.7

3.0

3.3

3.6

3.9

[V]

- V

Ta = +25

OL1

[mV]

[V]

2.7

3.0

3.3

3.6

3.9

100

200

300

400

500

OL1

- V

Ta = +25

OL2

[mV]

[V]

2.7

3.0

3.3

3.6

3.9

100

200

300

400

500

OL2

- V

Ta = +25

2.7

3.0

3.3

3.6

3.9

[

[V]

- V

Ta = +25

2.7

3.0

3.3

3.6

3.9

[V]

]

200

160

120

- V

Ta = +25

MB91350A Series

107

(Continued)

(6) Power supply current

(7) Power supply current

(8) Power supply current at sleep

(9) Power supply current at sleep

(10) Power supply current at stop

(11) Sub RUN power supply current

(12) Sub sleep power supply current

(13) Watch mode power supply current

[mA]

[V]

2.7

3.0

3.3

3.6

3.9

300

250

200

150

100

- V

Ta = +25

C, f

= 50 MHz,

CCP

= f

CPT

= 25 MHz

100

300

250

200

150

100

[mA]

[MHz]

- f

Ta = +25

C, V

= 3.3 V,

= 4

C (multiplied by 4)

CCS

[mA]

[V]

2.7

3.0

3.3

3.6

3.9

300

250

200

150

100

CCS

- V

Ta = +25

C, f

= 50 MHz,

CCP

= f

CPT

= 25 MHz

100

300

250

200

150

100

CCS

[mA]

[MHz]

CCS

- f

Ta = +25

C, V

= 3.3 V,

= 4

C (multiplied by 4)

[V]

2.7

3.0

3.3

3.6

3.9

CCH

[

100

CCH

- V

Ta = +25

[V]

2.7

3.0

3.3

3.6

3.9

CCL

[

100

200

300

400

500

CCL

- V

Ta = +25

C, f

= 32 kHz,

CCP

= f

CPT

= 32 kHz

500

400

300

200

100

2.7

3.0

3.3

3.6

3.9

CCLS

[

[V]

CCLS

- V

Ta = +25

C, f

= 32 kHz,

CCP

= f

CPT

= 32 kHz

[V]

CCT

[

100

2.7

3.0

3.3

3.6

3.9

CCT

- V

Ta = +25

C, f

= 32 kHz,

CCP

= f

CPT

= 32 kHz

MB91350A Series

108

(Continued)

(14) A/D converter power supply current

(15) A/D converter reference power supply voltage

(16) A/D converter power supply current at stop

(17) A/D converter reference power supply current at stop

(18) D/A converter power supply current

< per 1 channel >

(19) D/A converter power supply current at power down

2.7

3.0

3.3

3.6

3.9

[mA]

[V]

- V

Ta = +25

1000

800

600

400

200

2.7

3.0

3.3

3.6

3.9

[

[V]

- V

Ta = +25

2.7

3.0

3.3

3.6

3.9

[V]

[

- V

Ta = +25

2.7

3.0

3.3

3.6

3.9

[V]

[

- V

Ta = +25

500

400

300

200

100

2.7

3.0

3.3

3.6

3.9

[

[V]

ADA

- V

Ta = +25

2.7

3.0

3.3

3.6

3.9

[V]

[

ADAH

- V

Ta = +25

MB91350A Series

110

PACKAGE DIMENSION

176-pin plastic LQFP

(FPT-176P-M02)

Note 1) * : Values do not include resin protrusion.

Resin protrusion is

0.25 (.010) Max (each side) .

Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.

Dimensions in mm (inches).
Note: The values in parentheses are reference values.

2003 FUJITSU LIMITED F176006S-c-4-6

Details of "A" part

0°~8°

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.25(.010)

(Stand off)

(.004±.004)

0.10±0.10

1.50

+0.20
0.10

+.008
.004

.059

(Mounting height)

0.08(.003)

(.006±.002)

0.145±0.055

"A"

INDEX

LEAD No.

132

133

176

0.50(.020)

0.22±0.05

(.009±.002)

0.08(.003)

24.00±0.10(.945±.004)SQ

26.00±0.20(1.024±.008)SQ

MB91350A Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party's
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0505

2005 FUJITSU LIMITED Printed in Japan

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91F355A