DS07-16502-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-Bit Proprietary Microcontroller

CMOS

FR65E Series

MB91301/MB91V301

DESCRIPTION

The MB91301/MB91V301 are a line of microcontrollers based on a 32-bit RISC CPU core (FR family), incorpo-
rating a variety of I/O resources and a bus control mechanism for embedded control that requires the processing
of a high-performance, fast CPU as well as an SDRAM interface that can connect SDRAM directly to the chip.
The large address space supported by the 32-bit CPU addressing means that operation is primarily based on
external bus access although a large internal RAM area is included for high-speed execution of CPU instructions.
The MB91301 and MB91V301 are FR65E series products based on the FR30/40 series CPU with enhanced bus
access for higher speed operation. The device specifications include a D/A converter to facilitate motor control
and are ideal for use in DVD players that support fly-by transfer.

FEATURES

FR CPU

· 32-bit RISC, load/store architecture, 5-stage pipeline
· 68 MHz internal operating frequency (Max) [external (Max) 68 MHz] (when using PLL with base frequency

(Max) = 17 MHz)

· General purpose registers : 32 bits

· 16-bit fixed length instructions (basic instructions), 1 instruction per cycle

(Continued)

PACKAGE

144-pin, Plastic LQFP

179-pin, Ceramic PGA

(FPT-144P-M12)

(PGA-179C-A03)

MB91301/MB91V301

· Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift

etc.

· Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store

instructions

· Easier assembler coding: Register interlock function
· Branch instructions with delay slots : Reduced overhead time in branch executions
· Built-in multiplier with instruction-level support

Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles

· Interrupt (PC, PS save) : 6 cycles, 16 priority levels

Bus interface

· Operating frequency : Max 68 MHz (when using SDRAM)
· Full 24-bit address output (16 MB memory space)
· 8-bit, 16-bit or 32-bit data input/output
· Built-in pre-fetch buffer
· Unused data and address pins can be used as general-purpose input/output ports.
· Eight fully independent chip select outputs, can be set in minimum 64 KB units.
· Supports the following memory interfaces

Asynchronous SRAM, asynchronous ROM/Flash
Page mode ROM/Flash ROM (selectable page size

1, 2, 4, or 8)

Burst mode ROM/Flash ROM (MBM29BL160D/161D/162D)

· SDRAM (FCRAM Type, CAS Latency 1 to 8, 2/4 bank products.)
· Address/Data multiplex bus (only 8/16-bit width)
· Basic bus cycle : 2 cycles
· Automatic wait cycle generation function can insert wait cycles, independently programmable for each memory

area.

· RDY input for external wait cycles
· Endian setting of byte ordering (Big/Little)

CS0 area only for big endian

· Prohibition setting of write (only for Read)
· Permission/prohibition setting of fetch into built-in cache
· Permission/prohibition setting of prefetch function
· DMA supports fly-by transfer with independent I/O wait control
· External bus arbitration can be used using BRQ and BGRNT.

Built-in memory

· 4 KB data RAM
· Built-in 8 KB Data RAM and 8 KB instruction, DATA sharing RAM in EVA chip.

Instruction cache (MB91V301 only)

· Size : 4 KB
· 2-way set associative
· 128 blocks/way, 4 entries/block
· Lock function enables program code to be made cache-resident
· Areas not used for instruction cache can be used as instruction RAM

(Continued)

MB91301/MB91V301

(Continued)

DMAC (DMA Controller)

· 5-channel (2-channel external-to-external)
· 3 transfer triggers : External pin, internal peripheral, software
· Capable of selecting an internal peripheral as a transfer source freely for each channel
· Addressing using 32-bit full addressing mode (increment, decrement, fixed)
· Transfer modes : Demand transfer, burst transfer, step transfer, or block transfer
· Supports fly-by transfer (between external I/O and memory)
· Selectable transfer data size : 8, 16, or 32-bit

Bit search module

· Searches words from MSB for position of first 1/0 bit value change

Reload Timers

· 16-bit timer : 3 channels
· Internal clock : 2 clock cycle resolution, divide by 2/8/32 selective

UART

· Full duplex, double buffer UART
· Independent 3 channels
· Data length : 7 bits to 9 bits (without parity) , 6 bits to 8 bits (with parity)
· Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable

Multi-processor mode

· Built-in 16-bit timer (U-TIMER) as a baud rate generator to generate arbitrary baud rates
· External clock can be used as transfer clock
· Variety of error detection functions (parity, frame, overrun)

Interrupt controller

· External interrupt input : 1 non-maskable interrupt pin and 8 normal interrupt pins (INT0 to INT7)
· Internal interrupt resources : UART, DMAC, A/D, UTIMER, delay interrupt
· Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt

10. A/D converter

· 10-bit resolution, 4 channels
· Successive approximation type, conversion time : 4.1

s at 34 MHz

· Built-in sample and hold circuit
· Conversion modes : Single conversion mode, scan conversion mode and repeat conversion mode selectable
· Conversion triggers : Software, external trigger and built-in timer selectable

11. Other interval timers

· 16-bit timer : 3 channels (U-TIMER)
· PPG timer : 4 channels
· Watchdog timer : 1 channel

12. Other features

· Reset resources : watchdog timer/software reset/external reset (INIT pin)
· Power-saving modes : Stop mode, sleep mode
· Clock control

Gear function : Allows arbitrary different operating clock frequencies to be set for the CPU and peripherals.
You can select one of the 16 gear clock factors of 1/1 to 1/16. PLL multiplication can also be selected. Note,
however, that peripherals operate at a maximum of 34 MHz.

· Packages : MB91301 FPT-144P-M12, MB91V301 PGA-179C-A03
· CMOS technology : 0.25

· Power supply (analog power supply): 3.3 V

0.3 V (internal regulator used)

MB91301/MB91V301

PIN ASSIGNMENTS

· MB91301

(TOP VIEW)

(FPT-144P-M12)

108

107

106

105

104

103

102

101

100

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

P13/D11

P14/D12

P15/D13

P16/D14

P17/D15

P20/D16

P21/D17

P22/D18

P23/D19

P24/D20

P25/D21

P26/D22

P27/D23

D24

D25

D26

D27

D28

D29

D30

D31

P80/RDY

P81/BGRNT

P82/BRQ

DQMUU/WR0(UUB)

P85/DQMUL/WR1(ULB)

P86/DQMLU/WR2(LUB)

P87/DQMLL/WR3(LLB)

P90/SYSCLK

D10/P12

D09/P11

D08/P10

D07/P07

D06/P06

D05/P05

D04/P04

D03/P03

D02/P02

D01/P01

D00/P00

CS7/PA7

CS6/PA6

CS5/PPG2/PA5

CS4/TRG2/PA4

CS3/PA3

CS2/PA2

CS1/PA1

CS0/PA0

NMI

INIT

MD2

MD1

MD0

IORD/PB7

IOWR/PB6

DEOP1/PPG1/PB5

DACK1/TRG1/PB4

DREQ1/PB3

DEOP0/PB2

DACK0/PB1

DREQ0/PB0

TIN2/TRG3/PH2

TIN1/PPG3/PH1

TIN0/PH0

TRG0/PJ7

PPG0/PJ6

SCK1/PJ5

SOT1/PJ4

SIN1/PJ3

SCK0/PJ2

SOT0/PJ1

SIN0/PJ0

INT7/SCK2/PG7

INT6/SOT2/PG6

INT5/SIN2/PG5

INT4/ATG/PG4

INT3/PG3

INT2/PG2

INT1/PG1

INT0/PG0

/AVRL

AN0

AN1

AN2

AN3

AVR

AVRH

P91/MCLKE

P92/MCLK

P93

P94/SRAS/LBA/AS

P95/SCAS/BAA

P96/SWE/WR

A00

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

P60/A16

P61/A17

P62/A18

P63/A19

P64/A20

P65/A21

P66/A22

P67/A23

MB91301

MB91301/MB91V301

· MB91V301

(TOP VIEW)

(PGA-179C-A03)

INDEX

179

177

173

176

180

169

171

175

166

167

170

162

163

164

157

159

158

154

153

152

149

147

146

148

143

141

144

138

135

139

137

131

134

132

128

136

101

107

113

119

125

130

102

108

114

118

122

126

103

104

109

112

117

121

124

133

178

174

172

168

165

161

160

156

155

151

150

145

142

140

129

127

100

105

106

110

111

115

116

120

123

MB91301/MB91V301

·
·
·
·

MB91V301 Pin No. Table

(Continued)

No.

PIN

Pin Name

No.

PIN

Pin Name

No.

PIN

Pin Name

N.C.

C11

J15

A15

P13/D11

A12

DQMUU/WR0 (UUB) 72

J14

B12

P85/DQMUL/WR1 (ULB) 73

J13

A13

P86/DQMLU/WR2 (LUB) 74

J12

P60/A16

P14/D12

D11

P87/DQMLL/WR3 (LLB) 75

K15

P61/A17

P15/D13

C12

K14

P62/A18

P16/D14

B13

K13

P63/A19

P17/D15

A14

P90/SYSCLK

L15

P64/A20

B14

P91/MCLKE

L14

P65/A21

D12

P92/MCLK

K12

P66/A22

P20/D16

E11

P93

L13

P67/A23

P21/D17

C13

M15

P22/D18

D13

M14

P23/D19

C14

P94/SRAS/LABA/AS

N15

EWR3

P24/D20

A15

P95/SCAS/BAA

L12

EWR2

P25/D21

E12

P96/SWE/WR

M13

EWR1

P26/D22

B15

N14

EWR0

P27/D23

E13

P15

ECS

D14

A00

P14

EMRAM

C15

A01

M12

ICD3

D24

F12

A02

L11

ICD2

D25

F13

A03

N13

ICD1

D26

E14

A04

N12

ICD0

D27

F14

A05

P13

D15

A06

R15

E15

A07

M11

BREAK

D28

G12

R14

ICLK

D29

G13

N11

ICS2

D30

G14

A08

P12

ICS1

A10

D31

F15

A09

100

R13

ICS0

B10

G15

A10

101

M10

TRST

C10

H14

A11

102

N10

A11

P80/RDY

H12

A12

103

P11

B11

P81/BGRNT

H13

A13

104

P10

AVRH

D10

P82/BRQ

H15

A14

105

R12

AVR

MB91301/MB91V301

No.

PIN

Pin Name

No.

PIN

Pin Name

No.

PIN

Pin Name

106

R11

AN3

141

176

107

AN2

142

177

108

AN1

143

178

D08/P10

109

AN0

144

179

D09/P11

110

R10

/AVRL

145

180

D10/P12

111

INT0/PG0

146

112

INT1/PG1

147

MD0

113

INT2/PG2

148

MD1

114

INT3/PG3

149

MD2

115

INT4/ATG/PG4

150

116

INT5/SIN2/PG5

151

117

INT6/SOT2/PG6

152

INIT

118

INT7/SCK2/PG7

153

NMI

119

154

120

SIN0/PJ0

155

121

SOT0/PJ1

156

CS0/PA0

122

SCK0/PJ2

157

CS1/PA1

123

SIN1/PJ3

158

CS2/PA2

124

SOT1/PJ4

159

CS3/PA3

125

SCK1/PJ5

160

CS4/TRG2/PA4

126

PPG0/PJ6

161

CS5/PPG2/PA5

127

TRG0/PJ7

162

CS6/PA6

128

TIN0/PH0

163

CS7/PA7

129

TIN1/PPG3/PH1

164

130

TIN2/TRG3/PH2

165

131

166

D00/P00

132

167

D01/P01

133

DREQ0/PB0

168

D02/P02

134

DACK0/PB1

169

D03/P03

135

DEOP0/PB2

170

136

DREQ1/PB3

171

137

DACK1/TRG1/PB4 172

D04/P04

138

DEOP1/PPG1/PB5 173

D05/P05

139

IOWR/PB6

174

D06/P06

140

IORD/PB7

175

D07/P07

MB91301/MB91V301

PIN DESCRIPTIONS

· Except for Power supply , GND, and Tool pins

(Continued)

Pin no.

Pin name

I/O

circuit

type

Function

MB91301

MB91V301

132 to 139

166 to 169,

172 to 175

D00 to D07

External data bus bits 0 to 7. It is available in the external bus
mode.

P00 to P07

Can be used as ports in 8-bit or 16-bit external bus mode.

142 to 144,

1 to 5

178 to 180,

2, 5 to 8

D08 to D15

External data bus bits 08 to 15. It is available in the external bus
mode.

P10 to P17

Can be used as ports in 8-bit or 16-bit external bus mode.

8 to 15

11 to 18

D16 to D23

External data bus bits 16 to 23. It is available in the external bus
mode.

P20 to P27

Can be used as ports in 8-bit external bus mode.

18 to 25

21 to 24,

27 to 30

D24 to D31

External data bus bits 24 to 31. It is available in the external bus
mode.

RDY

[RDY] External ready input. The pin has this function when
external ready input is enabled.

P80

[P80] General purpose input/output port. The pin has this
function when external ready input is disabled.

BGRNT

[BGRNT] Acknowledge output for external bus release.
Outputs "L" when the external bus is released. The pin has this
function when output is enabled.

P81

[P81] General purpose input/output port. The pin has this
function when output is disabled for external bus release
acknowledge.

BRQ

[BRQ] External bus release request input. Input "1" to request
release of the external bus. The pin has this function when input
is enabled.

P82

[P82] General purpose input/output port. The pin has this
function when the external bus release request input is disabled.

[RD] External bus read strobe output.

WR0/ (UUB)

/DQMUU

[WR0] External bus write strobe output. When WR is used as the
write strobe, this becomes the byte-enable pin (UUB). Select
signal (DQMUU) of D31 to D24 at using of SDRAM.

WR1/ (ULB)

/DQMUL

[WR1] External bus write strobe output. The pin has this function
when WR1 output is enabled. When WR is used as the write
strobe, this becomes the byte-enable pin (ULB). Select signal
(DQMUL) of D23 to D16 at using of SDRAM.

P85

[P85] General purpose input/output port. The pin has this
function when the external bus write-enable output is disabled.

MB91301/MB91V301

(Continued)

Pin no.

Pin name

I/O

circuit

type

Function

MB91301 MB91V301

WR2/ (LUB)

/DQMLU

[WR2] External bus write strobe output. The pin has this function
when WR2 output is enabled. When WR is used as the write
strobe, this becomes the byte-enable pin (LUB). Select signal
(DQMLU) of D08 to D05 at using of SDRAM.

P86

[P86] General purpose input/output port. The pin has this function
when the external bus write-enable output is disabled.

WR3/ (LLB)

/DQMLL

[WR3] External bus write strobe output. The pin has this function
when WR3 output is enabled. When WR is used as the write
strobe, this becomes the byte-enable pin (LLB). Select signal
(DQMLL) of D07 to D00 at using of SDRAM.

P87

[P87] General purpose input/output port. The pin has this func-
tions when the external bus write-enable output is disabled.

SYSCLK

[SYSCLK] System clock output. The pin has this function when
system clock output is enabled. This outputs the same clock as
the external bus operating frequency. (Output halts in stop mode.)

P90

[P90] General purpose input/output port. The pin has this function
when system clock output is disabled.

MCLKE

[MCLKE] Clock enable signal for memory.

P91

[P91] General purpose input/output port. The pin has this function
when clock enable output is disabled.

MCLK

[MCLK] Memory clock output. The pin has this function when
memory clock output is enabled. This outputs the same clock as
the external bus operating frequency. (Output halts in sleep
mode.)

P92

[P92] General purpose input/output port. The pin has this function
when memory clock output is disabled.

P93

[P93] General purpose input/output port.

[AS] Address strobe output. The pin has this function when ASE
bit of port function register 9 is enabled "1".

LBA

[LBA] Address strobe output for burst flash ROM. The pin has this
function when ASE bit of port function register 9 is enabled "1".

SRAS

[SRAS] RAS single for SDRAM. This pin has this function when
ASE bit of port function register 9 is enabled "1".

P94

[P94] General purpose input/output port. The pin has this function
when ASE bit of port function register 9 is "0" general purpose
port.

BAA

[BAA] Address advance output for burst Flash ROM. The pin has
this function when BAAE bit of port function register is enabled.

SCAS

[SCAS] CAS signal for SDRAM. This pin has this function when
BAAE bit of port function register is enabled.

P95

[P95] General purpose input/output port. The pin has this function
when BAAE bit of port function register is general purpose port.

MB91301/MB91V301

(Continued)

Pin no.

Pin name

I/O

circuit

type

Function

MB91301 MB91V301

[WR] Memory write strobe output. This pin has this function when
WEXE bit of port function register is enabled.

SWE

[SWE] Write output for SDRAM. This pin has this function when
WEXE bit of port function register is enabled.

P96

[P96] General purpose input/output port. This pin has this function
when WEXE bit of port function register is general purpose port.

45 to 52

54 to 61

A00 to A07

External address bit 0 to 7.

55 to 62

64 to 71

A08 to A15

External address bit 8 to 15.

64 to 71

74 to 81

A16 to A23

External address bit 16 to 23. It is available in external bus mode.

P60 to P67

Can be used as ports when external address bus is not used.

76 to 79

106 to 109

AN3 to

AN0

Analog input pin.

81 to 84

111 to 114

INT0 to

INT3

[INT0 to INT3] External interrupt inputs. These inputs are used
continuously when the corresponding external interrupt is en-
abled. In this case, do not output to these ports unless doing so
intentionally.

PG0 to

PG3

[PG0 to PG3] General purpose input/output ports.

115

INT4

[INT4] External interrupt input. These inputs are used continuously
when the corresponding external interrupt is enabled. In this case,
do not output to these ports unless doing so intentionally.

ATG

[ATG] External trigger input for A/D converter. This input is used
continuously when selected as the A/D converter start trigger. In
this case, do not output to this port unless doing so intentionally.

PG4

[PG4] General purpose input/output ports.

116

INT5

[INT5] External interrupt input. These inputs are used continuously
when the corresponding external interrupt is enabled. In this case,
do not output to these ports unless doing so intentionally.

SIN2

[SIN2] UART2 data input pin. This input is used continuously when
UART2 is performing input. In this case, do not output to this port
unless doing so intentionally.

PG5

[PG5] General purpose input/output port.

117

INT6

[INT6] External interrupt input. This input is used continuously
when the corresponding external interrupt is enabled. In this case,
do not output to these ports unless doing so intentionally.

SOT2

[SOT2] UART2 data output pin. The pin has this function when
UART2 data output is enabled.

PG6

[PG6] General purpose input/output port.

MB91301/MB91V301

(Continued)

Pin no.

Pin name

I/O

circuit

type

Function

MB91301 MB91V301

118

INT7

[INT7] External interrupt input. This input is used continuously
when the corresponding external interrupt is enabled. In this case,
do not output to these ports unless doing so intentionally.

SCK2

[SCK2] UART2 clock input/output pin. The pin has this function
when UART2 clock output is enabled.

PG7

[PG7] General purpose input/output port.

120

SIN0

[SIN0] UART0 data input pin. This input is used continuously when
UART0 is performing input. In this case, do not output to this port
unless doing so intentionally.

PJ0

[PJ0] General purpose input/output port.

121

SOT0

[SOT0] UART0 data output pin. The pin has this function when
UART0 data output is enabled.

PJ1

[PJ1] General purpose input/output port.

122

SCK0

[SCK0] UART0 clock input/output pin. The pin has this function
when UART0 clock output is enabled.

PJ2

[PJ2] General purpose input/output port.

123

SIN1

[SIN1] UART1 data input pin. This input is used continuously
when UART1 is performing input. In this case, do not output to this
port unless doing so intentionally.

PJ3

[PJ3] General purpose input/output port.

124

SOT1

[SOT1] UART1 data output pin. The pin has this function when
UART1 data output is enabled.

PJ4

[PJ4] General purpose input/output port.

125

SCK1

[SCK1] UART1 clock input/output pin. The pin has this function
when UART1 clock output is enabled.

PJ5

[PJ5] General purpose input/output port.

126

PPG0

[PPG0] PPG timer output. This pin has this function when PPG0
output is enabled.

PJ6

[PJ6] General purpose input/output port.

127

TRG0

[TRG0] External trigger input for PPG timer. This input is used
continuously when the corresponding timer input is enabled. In
this case, do not output to this port unless doing so intentionally.

PJ7

[PJ7] General purpose input/output port.

128

TIN0

[TIN0] Reload timer input. This input is used continuously when
the corresponding timer input is enabled. In this case, do not out-
put to this port unless doing so intentionally.

PH0

[PH0] General purpose input/output port.

MB91301/MB91V301

(Continued)

Pin no.

Pin name

I/O

circuit

type

Function

MB91301 MB91V301

129

TIN1

[TIN1] Reload timer input. This input is used continuously when
the corresponding timer input is enabled. In this case, do not out-
put to this port unless doing so intentionally.

PPG3

[PPG3] PPG timer output. The pin has this function when PPG3
output is enabled.

PH1

[PH1] General purpose input/output port.

100

130

TIN2

[TIN2] Reload timer input. This input is used continuously when
the corresponding timer input is enabled. In this case, do not out-
put to this port unless doing so intentionally.

TRG3

[TRG3] External trigger input for PPG timer. This input is used con-
tinuously when the corresponding timer input is enabled. In this
case, do not output to this port unless doing so intentionally.

PH2

[PH2] General purpose input/output port.

103

133

DREQ0

[DREQ0] External input for DMA transfer requests. This input is
used continuously when selected as a DMA activation trigger. In
this case, do not output to this port unless doing so intentionally.

PB0

[PB0] General purpose input/output port.

104

134

DACK0

[DACK0] External acknowledge output for DMA transfer requests.
The pin has this function when outputting DMA transfer request
acknowledgement is enabled.

PB1

[PB1] General purpose input/output port.

105

135

DEOP0

[DEOP0] Completion output for DMA external transfer. The pin
has this function when outputting DMA transfer completion is en-
abled.

PB2

[PB2] General purpose input/output port.

106

136

DREQ1

[DREQ1] DMA External input for DMA transfer requests. This input
is used continuously when selected as a DMA activation trigger. In
this case, do not output to this port unless doing so intentionally.

PB3

[PB3] General purpose input/output port. The pin has this function
when completion output and stop input are disabled for DMA
transfer.

107

137

DACK1

[DACK1] External acknowledge output for DMA transfer requests.
The pin has this function when outputting DMA transfer request
acknowledgement is enabled.

TRG1

[TRG1] External trigger input for PPG timer. This input is used con-
tinuously when the corresponding timer input is enabled. In this
case, do not output to this port unless doing so intentionally.

PB4

[PB4] General purpose input/output port.

MB91301/MB91V301

(Continued)

Pin no.

Pin name

I/O

circuit

type

Function

MB91301 MB91V301

108

138

DEOP1

[DEOP1] Completion output for DMA external transfer. The pin
has this function when outputting DMA transfer completion is en-
abled.

PPG1

[PPG1] PPG timer output. The pin has this function when PPG1
bit is enabled.

PB5

[PB5] General purpose input/output port.

109

139

IOWR

[IOWR] Write strobe output for DMA fly-by transfer. The pin has
this function when outputting a write strobe for DMA fly-by transfer
is enabled.

PB6

[PB6] General purpose input/output port. The pin has this function
when outputting a write strobe for DMA fly-by transfer is disabled.

110

140

IORD

[IORD] Read strobe output for DMA fly-by transfer. The pin has
this function when outputting a read strobe for DMA fly-by transfer
is disabled.

PB7

[PB7] General purpose input/output port. The pin has this function
when outputting a write strobe for DMA fly-by transfer is disabled.

112

143

Clock (oscillation) input.

113

144

Clock (oscillation) output.

116 to

118

147 to 149

MD0 to

MD2

[MD0 to MD2] Mode pins to 0 to 2. The levels applied to these pins
set the basic operating mode. Connect VCC or VSS.

119

152

INIT

External reset input (Reset to initialize settings) ("L" active)

120

053

NMI

NMI (Non Maskable Interrupt) input ("L" active)

122

156

CS0

[CS0] Chip select 0 output. The pin has this function when chip se-
lect 0 output is enabled.

PA0

[PA0] General purpose input/output port. The pin has this function
when chip select 0 output is disabled.

123

157

CS1

[CS1] Chip select 1 output. The pin has this function when chip se-
lect 1 output is enabled.

PA1

[PA1] General purpose input/output port. The pin has this function
when chip select 1 output is disabled.

124

158

CS2

[CS2] Chip select 2 output. The pin has this function when chip se-
lect 2 output are enabled.

PA2

[PA2] General purpose input/output port. The pin has this function
when chip select 2 output is disabled.

125

159

CS3

[CS3] Chip select 3 output. The pin has this function when chip se-
lect 3 output are enabled.

PA3

[PA3] General purpose input/output port. The pin has this function
when chip select 3 output is disabled.

MB91301/MB91V301

(Continued)

* : Shaded pins are only present on the MB91V301.

· Power supply and GND pins

Pin no.

Pin name

I/O

circuit

type

Function

MB91301 MB91V301

126

160

CS4

[CS4] Chip select 4 output. The pin has this function when chip se-
lect 4 output is enabled.

TRG2

[TRG2] External trigger input for PPG timer. This input is used con-
tinuously when the corresponding timer input is enabled. In this
case, do not output to this port unless doing so intentionally.

PA4

[PA4] General purpose input/output port. The pin has this function
when chip select 4 output is disabled.

127

161

CS5

[CS5] Chip select 5 output. The pin has this function when chip se-
lect 5 output are enabled.

PPG2

[PPG2] PPG timer output. The pin has this function when PPG2 bit
is enabled.

PA5

[PA5] General purpose input/output port. The pin has this function
when chip select 5 output and PPG timer outputare disabled.

128

162

CS6

[CS6] Chip select 6 output. The pin has this function when chip se-
lect 6 output is enabled.

PA6

[PA6] General purpose input/output port. The pin has this function
when chip select 6 output are disabled.

129

163

CS7

[CS7] Chip select 7 output. The pin has this function when chip se-
lect 7 output are enabled.

PA7

[PA7] General purpose input/output port. The pin has this function
when chip select 7 output is disabled.

Pin no.

Pin name

Function

MB91301

MB91V301

6, 16, 26, 43, 53,

63, 101, 114, 130,

140

3, 9, 19, 25, 31, 41, 47, 52,

62, 72, 94, 131, 142, 145,

154, 164, 170, 176

GND pins.
Connect all pins at the same potential.

7, 17, 27, 44, 54,
72, 89, 111, 115,

121, 131, 141

4, 10, 20, 26, 32, 42, 48, 53,
63, 73, 82, 83, 95, 119, 141,

146, 150, 151, 155, 165,

171, 177

3 V power supply pins.
Connect all pins at the same potential.

103

Analog power supply pin for A/D converter

104

AVRH

Reference power supply pin for A/D converter

105

AVR

Capacitor coupling pin for the A/D converter

110

/AVRL

Analog GND pin for A/D converter

OPEN

Open pin. Use at open

102

102, 132

Capacitor coupling pin for the internal regula-
tor

MB91301/MB91V301

(Continued)

Type

Circuit

Remarks

· CMOS level output

No standby control

· With Pull-up control

Pull-up resistor value

25 k

approx. (Typ)

· CMOS level I/O

with standby control

· With Pull-up control
· I

4 mA

· With Pull-up control

Pull-up resistor value

25 k

approx. (Typ)

· CMOS level output

CMOS level hysteresis input
with standby control

· I

4 mA

· With Pull-up control

Pull-up resistor value

25 k

approx. (Typ)

· CMOS level output

CMOS level hysteresis input
no standby control

· I

4 mA

· CMOS level hysteresis input

no standby control

Digital input

Digital output

Digital input

Pull-up control

Standby control

Digital output

Digital input

Pull-up control

Standby control

Digital output

Digital input

Pull-up control

Digital input

MB91301/MB91V301

HANDLING DEVICES

MB91301/MB91V301

·
·
·
·

Operation at start-up

Always apply a settings initialization (INIT) to the INIT pin immediately after turning on the power.
Also, in order to provide a delay while the oscillator circuits stabilize immediately after start-up, maintain the "L"
level input to the INIT pin for the required stabilization delay time. (The initialization processing (INIT) triggered
by the INIT pin initializes the oscillation stabilization delay time to the minimum setting.)

·
·
·
·

External clock input at start-up

At power-on start-up, always input a clock signal until the oscillation stabilization delay time is ended.

·
·
·
·

Output indeterminate at power-on time

When the power is turned on, the output pin may remain indeterminate until the internal power supply becomes
stable.

·
·
·
·

Built-in DC/DC regulator

This device has a built-in regulator, requiring 3.3 V input to the Vcc pin and a bypass capacitor of approximately
4.7

F connected to the C pin for the regulator.

·
·
·
·

Note on use of the A/D converter

As the MB91301/MB91V301 contains an A/D converter, be sure to supply power to AVcc at 3.3 V and insert a
capacitor of at least 0.05

F between the AVR pin and the AVss/AVRL pin.

3.3 V

AVR

AVRH

/AVRL

GND

0.05

4.7

MB91301/MB91V301

Note of built-in DC/DC regulator

3.3 V

AVR

AVRH

/AVRL

0.05

MB91301/

MB91V301

Note on Use of A/D Converter

MB91301/MB91V301

·
·
·
·

Preventing Latchup

When CMOS integrated circuit devices are subjected to applied voltages higher than V

at input and output

pins, or to voltages lower than V

, as well as when voltages in excess of rated levels are applied between V

and V

, a phenomenon known as latchup can occur. When a latchup condition occurs, the supply current can

increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take
sufficient care to avoid exceeding maximum ratings.

·
·
·
·

Power supply pins

Devices with multiple V

and V

supply pins are designed to prevent problems such as latchup occurring by

providing internal connections between pins at the same potential. However, in order to reduce unwanted
radiation, prevent abnormal operation of strobe signals due to a rise in ground level, and to maintain the total
output current ratings, all such pins should always be connected externally to power supply or ground. Also,
ensure that the impedance of the V

and V

connections to the power supply are as low as possible.

In addition, it is recommended that a bypass capacitor of approximately 0.1

F be connected between V

and

. Connect the capacitor close to the V

and V

pins.

·
·
·
·

Crystal oscillators

Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Printed circuit boards
should be designed so that the X0 and X1 pins, crystal (or ceramic) oscillator, and bypass capacitor connected
to ground are placed as close together as possible.
Also, to ensure stable operation, it is strongly recommended that the printed circuit board art work be designed
such that the X0 and X1 pins are surrounded by ground.

·
·
·
·

Treatment of NC and OPEN pins

Pins marked as "NC" or "OPEN" must be left open-circuit.

·
·
·
·

Treatment of unused input pins

If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistors.

·
·
·
·

Mode pins (MD0 to MD2)

These pins should be connected directly to V

or V

. To prevent the device erroneously switching to test mode

due to noise, design the printed circuit board such that the distance between the mode pins and V

or V

as short as possible and the connection impedance is low.

·
·
·
·

Remarks for External Clock Operation

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at
"H" output in stop mode) .
When operating at 12.5 MHz or less, the microcontroller can be used with the clock signal supplied only to pin X0.
"Using an external clock (normal) and (12.5 MHz) " shows examples of how the MB91301 uses the external clock.

MB91301/MB91V301

·
·
·
·

Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.

·
·
·
·

Clock control block

For L-level input to the INIT pin, allow for the regulator settling time or oscillation settling time.

·
·
·
·

Bit search module

The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only word-
accessible.

·
·
·
·

I/O port access

Byte access only for access to port

·
·
·
·

Shared port function switching

To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are
switched depending on external bus settings.

·
·
·
·

D-bus memory

Do not set a code area in D-bus memory.
No instruction fetch is performed to the D-bus.
Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can cause the micro-
controller to lose control.
Do not set a data area in I-bus memory.

MB91301/MB91V301

Using an external clock (normal)

Note: Stop mode (oscillation stop mode) can not be used.

OPEN

MB91301/MB91V301

Using an external clock (12.5 MHz Max)

MB91301/MB91V301

·
·
·
·

I-bus memory

Do not set a stack area or vector table in I-bus memory.

It may cause a hang during EIT processing (including RETI).

Recovery from the hang requires a reset.

Do not perform DMA transfer to I-bus memory.

Do not access data in the instruction cache control register or the instruction cache RAM immediately before
the RETI instruction.

·
·
·
·

Low-power consumption modes

To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the
TBCR, or time-base counter control register) and be sure to use the following sequence:

(LDI

#value_of_standby, R0)

(LDI

#_STCR, R12)

STB

R0, @R12

; Write to standby control register (STCR)

LDUB

@R12, R0

; Read STCR for synchronous standby

LDUB

@R12, R0

; Read STCR again for dummy read

NOP

; NOP x 5 for timing adjustment

NOP
NOP
NOP
NOP

Set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt handler
triggers the microcontroller to return from the standby mode.

If you use the monitor debugger, follow the precautions below:

Do not set a breakpoint within the above array of instructions.
Do not single-step the above instructions.

·
·
·
·

Prefetch

When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits).
Byte or halfword access results in wrong data read.

·
·
·
·

Terminal and timing control register (TCR)

The terminal and timing control register (TCR) is a write-only register. Do not therefore use a bit manipulation
instruction to access the TCR.
To disable bus sharing by setting the BREN bit as bit 7 in the TCR from 1 to 0, be sure to follow the procedure
below. Failure to follow it may hang the device.

1) Write 0 to the BRQE bit as bit 2 in the port-8 function register (PFR8).
2) Write 0 to the BREN bit as bit 7 in the TCR.

·
·
·
·

MCLK and SYSCLK

MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either
depending on each application.

MB91301/MB91V301

·
·
·
·

Pull-up control

When function pins listed in the AC specifications (such as external bus control pins) have pull-up control,
enabling the pull-up resistor for a pin causes the actual pin load conditions to change. As all AC specifications
for this device were measured under the condition of pull-up resistors disabled, the values are not guaranteed
of AC specifications when pull-up resistors are enabled.

Even if the pull-up resistor is set to enabled for a pin, if the HIZ bit in the standby control register (STCR) specifies
setting output pins to high impedance during stop mode (HIZ

1) , changing to stop mode (STOP

1) causes

the pull-up resistor to be disabled.

·
·
·
·

R15 (General purpose register)

When any of the following instructions is executed, the SSP* or USP* value is not used as R15, resulting in an
incorrect value written to memory.

* : R15 is a virtual register. When a program attempts to access R15, the SSP or USP is accessed depending

on the status of the "S" flag as an SP flag. When coding the above ten instructions using an assembler,
specify a general-purpose register other than R15.

·
·
·
·

Notes on the PS register

Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the microcon-
troller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs oper-
ations before and after the EIT as specified in either case.

The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as those in (1) above.

The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the

same value as that in (1) above.

·
·
·
·

A/D converter

When the device is turned on or returns from a reset or stop, it takes time for the external capacitor to be charged,
requiring the A/D converter to wait for at least 10 ms.

·
·
·
·

Watchdog timer

The watchdog timer function of this model monitors that a program delays a reset within a certain period of time
and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once
the watchdog timer function is enabled, therefore, the watchdog timer countinues to operate until a reset takes
place.

An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under
a condition in which the CPU stops program execution.

Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of
control. If this is the case, use the external INIT pin to cause a reset (INIT) .

AND

R15, @Ri

ANDH

R15, @Ri

ANDB

R15, @Ri

ORH

R15, @Ri

ORB

R15, @Ri

EOR

R15, @Ri

EORH

R15, @Ri

EORB

R15, @Ri

XCHB

@Rj, R15

MB91301/MB91V301

Unique to the evaluation chip MB91V301

·
·
·
·

Tool reset

On an evaluation board, use the chip with INIT and TRST connected together.

·
·
·
·

Simultaneous occurrences of a software break and a user interrupt/NMI

When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause
the following phenomena:

The debugger stops pointing to a location other than the programmed breakpoints.

The halted program is not re-executed correctly.

If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has
been used, avoid setting any break at the relevant location.

·
·
·
·

Single-stepping the RETI instruction

If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly
after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being
executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant
interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.

·
·
·
·

Operand break

A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data
event break to access to the area containing the address of a system stack pointer.

·
·
·
·

ICE startup sequence

When using the ICE, when you start debugging, ensure that the bus configuration is set correctly for the area
being used before downloading. After turning on the power to the target, the states of the RD and WR0 to WR3
pins are undefined until you perform the above setting. Accordingly, include enabling pull-up as part of the startup
sequence. If using these pins as general-purpose ports, set as output ports to prevent conflict with the output
signals during the time the pin states are undefined.

* : Use as output ports.

External bus width

Pin name

32 bit

16 bit

8 bit

Pull-up

WR0

Pull-up

WR1 (P85)

Pull-up

WR2 (P86)

Pull-up

WR3 (P87)

Pull-up

MB91301/MB91V301

·
·
·
·

Configuration batch file

The example batch file below sets the mode vector and sets up the CS0 configuration register for the download
area. Use values appropriate to the hardware in the wait, timing, and other settings.

#---------------------------------------------------------
# Set MODR (0x7fd) =Enable In memory+16 bit External Bus
set mem/byte 0x7fd=0x5
#---------------------------------------------------------
# Set ASR0 (0x640) ; 0x0010_0000 - 0x002f_ffff
set mem/halfword 0x640=0x0010
#---------------------------------------------------------
# Set ACR0 (0x642)
#

; ASZ [3:0]=0101:2 MByte

; DBW [1:0]=01:16 bit width, automatically set from

MODR
#

; BST [1:0]=00:1 burst (16 bit x 2)

; SREN=0:Disable BRQ

; PFEN=1:Enable Pre fetch buffer

; WREN=1:Enable Write operation

; LEND=0: Big endian

; TYPE [3:0]=0010:WEX: Disable RDY

set mem/harfword 0x642=0x5462
#---------------------------------------------------------
# Set AWR0 (0x660)
#

; W15-12=0010:auto wait=2

; WR07, 06=01:RD, WR delay=1cycle

; W05, 04=01:WR->WR delay=1cycle (for WEX)

; W03 =1:MCLK->RD/WR delay=0.5cycle

;

:for async Memory

; W02 =0:ADR->CS delay=0

; W01 =0:ADR->RD/WR setup 0cycle

; W00 =RD/WR->ADR hold 0cycle

set mem/halfword 0x660=0x2058
#---------------------------------------------------------

MB91301/MB91V301

BLOCK DIAGRAM

I-Cache 4 KB

DMAC 5 ch

SDRAM I/F

PORT I/F

FR CPU

Core

Bus

Converter

32 to 16

Adapter

3 ch

UART

3 ch

U-TIMER

4 ch

A/D

X0, X1

MD0 to MD2

INIT

INT0 to INT7

NMI

SIN0 to SIN2

SOT0 to SOT2

SCK0 to SCK2

AN0 to AN3

AVR, ATG

AVRH, AV

/AVRL

TIN0 to TIN2

DREQ0, DREQ1

DACK0, DACK1

DEOP0, DEOP1

IOWR

IORD

A23 to A00

D31 to D16

D15 to D0

RD, WR

WR0 to WR3

CS0 to CS7

RDY

BRQ

BGRNT

SYSCLK

MCLK

MCLKE

SRAS

SCAS

SWE

DQMUU, L

DQMLU,L

LBA

BAA

PORT

PPG0 to PPG3

TRG0 to TRG3

Bit search

RAM 4 Kbytes

(stack)

Clock

control

Interrupt

controller

8 ch
External interrupts

4 ch
PPG timer

3 ch
Reload timer

External memory

I/F

MB91301/MB91V301

CPU

Memory Space

The FR family has 4 GB (2

addresses) of logical address space with linear access from the CPU.

Direct Addressing Areas

The following areas of address space are used for I/O operations.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The direct areas differ according to the size of the data accessed, as follows.

Memory map

Note : Each mode is set depending on the mode vector fetch after INIT is negated. (For mode setting, see "

MODE

SETTINGS".)

byte data access

: 000

to 0FF

half word data access : 000

to 1FF

word data access

: 000

to 3FF

0000 0000

0000 0400

0001 0000

0002 0000

0003 E000

0003 F000

0004 0000

0004 2000

0006 0000

0010 0000

FFFF FFFF

I/O

I-RAM

* : On specific area between 10000

and 2000

, 4 Kbyte RAM can be used.

External ROM/

External bus mode

(volume production)

Direct
addressing
area

External

area

Internal RAM

4 Kbytes

Internal ROM/

External bus mode

(Evaluation product)

(at MODR register ROMA

Access

prohibited

External ROM/

External bus mode

(Evaluation product)

(at MODR register ROMA

External

area

External

area

External

area

External

area

External

area

Access

prohibited

Access

prohibited

Internal RAM

8 Kbytes

Internal RAM

8 Kbytes

See "

I/O MAP"

I/O

Internal RAM

8 Kbytes

Access

prohibited

Direct
addressing
area

See "

I/O MAP"

I/O

See "

I/O MAP"

I/O

MB91301/MB91V301

Registers

The FR series has two types of registers: application-specific registers in the CPU and general purpose registers
in memory.

Dedicated registers

PC (Program Counter)

The PC is the program counter and stores the address of the currently executing instruction.

Table base register (TBR)

The TBR is the table base register and stores the top address of the vector table used by the EIT function.

Program counter (PC)

: 32-bit register. Stores the current instruction address.

Program status (PS)

: 32-bit register. Contains the register pointer and condition code.

Table base register (TBR)

: Stores the top address of the vector table used by the EIT (exception/interrupt/

trap) function.

Return pointer (RP)

: Stores the subroutine return address.

System stack pointer (SSP) : Points to the system stack area.

User stack pointer (USP)

: Points to the user stack area.

Multiplication and division
result register (MDH/MDL)

: 32-bit registers used for multiplication and division.

TBR

SSP

USP

MDH

MDL

XXXX XXXX

0000 0000

000F FC00

32 bit

Program counter

Program status

Table base register

Return pointer

System stack pointer

User stack pointer

Multiplication and division
result register

Initial value

TBR

MB91301/MB91V301

Program status (PS)

This register holds the program status and is divided into the ILM, SCR, and CCR.

Condition code register (CCR)

System condition code register (SCR)

Interrupt level mask register(ILM)

S flag

: Specifies which stack pointer to use as R15.

I flag

: Enables or disables user interrupt requests.

N flag

: Indicates the sign when an operation result is represented as a 2's complement integer.

Z flag

: Indicates whether an operation result is zero.

V flag

: Indicates whether an overflow occurred for an operation result when the operation operand is

represented as a 2's complement integer.

C flag

: Indicates whether an operation resulted in a borrow or a carry from the most significant bit.

D1, D0 flags

: Stores intermediate data for stepwise multiplication operations.

T flags

: A flag specifying whether the step trace trap function is enabled or not.

ILM4 to ILM0 : This register stores the interrupt level mask value. The value in the ILM register is used as

the level mask. Only interrupt requests to the CPU that have an interrupt level that is higher
than the level specified in ILM are accepted.

Initial Value

ILM4

ILM3

ILM2

ILM1

ILM0

Interrupt Level

01111

High

(Medium)

Low

ILM

Bit position

ILM

SCR

CCR

Initial Value

- - 00XXXX

CCR

Initial Value

XX0

SCR

MB91301/MB91V301

MODE SETTINGS

In the FR series, the mode is set by the mode pins (MD2, 1, 0) and mode register (MODR).

Mode Pins

The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.

Values other than those listed in the table are prohibited.

* : Single-chip mode is not set.

Mode Register (MODR)

· Details of mode register (MODR)

The data written to the mode register by the mode vector fetch operation (see "3.11.3 reset sequences") is
called the mode data.
After the data is set to the mode register (MODR), the device operates with the operating mode specified by
this data. The mode register is set by all types of reset. The register cannot be written to by user programs.

<Details of mode register (MODR) >

<Details of mode data>

[bit31 to bit27] Reserved bits

These bits should always be set to "00000." If set to any other value, stable operation is not assured.

Mode Pins

Mode name

Reset vector access

area

Remarks

MD2

MD1

MD0

Internal ROM vector mode

Internal

Single-chip mode*

External ROM vector mode

External

The bus width is specified by the
mode register.

bit

Initial Value

Address

XXXXXXXX

ROMA

WTH1

WTH0

Operation mode setting bits

bit

Initial Value

Address

XXXXXXXX

ROMA

WTH1

WTH0

Operation mode setting bits

MB91301/MB91V301

· Operating mode

· Bus mode

The bus mode controls the operations of internal ROM and the external access function. It is specified with
the mode setting pins (MD2, MD1, MD0) and the ROMA bit in mode data.

· Access mode

The access mode controls the external data bus width. It is specified with the WTH1 and WTH0 bits in the
mode register and the DBW1 and DBW0 bits in area configuration registers 0 to 7 (ACR0 to ACR7).

· Bus Modes

The FR family has three bus modes: bus mode 0 (single-chip mode), bus mode 1 (internal-ROM, external-bus
mode), and bus mode 2 (external-ROM, external-bus mode).
The MB91301 supports only bus mode 2 (external-ROM, external-bus mode).
See "Memory Space" in

CPU for details.

· Bus mode 2 (External-ROM, external-bus mode)

This mode enables internal I/O and D-bus RAM, in which any access is access to external space. Some
external pins serve as bus pins.

Bus mode

Access mode

32-bit bus width

External ROM, external bus

16-bit bus width

8-bit bus width

MB91301/MB91V301

I/O MAP

This shows the location of the various peripheral resource registers in the memory space.

[How to read the table]

Note : Initial values of register bits are represented as follows :

"1" : Initial value"1"

"0" : Initial value"0"

"X" : Initial value"X"

"-"

: No physical register at this location

address

register

block

+
+
+
+

000000

PDR0 [R/W]

XXXXXXXX

PDR1 [R/W]

XXXXXXXX

PDR2 [R/W]

XXXXXXXX

PDR3 [R/W]

XXXXXXXX

T-unit

Port Data Register

Read/write attribute, Access type

Location of left-most register (When using word access,
the register in column 1 is in the MSB side of the data.)

Initial value after a reset

MB91301/MB91V301

(Continued)

Address

Register

Block

+
+
+
+

000000

PDR0 [R/W] B

XXXXXXXX

PDR1 [R/W] B

XXXXXXXX

PDR2 [R/W] B

XXXXXXXX

T-unit

Port Data

000004

PDR6 [R/W] B

XXXXXXXX

000008

PDR8 [R/W] B

XXXXXXXX

PDR9 [R/W] B

XXXXXXX

PDRA [R/W] B

XXXXXXXX

PDRB [R/W] B

XXXXXXXX

00000C

000010

PDRG [R/W] B

XXXXXXXX

PDRH [R/W] B

XXX

PDRJ [R/W] B

XXXXXXXX

R-bus

Port Data

000014

00003C

Reserved

000040

EIRR [R/W] B, H, W

00000000

ENIR [R/W] B, H, W

00000000

ELVR [R/W] B, H, W

00000000

Ext int

000044

DICR [R/W] B, H, W

HRCL [R/W] B, H, W

11111

DLYI/I-unit

000048

TMRLR0 [W] H, W

XXXXXXXX XXXXXXXX

TMR0 [R] H, W

XXXXXXXX XXXXXXXX

Reload

Timer 0

00004C

TMCSR0 [R/W] B, H, W

XX0000 00000000

000050

TMRLR1 [W] H, W

XXXXXXXX XXXXXXXX

TMR1 [R] H, W

XXXXXXXX XXXXXXXX

Reload

Timer 1

000054

TMCSR1 [R/W] B, H, W

XX0000 00000000

000058

TMRLR2 [W] H, W

XXXXXXXX XXXXXXXX

TMR2 [R] H, W

XXXXXXXX XXXXXXXX

Reload

Timer 2

00005C

TMCSR2 [R/W] B, H, W

XX0000 00000000

000060

SSR0 [R/W] B, H, W

00001000

SIDR0 [R]

SODR0 [W] B, H, W

XXXXXXXX

SCR0 [R/W] B, H, W

00000100

SMR0 [R/W] B, H, W

UART0

000064

UTIM0 [R] H, W (UTIMR0 [W] H, W)

00000000 00000000

DRCL0 [W] B

UTIMC0 [R/W] B

00001

U-TIMER 0

000068

SSR1 [R/W] B, H, W

00001000

SIDR1 [R]

SODR1 [W] B, H, W

XXXXXXXX

SCR1 [R/W] B, H, W

00000100

SMR1 [R/W] B, H, W

UART1

00006C

UTIM1 [R] H, W (UTIMR1 [W] H, W )

00000000 00000000

DRCL1 [W] B

UTIMC1 [R/W] B

00001

U-TIMER 1

MB91301/MB91V301

(Continued)

Address

Register

Block

+
+
+
+

000070

SSR2 [R/W] B, H, W

00001000

SIDR2 [R]

SODR2 [W] B, H, W

XXXXXXXX

SCR2 [R/W] B, H, W

00000100

SMR2 [R/W] B, H, W

UART2

000074

UTIM2 [R] H, W (UTIMR2 [W] H, W )

00000000 00000000

DRCL2 [W] B

UTIMC2 [R/W] B

00001

U-TIMER 2

000078

ADCR [R] B, H, W

000000XX XXXXXXXX

ADCS [R/W] B, H, W

00000000 00000000

A/D

Converter

Sequential

Comparator

00007C

ADCR0 [R] B, H, W

XXXXXXXX

ADCR1 [R] B, H, W

XXXXXXXX

ADCR2 [R] B, H, W

XXXXXXXX

ADCR3 [R] B, H, W

XXXXXXXX

000080

000117

Reserved

000118

GCN10 [R/W] H

00110010 00010000

GCN20 [R/W] B

00000000

PPG timer

000011C

Reserved

000120

PTMR0 [R] H

11111111 11111111

PCSR0 [W] H, W

XXXXXXXX XXXXXXXX

PPG0

000124

PDUT0 [W] H, W

XXXXXXXX XXXXXXXX

PCNH0 [R/W] B

00000000

PCNL0 [R/W] B

000000X0

000128

PTMR1[R] H

11111111 11111111

PCSR1 [W] H, W

XXXXXXXX XXXXXXXX

PPG1

00012C

PDUT1 [W] H, W

XXXXXXXX XXXXXXXX

PCNH1 [R/W] B

00000000

PCNL1 [R/W] B

000000X0

000130

PTMR2 [R] H

11111111 11111111

PCSR2 [W] H, W

XXXXXXXX XXXXXXXX

PPG2

000134

PDUT2 [W] H, W

XXXXXXXX XXXXXXXX

PCNH2 [R/W] B

00000000

PCNL2 [R/W] B

000000X0

000138

PTMR3[R] H

11111111 11111111

PCSR3 [W] H, W

XXXXXXXX XXXXXXXX

PPG3

00013C

PDUT3 [W] H, W

XXXXXXXX XXXXXXXX

PCNH3 [R/W] B

00000000

PCNL3 [R/W] B

000000X0

000140

0001FC

Reserved

000200

DMACA0 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMAC

000204

DMACB0 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000208

DMACA1 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

MB91301/MB91V301

(Continued)

Address

Register

Block

+
+
+
+

00020C

DMACB1 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

DMAC

000210

DMACA2 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

000214

DMACB2 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000218

DMACA3 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

00021C

DMACB3 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000220

DMACA4 [R/W] B, H, W*

00000000 0000XXXX XXXXXXXX XXXXXXXX

000224

DMACB4 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000228

00023C

Reserved

000240

DMACR [R/W] B

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

DMAC

000244

000300

Reserved

000304

ISIZE [R/W] B, H, W

I-Cache

000308

0003E0

Reserved

0003E4

ICHCR [R/W] B, H, W

000000

I-Cache

0003E8

0003EF

Reserved

0003F0

BSD0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search

Module

0003F4

BSD1 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8

BSDC [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FC

BSRR [R] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

MB91301/MB91V301

(Continued)

Address

Register

Block

+
+
+
+

000400

DDRG [R/W] B

00000000

DDRH [R/W] B

000

DDRJ [R/W] B

00000000

R-bus Data

Direction

000404

00040C

Reserved

000410

PFRG [R/W] B

PFRH [R/W] B

PFRJ [R/W] B

R-bus Port

Function

000414

00041C

Reserved

000420

PCRG [R/W] B

00000000

PCRH [R/W] B

000

PCRJ [R/W] B

00000000

R-bus

Pull-up

Resistance

Control

000424

00043C

Reserved

000440

ICR00 [R/W] B, H, W

11111

ICR01 [R/W] B, H, W

11111

ICR02 [R/W] B, H, W

11111

ICR03 [R/W] B, H, W

11111

Interrupt

Controller

000444

ICR04 [R/W] B, H, W

11111

ICR05 [R/W] B, H, W

11111

ICR06 [R/W] B, H, W

11111

ICR07 [R/W] B, H, W

11111

000448

ICR08 [R/W] B, H, W

11111

ICR09 [R/W] B, H, W

11111

ICR10 [R/W] B, H, W

11111

ICR11 [R/W] B, H, W

11111

00044C

ICR12 [R/W] B, H, W

11111

ICR13 [R/W] B, H, W

11111

ICR14 [R/W] B, H, W

11111

ICR15 [R/W] B, H, W

11111

000450

ICR16 [R/W] B, H, W

11111

ICR17 [R/W] B, H, W

11111

ICR18 [R/W] B, H, W

11111

ICR19 [R/W] B, H, W

11111

000454

ICR20 [R/W] B, H, W

11111

ICR21 [R/W] B, H, W

11111

ICR22 [R/W] B, H, W

11111

ICR23 [R/W] B, H, W

11111

000458

ICR24 [R/W] B, H, W

11111

ICR25 [R/W] B, H, W

11111

ICR26 [R/W] B, H, W

11111

ICR27 [R/W] B, H, W

11111

00045C

ICR28 [R/W] B, H, W

11111

ICR29 [R/W] B, H, W

11111

ICR30 [R/W] B, H, W

11111

ICR31 [R/W] B, H, W

11111

000460

ICR32 [R/W] B, H, W

11111

ICR33 [R/W] B, H, W

11111

ICR34 [R/W] B, H, W

11111

ICR35 [R/W] B, H, W

11111

000464

ICR36 [R/W] B, H, W

11111

ICR37 [R/W] B, H, W

11111

ICR38 [R/W] B, H, W

11111

ICR39 [R/W] B, H, W

11111

000468

ICR40 [R/W] B, H, W

11111

ICR41 [R/W] B, H, W

11111

ICR42 [R/W] B, H, W

11111

ICR43 [R/W] B, H, W

11111

MB91301/MB91V301

(Continued)

Address

Register

Block

+
+
+
+

00046C

ICR44 [R/W] B, H, W

11111

ICR45 [R/W] B, H, W

11111

ICR46 [R/W] B, H, W

11111

ICR47 [R/W] B, H, W

11111

Interrupt

Controller

000470

00047C

000480

RSRR [R/W] B, H, W

10000000 (INIT)

00 (INIT)

XXX

X00 (RST)

STCR [R/W] B, H, W

00110011 (INIT)

00111111 (HST)

0011XX11 (INIT)

00X1XXX (RST)

TBCR [R/W] B, H, W

00XXXX00 (INIT)

00XXXXXX (RST)

CTBR [W] B, H, W

XXXXXXXX (INIT)

XXXXXXXX (RST)

Clock

Control unit

000484

CLKR [R/W] B, H, W

00000000 (INIT)

XXXXXXXX (RST)

WPR [W] B, H, W

XXXXXXXX (INIT)

XXXXXXXX (RST)

DIVR0 [R/W] B, H, W

00000011 (INIT)

XXXXXXXX (RST)

DIVR1 [R/W] B, H, W

00000000 (INIT)

XXXXXXXX (RST)

000488

0005FC

Reserved

000600

DDR0 [R/W] B

00000000

DDR1 [R/W] B

00000000

DDR2 [R/W] B

00000000

T-unit

Data

Direction

000604

DDR6 [R/W] B

00000000

000608

DDR8 [R/W] B

00000000

DDR9 [R/W] B

0000000

DDRA [R/W] B

00000000

DDRB [R/W] B

00000000

00060C

000610

T-unit

Port

Function

000614

PFR6 [R/W] B

11111111

000618

PFR8 [R/W] B

111

PFR9 [R/W] B

0000111

PFRA1 [R/W] B

11111111

PFRB1 [R/W] B

00000000

00061C

PFRB2 [R/W] B

000

PFRA2 [R/W] B

000620

PCR0 [R/W] B

00000000

PCR1 [R/W] B

00000000

PCR2 [R/W] B

00000000

T-unit

Pull-up

Resistance

Control

000624

PCR6 [R/W] B

00000000

000628

PCR8 [R/W] B

00000000

PCR9 [R/W] B

000

PCRA [R/W] B

00000000

PCRB [R/W] B

00000000

00062C

000630

00063C

Reserved

MB91301/MB91V301

(Continued)

Address

Register

Block

+
+
+
+

000640

ASR0 [R/W] H, W

00000000 00000000

ACR0 [R/W] H, W

1111XX00 00000000

T-unit

000644

ASR1 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR1 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000648

ASR2 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

00064C

ASR3 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000650

ASR4 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000654

ASR5 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000658

ASR6 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

00065C

ASR7 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000660

AWR0 [R/W] B, H, W

01111111 11111011

AWR1 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000664

AWR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000668

AWR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

00066C

AWR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000670

MCRA [R/W] B, H, W

XXXXXXXX

MCRB [R/W] B, H, W

XXXXXXXX

000674

000678

IOWR0 [R/W] B, H,

XXXXXXXX

IOWR1 [R/W] B, H,

XXXXXXXX

IOWR2 [R/W] B, H, W

XXXXXXXX

00067C

000680

CSER [R/W] B, H, W

00000001

CHER [R/W] B, H,

11111111

TCR [R/W] B, H, W

00000000 (INIT)

0000XXXX (RST)

000684

RCR [R/W] B, H, W

00XXXXXX XXXX0XXX

00068C

0007F8

Reserved

0007FC

MODR [W] *

XXXXXXXX

T-unit

MB91301/MB91V301

(Continued)

Address

Register

Block

+
+
+
+

000800

000AFC

Reserved

000B00

ESTS0 [R/W] B

X0000000

ESTS1 [R/W] B

XXXXXXXX

ESTS2 [R] B

1XXXXXXX

DSU

(Evaluation

chip only)

000B04

ECTL0 [R/W] B

0X000000

ECTL1 [R/W] B

00000000

ECTL2 [W] B

000X0000

ECTL3 [R/W] B

00X00X11

000B08

ECNT0 [W] B

XXXXXXXX

ECNT1 [W] B

XXXXXXXX

EUSA [W] B

XXX00000

EDTC [W] B

0000XXXX

000B0C

EWPT [R] H

00000000 00000000

ECTL4 [R] ([R/W]) B

0X00000

ECTL5 [R] ([R/W]) B

000X

000B10

EDTR0 [W] H

XXXXXXXX XXXXXXXX

EDTR1 [W] H

XXXXXXXX XXXXXXXX

000B14

000B1C

000B20

EIA0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B24

EIA1 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B28

EIA2 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B2C

EIA3 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B30

EIA4 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B34

EIA5 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B38

EIA6 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B3C

EIA7 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B40

EDTA [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B44

EDTM [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B48

EOA0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B4C

EOA1 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B50

EPCR [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

MB91301/MB91V301

(Continued)

*1 : Byte access is not permitted for the lower 16 bits of DMAC0 to DMAC4 (DTC15 to DTC0) .

*2 : This register is accessed through mode vector fetch; it cannot be accessed in normal mode.

Address

Register

Block

+
+
+
+

000B54

EPSR [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B58

EIAM0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B5C

EIAM1 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B60

EOAM0/EODM0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B64

EOAM1/EODM1 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B68

EOD0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B6C

EOD1 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B70

000FFC

Reserved

001000

DMASA0 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMAC

001004

DMADA0 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001008

DMASA1 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00100C

DMADA1 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001010

DMASA2 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001014

DMADA2 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001018

DMASA3 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00101C

DMADA3 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001020

DMASA4 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001024

DMADA4 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001028

001FFC

Reserved

MB91301/MB91V301

INTERRUPT VECTORS

(Continued)

Interrupt

Interrupt No.

Interrupt

level*

Offset

TBR default

address*

Reset

3FC

000FFFFC

Mode vector

3F8

000FFFF8

System reserved

3F4

000FFFF4

System reserved

3F0

000FFFF0

System reserved

3EC

000FFFEC

System reserved

3E8

000FFFE8

System reserved

3E4

000FFFE4

Coprocessor absent trap

3E0

000FFFE0

Coprocessor error trap

3DC

000FFFDC

INTE instruction

3D8

000FFFD8

Instruction break exception

3D4

000FFFD4

Operand break trap

3D0

000FFFD0

Step trace trap

3CC

000FFFCC

NMI request (tool)

3C8

000FFFC8

Undefined instruction exception

3C4

000FFFC4

NMI request

15 (F

)

fixed

3C0

000FFFC0

External interrupt 0

ICR00

3BC

000FFFBC

External interrupt 1

ICR01

3B8

000FFFB8

External interrupt 2

ICR02

3B4

000FFFB4

External interrupt 3

ICR03

3B0

000FFFB0

External interrupt 4

ICR04

3AC

000FFFAC

External interrupt 5

ICR05

3A8

000FFFA8

External interrupt 6

ICR06

3A4

000FFFA4

External interrupt 7

ICR07

3A0

000FFFA0

Reload timer 0

ICR08

39C

000FFF9C

Reload timer 1

ICR09

398

000FFF98

Reload timer 2

ICR10

394

000FFF94

UART0 (RX completed)

ICR11

390

000FFF90

UART1 (RX completed)

ICR12

38C

000FFF8C

UART2 (RX completed)

ICR13

388

000FFF88

UART0 (TX completed)

ICR14

384

000FFF84

UART1 (TX completed)

ICR15

380

000FFF80

UART2 (TX completed)

ICR16

37C

000FFF7C

MB91301/MB91V301

(Continued)

Interrupt

Interrupt No.

Interrupt

level*

Offset

TBR default

address*

DMAC0 (end, error)

ICR17

378

000FFF78

DMAC1 (end, error)

ICR18

374

000FFF74

DMAC2 (end, error)

ICR19

370

000FFF70

DMAC3 (end, error)

ICR20

36C

000FFF6C

DMAC4 (end, error)

ICR21

368

000FFF68

A/D

ICR22

364

000FFF64

PPG0

ICR23

360

000FFF60

PPG1

ICR24

35C

000FFF5C

PPG2

ICR25

358

000FFF58

PPG3

ICR26

354

000FFF54

System reserved

ICR27

350

000FFF50

U-TIMER0

ICR28

34C

000FFF4C

U-TIMER1

ICR29

348

000FFF48

U-TIMER2

ICR30

344

000FFF44

Time base timer overflow

ICR31

340

000FFF40

System reserved

ICR32

33C

000FFF3C

System reserved

ICR33

338

000FFF38

System reserved

ICR34

334

000FFF34

System reserved

ICR35

330

000FFF30

System reserved

ICR36

32C

000FFF2C

System reserved

ICR37

328

000FFF28

System reserved

ICR38

324

000FFF24

System reserved

ICR39

320

000FFF20

System reserved

ICR40

31C

000FFF1C

System reserved

ICR41

318

000FFF18

System reserved

ICR42

314

000FFF14

System reserved

ICR43

310

000FFF10

System reserved

ICR44

30C

000FFF0C

System reserved

ICR45

308

000FFF08

System reserved

ICR46

304

000FFF04

Delay interrupt bit

ICR47

300

000FFF00

System reserved (Used by REALOS)

2FC

000FFEFC

System reserved (Used by REALOS)

2F8

000FFEF8

System reserved

2F4

000FFEF4

MB91301/MB91V301

(Continued)

*1 : ICRs are registers built in the interrupt controller to set interrupt levels for individual interrupt requests.

The ICRs are provided for the different interrupt levels.

*2 : The TBR is the register holding the start address of the EIT vector table.

The TBR value and the offset value preset for each EIT source are added together to be the vector address.

Note: The 1-KB area from the TBR address is the EIT vector area.

The vector size is 4 bytes and the relationship between vector number and vector address is expressed as
follows:

Interrupt

Interrupt No.

Interrupt

level*

Offset

TBR default

address*

System reserved

2F0

000FFEF0

System reserved

2EC

000FFEEC

System reserved

2E8

000FFEE8

System reserved

2E4

000FFEE4

System reserved

2E0

000FFEE0

System reserved

2DC

000FFEDC

System reserved

2D8

000FFED8

System reserved

2D4

000FFED4

System reserved

2D0

000FFED0

System reserved

2CC

000FFECC

System reserved

2C8

000FFEC8

System reserved

2C4

000FFEC4

System reserved

2C0

000FFEC0

Used by INT instruction

80
to

255

50
to

2BC

000

000FFEBC

000FFC00

Vctadr

TBR

vctofs

TBR

(3FC

vct)

vctadr : vector address

vctofs : vector offset

vct

: vector number

MB91301/MB91V301

INSTRUCTION CACHE

The instruction cache is a fast local memory for temporary storage. Once an instruction code is accessed from
external slower memory, the instruction cache holds the instruction code inside to increase the speed of access-
ing the same code from then on.
By setting the RAM mode, the instruction cache data RAM is made directly read/write-accessible by software.

Configuration

· FR family's basic instruction length : Two bytes
· Block layout : Two-way set associative
· Blocks : 128 blocks per way

16 bytes per block (

4 sub-blocks)

4 bytes per sub-block (

1 bus access unit)

Instruction Cache Configuration

4 bytes

Way 1

Way 2

128 block

128

block

Cash tag

Sub

block 3

Sub

block 3

Sub

block 2

Sub

block 1

Sub

block 0

Sub

block 3

Sub

block 2

Sub

block 1

Sub

block 0

Sub

block 3

Sub

block 2

Sub

block 1

Sub

block 0

block 127

Sub

block 2

Sub

block 1

Sub

block 0

MB91301/MB91V301

Instruction Cache Tags

[bit 31 to bit 9] Address tag

The address tag stores the upper 23 bits of the memory address of the instruction cached in the corresponding
block.
For example, memory address IA of the instruction data stored in sub-block k in block i is obtained from the
following equation:

address tag

The address tag is used to check for a match with the instruction address requested for access by the CPU.
The CPU and cache behave as follows depending on the result of the tag check:

· When the requested instruction data exists in the cache (hit), the cache transfers the data to the CPU within

the cycle.

· When the requested instruction data does not exist in the cache (miss), the CPU and cache obtain the data

loaded by external access at the same time.

[bit 7 to bit4] SBV3 to SBV0 : Sub-block validation

When SBV

contains "1", the corresponding sub-block holds the current instruction data at the address located

by the tag. Each sub-block usually holds two instructions (excluding immediate-value transfer instructions).

[bit 3] TAGV : Tag validation bit

This bit indicates whether the address tag value is valid. When the bit contains "0", the corresponding block is
invalid regardless of the settings of the sub-block validation bits. (The bit is set to "0" when the cache is flushed.)

[bit 1] LRU (only in way 1)

This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the
last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1
is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed.

[bit 0] ETLK : Entry lock

This bit is used to lock all the entries in the block corresponding to the tag in the cache. When the ETLK bit is
set to "1", the entries are locked and are not updated when a cache miss occurs. Note, however, that invalid
sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entry lock states, access to
external memory takes place after losing one cycle used for evaluating the cache miss.

SBV2

SBV3

SBV1

SBV0

TAGV

LRU

ETLK

SBV2

SBV3

SBV1

SBV0

TAGV

ETLK

Address tag

Way 1

Way 2

Address tag

Vacancy

MB91301/MB91V301

Control Registers

Cache Size Register (ISIZE)

Instruction Cache Control Register (ICHCR)

The instruction cache (I-cache) control register (ICHCR) controls the operations of the instruction cache.
Writing a value to the ICHCR has no effect on the caching of any instruction fetched within three cycles that follow.

bit

Initial value

Address : 00000307

- - - - - - 10

R/W

SIZE1

R/W

SIZE0

bit

Initial value

Address : 000003E7

0 - 000000

R/W

RAM

GBLK

ALFL

EOLK

ELKR

FLSH

R/W

ENAB

Address
00010000

00010200

00010400

00010600

00010800

00010FFF

TAG RAM
00010000

00010004

00010008

0001000C

00010010

00010014

00014000

00014200

00014400

00014600

00014800

00014FFF

00018000

00018200

00018400

00018600

00018800

00018FFF

0001C000

0001C200

0001C400

0001C600

0001C800

0001CFFF

Cache RAM
00018000

00018004

00018008

0001800C

00018010

00018014

Cache off

RAM off

Cache off

RAM on

TAG1

TAG2

IRAM1

$RAM1

IRAM2

$RAM2

<TAG1>

<TAG2>

<IRAM1>

<$RAM1>

<IRAM2>

IRAM1

IRAM2

IRAM1

IRAM2

<IRAM1>

<IRAM2>

IRAM1

IRAM2

<IRAM1>

<IRAM2>

<$RAM2>

TAG1

TAG2

$RAM1

$RAM2

<TAG1>

<TAG2>

<$RAM1>

<$RAM2>

TAG1

TAG2

$RAM1

$RAM2

<TAG1>

<TAG2>

<TAG1>

<TAG2>

<$RAM1>

<$RAM2>

IRAM1

IRAM2

TAG1

TAG2

$RAM1

$RAM2

<TAG1>

<TAG2>

<TAG1>

<TAG2>

<TAG1>

<TAG2>

<TAG1>

<TAG2>

<$RAM1>

<$RAM2>

Cache 4 K

RAM off

Cache 4 K

RAM on

Cache 2 K

RAM off

Cache 2 K

RAM on

Cache 1 K

RAM off

Cache

RAM on

TAG1

TAG RAM (way1)

TAG2

TAG RAM (way2)

Mirror area

RAM on/off

RAM bit

I/O

$RAM1

Cahce RAM (way1) IRAM1

I-Bus RAM (way1)

$RAM2

Cahce RAM (way2) IRAM1

I-Bus RAM (way2)

Entry at address 00x

Mirror of 00x

Entry at address 00x

Mirror of 00x

Instruction at address 000 (SBV0)
Instruction at address 004 (SBV1)
Instruction at address 008 (SBV2)
Instruction at address 00C (SBV3)
Instruction at address 010 (SBV0)
Instruction at address 014 (SBV1)

MB91301/MB91V301

PERIPHERAL RESOURCES

External Bus Interface Controller

·
·
·
·

External Bus Interface Controller Features

· Maximum output address width = 32-bit (4 GB memory space)
· Various different types of external memory (8-bit, 16-bit, or 32-bit devices) can be directly connected and the

controller can support multiple devices with different access timings.
Asynchronous SRAM, asynchronous ROM/FLASH memory (supports multiple write strobe access or byte-
enable access)
Page mode ROM/FLASH memory (2, 4, or 8 page size)
Burst mode ROM/FLASH memory
Address/data multiplexed bus (8-bit or 16-bit width only)
Synchronous memory (built-in ASIC memory, etc.)

Note:

Synchronous SRAM cannot be directly connected.

· Memory can be divided into eight independent banks (chip select areas) with a separate chip select output

for each bank.
The size of each area can be set in 64 Kbyte increments (the size of each chip select area can range from
64 Kbyte to 2 Gbyte)
Each area can be located anywhere in the physical address space (subject to boundary limitations based on
the area size)

· The following functions can be set independently for each chip select area :

Chip select area enable/disable (Access is not performed to disabled areas)
Setting of an access timing type to support each type of memory (For SDRAM, only the CS6 and CS7 areas
can be connected.)
Detailed access timing settings (wait cycles and similar settings for each access type)
Data bus width (8-bit, 16-bit, 32-bit)
Byte-ordering setting (big or little endian)

Note:

The CS0 area must be big endian.

Write-prohibit setting (read-only areas)
Enable or disable loading into built-in cache
Enable or disable prefetch function
Maximum burst length setting (1, 2, 4, 8)

· Different detailed timing settings can be set for each timing type

Even for the same type, different settings can be used for each chip select area.
Up to 15 auto-wait cycles can be specified. (For asynchronous SRAM, ROM, Flash, and I/O areas)
The bus cycle can be extended by the external RDY input. (For asynchronous SRAM, ROM, Flash, and I/O
areas)
Fast access wait and page wait settings are supported (For burst/page mode ROM and Flash areas)
Idle cycles, recovery cycles, setup delays, and similar can be inserted.
Capable of setting timing values such as the CAS latency and RAS-CAS delay (SDRAM area)
Capable of controlling the distributed/centralized auto-refresh, self-refresh, and other refresh timings (SDRAM
area)

· DMA supports fly-by transfer

Transfer between memory and I/O can be performed by a single access.
Memory wait cycles can be synchronized with the I/O wait period during fly-by transfer.
Hold times can be maintained by extending access to the data source only.
Separate idle and recovery cycle settings can be specified for use in fly-by transfer.

· Supports external bus arbitration using BRQ and BGRNT.
· Pins not used by the external interface can be set as general purpose I/O ports.

MB91301/MB91V301

ASR0

ACR0

ASR1

ACR1

ASR2

ACR2

ASR3

ACR3

ASR4

ACR4

ASR5

ACR5

ASR6

ACR6

ASR7

ACR7

AWR0

AWR1

AWR2

AWR3

AWR4

AWR5

AWR6

RCR

MCRA

MCRB

IOWR0

IOWR1

CSER

CHER

TCR

(MODR)

AWR7

Reserved

Notes :

Reserved indicates a reserved register. When writing, always set to "0".

The MODR register cannot be accessed by the user program.

Area select registers 0 to 7 (ASR0 to ASR7)
Area configuration registers 0 to 7 (ACR0 to ACR7)

Area weight register (AWR0 to AWR7)

Memory setting register
(For SDRAM/FCRAM auto-precharge OFF mode) (MCRA)

Memory setting register
(For FCRAM auto-precharge ON mode) (MCRB)

DMAC I/O wait registers (IOWR0 and IOWR1)

Chip-select area enable register (CSER)

Cache fetch enable register (CHER)

Terminal and timing control register (TCR)

Refresh control register (RCR)

MB91301/MB91V301

I/O Ports

MB91301/MB91V301 pins can be used as I/O ports when not set for use by the external bus interface or the
various peripheral I/O functions.

I/O port (with pull-up resistor) block diagram

Note : For port output, the pull-up resistor is disabled irrespective of the setting.

I/O ports with pull-up resistors have the following registers :

PDR (Port Data Register)

DDR (Data Direction Register)

PFR (Port Function Register)

PCR (Pull-up Control Register)

I/O ports have three following modes
· When port is in input mode (PFR

"0" & DDR

"0")

PDR read : Reads the level of the corresponding external pin.
PDR write : Writes the value to the PDR.

· When port is in output mode (PFR

"0" & DDR

"1")

PDR read : Reads the PDR value.
PDR write : Outputs the PDR value to the corresponding external pin.

· When port is in peripheral output mode (PFR

"1" & DDR

"X")

PDR

: Reads the value of the corresponding peripheral output.

PDR write : Writes the value to the PDR.

Port Bus

PDR

PFR

DDR

PCR

PDR
DDR
PFR
PCR

: Port Data Register
: Data Direction Register
: Port Function Register
: Pull-up Control Register

Peripheral output

PDR read

Peripheral input

Pull-up resistor
(approx. 25 k

)

PCR

0 : No pull-up resistor

PCR

1 : Use pull-up resistor

MB91301/MB91V301

Notes :

Use byte access to access ports.

The external bus function has priority for port 0 to port A when these are used as external bus pins.

Accordingly, writing to the DDR has no effect on the pin input/output setting while the pins are operating
as external bus pins. The value set in the DDR becomes meaningful when the PFR register is modified
to set the pins as general purpose ports.

In stop mode (HIZ = 0), the pull-up resistor control register setting is used.

In stop mode (HIZ = 1), the pull-up resistor control register setting is ignored during hardware standby.

Using pull-up resistors is prohibited when these pins are used as external bus pins. In this case, do not

write '1" to the corresponding bit in the pull-up control register (PCR).

MB91301/MB91V301

Port Data Register (PDR)

PDR0 to PDR2, PDR6, PDR8 to PDRB, PDRG, PDRH and PDRJ are the I/O data registers for the I/O pots.

The corresponding PDR0 to DDRJ and PFR6 to PFRJ registers control input/output.

P00 to P07, P10 to P17 and P20 to P27 do not have a PFR (port function register).

PDR0

Initial value

Address : 00000000

XXXXXXXX

PDR1

Initial value

Address : 00000001

XXXXXXXX

PDR2

Initial value

Address : 00000002

XXXXXXXX

PDR6

Initial value

Address : 00000006

XXXXXXXX

PDR8

Initial value

Address : 00000008

XXXXXXXX

PDR9

Initial value

Address : 00000009

- XXXXXXX

PDRA

Initial value

Address : 0000000A

XXXXXXXX

PDRB

Initial value

Address : 0000000B

XXXXXXXX

PDRG

Initial value

Address : 00000010

XXXXXXXX

PDRH

Initial value

Address : 00000011

- - - - - XXX

PDRJ

Initial value

Address : 00000013

XXXXXXXX

R/W

P06

P07

P05

P04

P03

P02

P01

P00

P16

P17

P15

P14

P13

P12

P11

P10

R/W

P26

P27

P25

P24

P23

P22

P21

P20

R/W

P66

P67

P65

P64

P63

P62

P61

P60

R/W

P86

P87

P85

P84

P83

P82

P81

P80

R/W

P96

P95

P94

P93

P92

P91

P90

R/W

PA6

PA7

PA5

PA4

PA3

PA2

PA1

PA0

R/W

PB6

PB7

PB5

PB4

PB3

PB2

PB1

PB0

R/W

PG6

PG7

PG5

PG4

PG3

PG2

PG1

PG0

R/W

PH2

PH1

PH0

R/W

PJ6

PJ7

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

R/W

MB91301/MB91V301

Data Direction Register (DDR)

DDR0 to DDR2, DDR6, DDR8 to DDRB, DDRG, DDRH and DDRJ control the direction (input or output) of each
bit in the corresponding port.

When PFR

0 DDR

0 : Port input

DDR

1 : Port output

When PFR

1 DDR

0 : Peripheral input

DDR

1 : Peripheral output

DDR0

Initial value

Address : 00000600

00000000

DDR1

Initial value

Address : 00000601

00000000

DDR2

Initial value

Address : 00000602

00000000

DDR6

Initial value

Address : 00000606

00000000

DDR8

Initial value

Address : 00000608

00000000

DDR9

Initial value

Address : 00000609

- 0000000

DDRA

Initial value

Address : 0000060A

00000000

DDRB

Initial value

Address : 0000060B

00000000

DDRG

Initial value

Address : 00000400

00000000

DDRH

Initial value

Address : 00000401

- - - - - 000

DDRJ

Initial value

Address : 00000403

00000000

R/W

P06

P07

P05

P04

P03

P02

P01

P00

P16

P17

P15

P14

P13

P12

P11

P10

R/W

P26

P27

P25

P24

P23

P22

P21

P20

R/W

P66

P67

P65

P64

P63

P62

P61

P60

R/W

P86

P87

P85

P84

P83

P82

P81

P80

R/W

P96

P95

P94

P93

P92

P91

P90

R/W

PA6

PA7

PA5

PA4

PA3

PA2

PA1

PA0

R/W

PB6

PB7

PB5

PB4

PB3

PB2

PB1

PB0

R/W

PG6

PG7

PG5

PG4

PG3

PG2

PG1

PG0

R/W

PH2

PH1

PH0

R/W

PJ6

PJ7

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

R/W

MB91301/MB91V301

Pull-up Resistor Control Register (PCR)

PCR0 to PCR2, PCR6, PCR8 to PCRB, PCRG, PCRH and PCRJ control the pull-up resistors for the corre-
sponding port.

PCR

0 : No pull-up resistor

PCR

1 : Use pull-up resistor

PCR0

bit

Initial value

Address :

00000620

00000000

PCR1

bit

Initial value

Address :

00000621

00000000

PCR2

bit

Initial value

Address :

00000622

00000000

PCR6

bit

Initial value

Address :

00000626

00000000

PCR8

bit

Initial value

Address :

00000628

00000000

PCR9

bit

Initial value

Address :

00000629

- 000 - - 0 -

PCRA

bit

Initial value

Address :

0000062A

00000000

PCRB

bit

Initial value

Address :

0000062B

00000000

PCRG

bit

Initial value

Address :

00000420

00000000

PCRH

bit

Initial value

Address :

00000421

- - - - - 000

PCRJ

bit

Initial value

Address :

00000423

00000000

R/W

P06

P07

P05

P04

P03

P02

P01

P00

P16

P17

P15

P14

P13

P12

P11

P10

R/W

P26

P27

P25

P24

P23

P22

P21

P20

R/W

P66

P67

P65

P64

P63

P62

P61

P60

R/W

P86

P87

P85

P84

P83

P82

P81

P80

R/W

P96

P95

P94

P91

R/W

PA6

PA7

PA5

PA4

PA3

PA2

PA1

PA0

R/W

PB6

PB7

PB5

PB4

PB3

PB2

PB1

PB0

R/W

PG6

PG7

PG5

PG4

PG3

PG2

PG1

PG0

R/W

PH2

PH1

PH0

R/W

PJ6

PJ7

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

R/W

MB91301/MB91V301

· Port Function Register (PFR)

PFR6, PFR8 to PFRB, PFRA2, PFRG, PFRH and PFRJ control the output for the corresponding external bus
interface or peripheral output bit.
Always write "0" to unused bits in the PFR.

PFR6

bit

Initial value

Address :

00000616

11111111

PFR8

bit

Initial value

Address :

00000618

111 - - 0 - -

PFR9

bit

Initial value

Address :

00000619

- 0000111

PFRA1

bit

Initial value

Address :

0000061A

11111111

PFRB1

bit

Initial value

Address :

0000061B

00000000

PFRB2

bit

Initial value

Address :

0000061C

0000 - - 00

PFRA2

bit

Initial value

Address :

0000061E

- 0 - - - - - -

PFRG

bit

Initial value

Address :

00000410

00 - - - - - -

PFRH

bit

Initial value

Address :

00000411

- - - - - - 0 -

PFRJ

bit

Initial value

Address :

00000413

- 000 - 00 -

A22E

A23E

A21E

A20E

A19E

A18E

A17E

A16E

R/W

WR2XE

WR3XE

WR1XE

BRQE

R/W

WRXE

BAAE

ASXE

MCKE

MCKEE

SYSE

R/W

CS6XE

CS7XE

CS5XE

CS4XE

CS3XE

CS2XE

CS1XE

CS0XE

R/W

AK12

DES1

AK11

AK10

DES0

AK02

AK01

AK00

R/W

DWRE

DRDE

PPE1

AKH1

AKH0

R/W

PPE2

R/W

SOE2

SCE2

R/W

PPE3

R/W

PPE0

SCE1

SOE1

SCE0

SOE0

R/W

MB91301/MB91V301

Interrupt Controller

The interrupt controller receives and processes interrupts.

·
·
·
·

Hardware Configuration

The interrupt controller consists of the following :
· ICR register
· Interrupt priority determination circuit
· Interrupt level and interrupt number (vector) generator
· Hold request removal request generator

·
·
·
·

Principal Functions

The main functions of the interrupt controller are as follows :
· Detect NMI and interrupt requests
· Prioritize interrupts (according to level and number)
· Notify interrupt level of selected interrupt request (to CPU)
· Notify interrupt number of selected interrupt request (to CPU)

If an NMI or interrupt request with an interrupt level other than "11111

" occurs, notify recovery from stop mode

(to CPU)

· Generate hold request removal requests to the bus master

Block Diagram

RI00

RI47

(DLYIRQ)

LEVEL4 to

LEVEL0

MHALTI

VCT5 to

VCT0

R-BUS

UNMI

WAKEUP

ICR00

ICR47

("1" when LEVEL

11111

)

Determine order of priority

NMI

processing

LEVEL

determination

VECTOR

determination

LEVEL,

VECTOR

genera-

tion

HLDREQ

removal

request

MB91301/MB91V301

(Continued)

Address :

bit

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

00000440

00000441

00000442

00000443

00000444

00000445

00000446

00000447

00000448

00000449

0000044A

0000044B

0000044C

0000044D

0000044E

0000044F

00000450

00000451

00000452

00000453

00000454

00000455

00000456

00000457

00000458

00000459

0000045A

0000045B

0000045C

0000045D

0000045E

0000045F

MB91301/MB91V301

(Continued)

Address :

bit

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

ICR4

ICR3

ICR2

ICR1

ICR0

MHALTI

LVL4

LVL3

LVL2

LVL1

LVL0

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

HRCL

00000460

00000461

00000462

00000463

00000464

00000465

00000466

00000467

00000468

00000469

0000046A

0000046B

0000046C

0000046D

0000046E

0000046F

0000045

MB91301/MB91V301

External Interrupt/NMI Control Block

The external interrupt control block controls external interrupt requests input to the NMI and INT0 to INT7 pins.
The interrupt trigger level can be selected from "H", "L", "rising edge", or "falling edge" (except for NMI).

Block Diagram

INT0 to INT7
NMI

R-BUS

Interrupt

request

Interrupt enable register

Gate

Request F/F

Edge detection circuit

Interrupt request register

Interrupt level setting register

External interrupt enable register (ENIR)

External interrupt request register (EIRR)

Request level setting register (ELVR)

bit

EN6

EN7

EN5

EN4

EN3

EN2

EN1

EN0

ER6

ER7

ER5

ER4

ER3

ER2

ER1

ER0

LA7

LB7

LB6

LA6

LB5

LA5

LB4

LA4

LA3

LB3

LB2

LA2

LB1

LA1

LB0

LA0

MB91301/MB91V301

PPG Timer

The PPG timer can output highly precise PWM waveforms efficiently.
The MB91301/MB91V301 contains four channels of PPG timer.

Features of the PPG Timer

· Each channel consists of a 16-bit down counter, a 16-bit data register with cycle setting buffer, a 16-bit compare

· The count clocks for the 16-bit down counter can be selected from the following four types :

Internal clock

/4,

/16,

/64

· The counter is initialized to "FFFF

" at a reset or counter borrow.

· Each channel has a PPG output.
· Register outline

Cycle setting register: Reload data register with buffer
Duty setting register: Compare register with buffer
Transfer from the buffer takes place upon a counter borrow.

· Pin control overview

A duty match sets the pin control section to 1. (Preferential)
A counter borrow resets it to 0.
The output value fix mode is available, which can each output all "L" (or "H").
A polarity can also be specified.

· An interrupt request can be generated at a combination of the following events :

Activation of the PPG timer
Counter borrow (cycle match)
Duty match
Counter borrow (cycle match) or duty match

DMA transfer can be initiated by the above interrupt request.

· It is possible to set the simultaneous activation of two or more channels by means of software or another

interval timer.
Restarting during operation can also be set.

· The request level to be detected can be selected from among "rising edge", "falling edge", and "both edges".

MB91301/MB91V301

16-Bit Reload Timer

The 16-bit timer consists of a 16-bit down-counter, 16-bit reload register, prescaler for generating the internal
count clock, and a control register.
The clock source can be selected from three internal clock signals (machine clock divided by 2, 8, or 32) or the
external event.
The interrupt can be used to initiate DMA transfer.
The MB91301/MB91V301 has three 16-bit reload timer channels.

Block Diagram

RELD

INTE

CNTE

TRG

OUT
CTL.

CSL1

CSL0

MOD0

MOD1

MOD2

IN CTL.

EXCK

IRQ

B
U
S

16-bit reload register (TMRLR)

16-bit down counter (TMR) UF

Reload

Clock selector

Re-trigger

Prescaler

clear

External trigger input (TI)

External

trigger

selection

Count enable

CLKP input

MB91301/MB91V301

U-TIMER (16 bit timer for UART baud rate generation)

The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set
using the combination of the chip operating frequency and U-TIMER reload value.
The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event.
The MB91301/MB91V301 has three U-TIMER channels. When used as an interval timer, two U-TIMER channels
can be connected in cascade for a maximum count interval of up to 2

Cascade connection is only available for channel 0 and channel 1 or channel 0 and channel 2.

Block Diagram

UTIMR (reload register)

UTIM (timer)

clock

load

underflow

under flow U-TIMER 1

to UART

control

f.f.

MUX

Channel 0

only

(CLKP)

(Peripheral clock)

MB91301/MB91V301

UART

The UART is a serial I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission.
The MB91301/MB91V301 has three UART channels.

·
·
·
·

UART Features

· Full duplex double buffer
· Asynchronous (start-stop synchronized) or CLK synchronized transmission
· Supports multi-processor mode
· Fully programmable baud rate

The internal timer can be set to any desired baud rate (see "8. U-TIMER" description)

· Variable baud rate can be input from an external clock.
· Error detection functions (parity, framing, overrun)
· Transmission signal format is NRZ
· The interrupt can be used to initiate DMA transfer.
· The DMAC interrupt can be cleared by writing to the DRCL register.

· U-TIMER (UTIM)

UTIM contains the timer value. Use a 16-bit transfer instruction to access the register.

Reload register (UTIMR)

UTIMR is the register that contains the value to be reloaded to UTIM when UTIM causes an underflow.
Use a 16-bit transfer instruction to access the register.

Address

bit

Initial value

000064

(ch.0)

00006C

(ch.1)

000074

(ch.2)

00000000

Address

bit

Initial value

000064

(ch.0)

00006C

(ch.1)

000074

(ch.2)

00000000

UTIMR

UTIM

UTIMC

8 7

b14

b15

b14

b15

MB91301/MB91V301

10. A/D Converter (Successive Approximation Type)

The A/D converter converts analog input voltages to digital values.

·
·
·
·

A/D Converter Features

· Peripheral clock (CLKP) 140 clock cycle
· Minimum conversion time 4.1

s/ch (for machine clock 34 MHz

CLKP)

· Built-in sample & hold circuit
· Resolution

10-bit

· 4 channel program-selectable analog inputs

Single conversion mode : Convert 1 specified channel
Scan conversion mode : Continuous conversion of multiple channels. Conversion can be specified for up

to 4 channels.

· Single, continuous, and stop conversion operation is supported.

Single conversion mode

: Convert specified channel then stop.

Continuous conversion mode : Perform continuous conversion for the selected channel.
Stop conversion mode

: Perform conversion for one channel, then wait for the next activation trigger
(synchronizes the conversion start timing)

· DMA transfer can be initiated by an interrupt.
· Selectable conversion activation trigger: Software, external trigger (falling edge), or reload timer (rising edge)

MB91301/MB91V301

Block Diagram

AN0

AN1

AN2

AN3

AVRH

AVR

B
U
S

Input switch

Sample & hold circuit

Channel decoder

Internal voltage

generator

Successive

approximation register

Data register

(ADCR : 10 bit)

A/D control register

(ADCS)

ATG (External pin trigger)

Reload timer ch2
(internal connection)

Timing generation circuit

Prescaler

Machine clock

(CLKP)

Data register

(ADCR0 to ADCR7 : 8

Upper 8 bit COPY

Control status register (ADCS)

Data register (ADCR)

Conversion result register (ADCR0 to ADCR3)

bit

INT

BUSY

INTE

CRF

STS1

STS0

STRT

MD0

MD1

ANS2

ANS1

ANS0

ANE2

ANE1

ANE0

MB91301/MB91V301

11. DMAC (DMA Controller)

The DMA controller is used to perform DMA (direct memory access) transfer on the FR series device.
Using DMA transfer under the control of the DMA controller improves system performance by enabling data to
be transferred at high speed independently of the CPU.

·
·
·
·

Hardware Configuration

· Independent DMA channels

5 ch

· 5 ch independent access control circuits
· 32-bit address register (Supports reloading : 2 per channel)
· 16-bit transfer count register (Supports reloading : 1 per channel)
· 4-bit block count register (1 per channel)
· External transfer request input pins : DREQ0, DREQ1 (ch0, 1 only)
· External transfer request acknowledge output pins : DACK0, DACK1 (ch0, 1 only)
· DMA completion output pins : DEOP0, DEOP1 (ch0, 1 only)
· fly-by transfer (memory to I/O , I/O to memory) (ch0, 1 only)
· Two-cycle transfer

·
·
·
·

Main Functions of the DMA Controller

· Supports independent data transfer for multiple channels (5 channels)

(1) Priority order (ch.0

ch.1

ch.2

ch.3

ch.4)

(2) Order can be reversed for ch0 and ch1
(3) DMAC activation triggers

Input from dedicated external pin (edge detection/level detection, ch0,1 only)

Request from built-in peripheral (shared interrupt request, including external interrupts)

Software request (register write)

(4) Transfer modes

Demand transfer, burst transfer, step transfer, or block transfer

Addressing mode: Full 32-bit address (increment/decrement/fixed)
(address increment can be in the range

255 to

255)

Data type : byte/half-word/word

Single-shot or reload operation selectable

MB91301/MB91V301

Block Diagram

Read
Write

DDNO

BLK register

DDNO register

DTCR

DSS [3:0]

ERIR, EDIR

TYPE, MOD, WS

IRQ
[4:0]

MCLREQ

X-bus

DADM, DASZ [7:0] DADR

SDAM, SASZ [7:0] SADR

DMA transfer

request to bus

controller

Read/write

control

To bus

controller

Bus control block

Access

ad-

dress

Addr

ess counter

Counter buffer

Selector

Write back

Selector

Buffer

Counter

Selector

Write back

DTC two-stage register

Buffer

Counter

Selector

DMA

start trigger

selection cir-

cuit & request

acknowledge

control

Priority

circuit

Status

transition

circuit

DMA control

DSAD two-stage register

DDAD

two-stage register

Bus control block

Peripheral start request/

Stop input

External pin start

request/Stop input

To interrupt controller

Clear peripheral interrupt

5-channel DMAC block diagram

Write back

MB91301/MB91V301

ch.0 control/status

ch.1 control/status

ch.2 control/status

ch.3 control/status

ch.4 control/status

Overall control register

ch.0 transfer source address register

ch.0 transfer destination address register

ch.1 transfer source address register

ch.1 transfer destination address register

ch.2 transfer source address register

ch.2 transfer destination address register

ch.3 transfer source address register

ch.3 transfer destination address register

ch.4 transfer source address register

ch.4 transfer destination address register

(bit) 31

24 23

16 15

08 07

(bit) 31

24 23

16 15

08 07

0000200

0000204

0000208

000020C

0000210

0000214

0000218

000021C

0000220

0000224

0000240

0001000

0001004

0001008

000100C

0001010

0001014

0001018

000101C

0001020

0001024

DMACA0

DMACB0

DMACA1

DMACB1

DMACA2

DMACB2

DMACA3

DMACB3

DMACA4

DMACB4

D M A C R

DMASA0

DMADA0

DMASA1

DMADA1

DMASA2

DMADA2

DMASA3

DMADA3

DMASA4

DMADA4

MB91301/MB91V301

12. Clock Generation Control

The internal operating clock is generated as follows in MB91301/MB91V301.

Source clock selection : Selects the clock source.

Base clock generation : The base clock is generated by dividing the source clock by 2 or using a PLL.

Generation in each internal block : The base clock is divided to generate the operating clock for each block.

(Continued)

RSRR : Reset initiation register/Watchdog timer control register

* : Changes depending on what triggered the reset.

: Not initialized

STCR : Standby control register

* : Only when asserted during a reset initiated by the INIT pin. Otherwise, same as INIT.

bit

address : 00000480

Initial value (INIT pin)

Initial value (INIT)

Initial value (RST)

bit

address : 00000481

Initial value (INIT pin)

Initial value (HST) *

Initial value (INIT)

Initial value (RST)

R/W

HSTB

INIT

WDOG

SRST

WT1

WT0

R/W

SLEEP

R/W

STOP

HIZ

SRST

OS1

OS0

OSCD1

MB91301/MB91V301

(Continued)

TBCR : Timebase counter control register

CTBR : Timebase counter clear register

CLKR : Clock source control register

WPR : Watchdog reset generation delay register

DIVR0 : Base clock division setting register 0

DIVR1 : Base clock division setting register 1

bit

address : 00000482

Initial value (INIT)

Initial value (RST)

bit

address : 00000483

Initial value (INIT)

Initial value (RST)

bit

address : 00000484

Initial value (INIT)

Initial value (RST)

bit

address : 00000485

Initial value (INIT)

Initial value (RST)

bit

address : 00000486

Initial value (INIT)

Initial value (RST)

bit

address : 00000487

Initial value (INIT)

Initial value (RST)

R/W

0
0

R/W

X
X

R/W

X
X

R/W

X
X

R/W

TBIE

R/W

0
0

TBIF

TBC2

TBC1

TBC0

SYNCR SYNCS

X
X

R/W

PLL1S2

PLL1S1 PLL1S0

PLL1EN CLKS1

CLKS0

X
X

R/W

MB91301/MB91V301

Block Diagram

PLL

1/2

B
U
S

DIVR0, 1 register

[Clock generator]

CPU clock division

Stop control

CPU clock

(CLKB)

Peripheral clock

(CLKP)

External bus

clock (CLKT)

Peripheral clock

division

External bus clock

division

CLKR register

Osc

illa-

tion

circu

[Stop/sleep

controller]

STCR register

Stop state

Internal interrupt

Internal reset

State

transi-

tion

con-

trol cir-

cuit

SLEEP state

Reset F/F

Internal reset (RST)

Internal reset (INIT)

[Reset circuit]

RSRR register

WPR register

CTBR register

Watchdog F/F

TBCR register

Timebase counter

Overflow detection F/F

Interrupt enable

[Watchdog controller]

Timebase timer

interrupt request

Selec-

Selector

HST pin

RST pin
INIT pin

Selector

Count clock

Selec-

tor

Selec-

tor

MB91301/MB91V301

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

0 V)

*1 : V

must not be lower than V

0.3 V.

*2 : AV

, AVRH and AVRL should not exceed V

0.3 V, including at power-on. AVRH and AVRL should not exceed

. Also AVRL should not exceed AVRH.

*3 : The maximum output current is the peak value for a single pin.

*4 : The average output current is the average current for a single pin over a period of 100ms.

*5 : The total average output current is the average current for all pins over a period of 100ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter

Symbol

Rating

Unit

Remaeks

Min

Max

Supply voltage

0.5

4.0

Analog supply voltage

0.5

4.0

Analog reference voltage

AVRH,

AVRL

0.5

Input voltage

0.3

Analog pin input voltage

0.3

Output voltage

0.3

"L" level maximum output
current

"L" level average output current

OLAV

"L" level total maximum output
current

100

"L" level total average output
current

OLAV

"H" level maximum output
current

"H" level average output current

OHAV

"H" level total maximum output
current

"H" level total average output
current

OHAV

Power consumption

1000

Operating temperature

Storage temperature

STG

150

MB91301/MB91V301

Recommended Operating Conditions

0 V)

<Notes on turning the power on>
The maximum power rising slope (

t) must be 0.05 V/

s when the 3 V power supply is turned on.

It takes about 100

s until the 2.5 V power supply becomes stable after the 3 V power supply becomes stable.

Keep INIT input during that interval.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

Parameter

Symbol

Value

Unit

Remarks

Min

Max

Supply voltage

3.0

3.6

Normal operation

Analog supply voltage

3.6

Analog reference voltage

AVRH

AVRL

AVRH

Operating temperature

MB91301/MB91V301

DC Characteristics

3.0 V to 3.6 V , V

0 V, Ta

C to

*1 : Excludes X0, X1, pins with internal pull-up resistor (INIT, TRST), and pins with a pull-up resistor set by PCR.

*2 : Values enclosed in brackets ( ) are for the MB91V301.

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Remarks

Min

Typ

Max

"H" level input
voltage

Non-hystere-
sis input pin

2.0

0.3

IHS

Hysteresis
input pin

0.8

0.3

Hysteresis input

"L" level input
voltage

Non-hystere-
sis input pin

0.8

ILS

Hysteresis
input pin

0.2

Hysteresis input

"H" level output
voltage

All output pins

3.0 V

4.0 mA

0.4

"L" level output
voltage

All output pins

3.0 V

4.0 mA

0.4

Input leak
current
(Hi-Z output
leak current)

All input pins*

3.6 V

0.45 V

Pull-up
resistance

With pins Pull-

up settings

3.6 V

0.45 V

120

Power supply
current*

17 MHz

3.6 V

110

(160)

150

(220)

When operating at :
CLKB : 68 MHz
CLKT : 68 MHz
CLKP : 34 MHz
(

4 multiplier)

CCS

17 MHz

3.6 V

(75)

(130)

When sleeping at :
CLKP : 34 MHz
in sleep mode

CCH

3.6 V

200

(300)

700

(

)

In stop mode

Input
capacitance

Except for

AVRH

AVR

MB91301/MB91V301

AC Characteristics

(1) Clock Timing Ratings

3.0 V to 3.6 V , V

0 V, Ta

C to

* : Values are for minimum clock frequency (12.5 MHz) input to X0, oscillation circuit uses PLL, and gear ratio

1/16.

Conditions for measuring the clock timing ratings

Warranted operation range

Parameter

Sym-

bol

Pin

name

Condi-

tion

Value

Unit

Remarks

Min

Max

Clock frequency (1)

X0,

12.5

MHz

Using PLL
(When operating at max in-
ternal frequency (68 MHz)

17 MHz self-oscillation with

4 PLL)

Clock cycle time

X0,

58.8

Clock frequency (2)

X0,

MHz

Self-oscillation (1/2 division
input)

Internal operation clock
frequency

0.78*

MHz

CPU

CPP

0.78*

MHz

Peripherals

CPT

0.78*

MHz

External bus

Internal operation clock
cycle time

14.7

1280*

CPU

CPP

29.4

1280*

Peripherals

CPT

14.7

1280*

External bus

0.8 V

50 pF

Output pin

(MHz)

3.6

3.0

/ f

CPP

0.78

(V)

Internal clock

Power supply

Warranted operation range (Ta

C to

CPP

is represented by the shaded area.

MB91301/MB91V301

External/internal clock setting range

fcpp

fcp, fcpt

MHz

22.7

fc
MHz

12.5

5 multiplier (CPU)

Notes :

If using the PLL, input an external clock in the range 12.5 MHz to 17 MHz.

Allow a PLL oscillation stabilization time

300

Set the gear ratio for the internal clock to be within the values shown in the "(1) Clock Timing Ratings"

table.

4 multiplier (CPU)

3 multiplier (CPU)

5 multiplier, 2 divide

(CPU, peripheral)

4 multiplier, 2 divide

(CPU, peripheral)

3 multiplier, 2 divide

(CPU, peripheral)

4 multiplier, 3 divide

(CPU, peripheral)

4 multiplier, 4 divide

(CPU, peripheral)

5 multiplier, 3 divide

(CPU, peripheral)

1/2 divide

PLL

MB91301/MB91V301

(2) Clock Output Timing

3.0 V to 3.6 V, V

0 V, Ta

C to

*1 : t

CYC

is the frequency of one clock cycle after gearing.

*2 : The following ratings are for the gear ratio set to

For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the
following equation.

Min : (1

CYC

2.35

Max : (1

CYC

2.65

*3 : The following rating are for the gear ratio set to

Min : (1

CYC

2.35

Max : (1

CYC

2.65

(3) Reset and Tool Reset Input Ratings

3.0 V to 3.6 V , V

0 V, Ta

C to

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Cycle time

CYC

SYSCLK,

MCLK

CPT

SYSCLK

CHCL

SYSCLK,

MCLK

CYC

2.35

CYC

2.65

SYSCLK

CLCH

SYSCLK,

MCLK

CYC

2.35

CYC

2.65

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Init input time (at power-on)

INTL

INIT,

TRST

Init input time
( other than at power-on)

Init input time
(recovery from stop)

1
2

SYSCLK
MCLK

VOH

VOL

VOH

CYC

CLCH

CHCL

TRST

0.2 V

INTL

INIT

MB91301/MB91V301

(4) Normal Bus Access Read/Write Operation

3.0 V to 3.6 V , V

0 V, Ta

C to

* : When the bus is delayed by automatic wait insertion or RDY input, add (t

CYC

number of wait cycles) to the rated

values.

Parameter

Sym-

bol

Pin name

Condition

Value

Unit Remarks

Min

Max

CS0 to CS7 setup

CSLCH

SYSCLK,

CS0 to CS7

CS0 to CS7 hold

CHCSH

CYC

Address setup

ASCH

SYSCLK,

A23 to A00

ASWL

WR0 to WR3,

A23 to A00

ASRL

RD, A23 to A00

Address hold

CHAX

SYSCLK,

A23 to A00

CYC

WHAX

WR0 to WR3,

A23 to A00

CYC

RHAX

RD, A23 to A00

CYC

Valid address

Valid data input time

AVDV

A23 to A00,

D31 to D00

CYC

WR0 to WR3 delay time

CHWL

SYSCLK, WR,

WR0 to WR3

WR0 to WR3 delay time

CHWH

WR0 to WR3 minimum pulse
width

WLWH

WR,

WR0 to WR3

CYC

Data setup

WRx

DSWH

WR,

WR0 to WR3,

D31 to D00

CYC

WRx

Data hold time

WHDX

RD delay time

CHRL

SYSCLK,

RD delay time

CHRH

Valid data input time

RLDV

RD,

D31 to D00

CYC

Data setup

time

DSRH

Data hold time

RHDX

RD minimum pulse width

RLRH

CYC

AS setup

ASLCH

SYSCLK,

CYC

AS hold

CHASH

UUB/ULB/LUB/LLB set up

BLCH

SYSCLK

UUB

ULB

LUB

LLB

CYC

UUB/ULB/LUB/LLB hold

CHBH

MB91301/MB91V301

(8) SDRAM Timing

3.0 V to 3.6 V , V

0 V, Ta

C to

Parameter

Symbol

Pin name

Condi-

tion

Value

Unit

Remarks

Min

Max

Output clock cycle time

CYCSD

MCLK

MHz

"H" level clock pulse width

CHSD

"L" level clock pulse width

CLSD

MCLKO

output delay

time

ODSDCKE

MCLKE

Output hold time

OHSDCKE

MCLKO

output delay

time

ODSDRAS

SRAS

Output hold time

OHSDRAS

MCLKO

output delay

time

ODSDCAS

SCAS

Output hold time

OHSDCAS

MCLKO

output delay

time

ODSDWE

SWE

Output hold time

OHSDWE

MCLKO

output delay

time

ODSDCS

CS6,

CS7

Output hold time

OHSDCS

MCLKO

output delay

time

ODSDA

A0 to A13

Output hold time

OHSDA

MCLKO

output delay

time

ODSDBA

A14,

A15

Output hold time

OHSDBA

MCLKO

output delay

time

ODSDDQM

DQMUU,

DQMUL,
DQMLU,

DQMLL

Output hold time

OHSDDQM

MCLKO

output delay

time

ODSDD

D00 to D31

Output hold time

OHSDD

Data input setup time

ISSDD

D00 to D31

Data input hold time

IHSDD

MB91301/MB91V301

(9) UART Timing

3.0 V to 3.6 V, V

0 V, Ta

C to

Notes :

These are the AC ratings for CLK synchronous mode.

CYCP

is the peripheral clock cycle time.

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Serial clock cycle time

SCYC

SCK0 to SCK2

Internal

shift clock

mode

8 t

CYCP

SCK

SO delay time

SLOV

SCK0 to SCK2,

SOT0 to SOT2

Valid SI

SCK

IVSH

SCK0 to SCK2,

SIN0 to SIN2

100

SCK

valid SIN hold time

SHIX

SCK0 to SCK2,

SIN0 to SIN2

Serial clock "H" pulse width

SHSL

SCK0 to SCK2

External

shift clock

mode

4 t

CYCP

Serial clock "L" pulse width

SLSH

SCK0 to SCK2

4 t

CYCP

SCK

SOT delay time

SLOV

SCK0 to SCK2,

SOT0 to SOT2

150

Valid SIN

SCK

IVSH

SCK0 to SCK2,

SIN0 to SIN2

SCK

valid SIN hold time

SHIX

SCK0 to SCK2,

SIN0 to SIN2

MB91301/MB91V301

(10) Reload Timer Clock and PPG Timer Input Timings

3.0 V to 3.6 V, V

0 V, Ta

C to

Note : t

CYCP

is the peripheral clock cycle time.

(11) Trigger Input Timing

3.0 V to 3.6 V, V

0 V, Ta

C to

Note : t

CYCP

is the peripheral clock cycle time.

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Remarks

Min

Max

Input pulse width

TIWH

TIWL

TIN0 to TIN2,

PPG0 to PPG3,

TRG0 to TRG3

2 t

CYCP

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Remarks

Min

Max

A/D activation trigger input time

ATGL

ATG

5 t

CYCP

TIWH

TIWL

TIN0 to TIN2
PPG0 to PPG3
TRG0 to TRG3

ATG

ATGL

MB91301/MB91V301

(12) DMA Controller Timing

3.0 V to 3.6 V, V

0 V, Ta

C to

[ For edge detection ] (Block/step transfer mode, burst transfer mode)

Note : When f

CPT

, t

CYC

becomes same as t

[ For level detection ] (Demand transfer mode)

[ For all operation modes ]

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Remarks

Min

Max

DREQ input pulse width

DRWL

DREQ 0, DREQ1

2 t

CYC

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Remarks

Min

Max

DSTP setup time

DREQS

SYSCLK,

DREQ 0, DREQ1

DSTP hold time

DREQH

SYSCLK,

DREQ 0, DREQ1

0.0

Parameter

Sym-

bol

Pin name

Condition

Value

Unit

Remarks

Min

Max

DACK delay time

CLDL

SYSCLK, DACK 0,

DACK1

CLDH

DEOP delay time

CLEL

SYSCLK, DEOP 0,

DEOP1

CLEH

IORD delay time

CLIRL

SYSCLK,

IORD

CLIRH

IOWR delay time

CLIWL

SYSCLK,

IOWR

CLIWH

MB91301/MB91V301

101

Electrical Characteristics for the A/D Converter

3.0 V to 3.6 V, V

0 V, AVRH

3.0 V to 3.6 V , Ta

C to

*1 : For V

3.0 V to 3.6 V , machine clock

34 MHz

*2 : Current when A/D converter not operating and CPU in stop mode (V

AVRH

3.6 V)

Notes :

The relative error increases as AVRH becomes smaller.

Ensure that the output impedance of the external circuit connected to the analog input meets the following

condition :

Output impedance of external circuit

7 k

If the output impedance of the external circuit is too high, the analog voltage sampling time may be too
short.

Parameter

Symbol

Pin name

Value

Unit

Min

Typ

Max

Resolution

BIT

Total error

8.5

LSB

Linearity error

3.0

LSB

Differential linearity error

2.5

LSB

Zero transition error

AN0 to AN3

8.0

0.5

8.0

LSB

Full-scale transition error

FST

AN0 to AN3

AVRH

8.0

AVRH

1.5

AVRH

8.0

LSB

Conversion time*

4.1

machine

clock (CLKP)

34 MHz at

operating

Analog port input current

AIN

AN0 to AN3

0.1

Analog input voltage

AIN

AN0 to AN3

AVss

AVRH

Reference voltage

AVRH

AVss

Power supply current

0.6

Reference voltage supply current

AVRH

0.6

Variation between channels

AN0 to AN3

LSB

MB91301/MB91V301

103

PIN STATUS IN EACH CPU STATE

Terms used in the pin status list

· Input ready

Indicates that the input function can be used.

· Input 0 fixed

Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released.

· Output Hi-Z

Indicates to put the pin in a high impedance state with the pin driving transistor disabled for driving.

· Output held

Indicates the output in the output state existing immediately before this mode is established.
If the device enters this mode with an internal output peripheral operating or while serving as an output port,
the output is performed by the internal peripheral or the port output is maintained, respectively.

· Previous state held

When the device serves for output or input immediately before entering this mode, the device maintains the
output or is ready for the input, respectively.

MB91301/MB91V301

104

Pin Status List (External bus : 32 bit bus width)

(Continued)

Pin no.

Port

name

Specified

function

name

Function

name

At initialization (INIT)

Sleep
mode

Stop mode

Bus released

(BGRNT)

Function

name

Initial

value

HIZ

=
=
=
=

HIZ

=
=
=
=

Bus width

32 bit

Bus width

8 bit

shared

CS not
shared

1 to 5

P13 to P17

D11 to D15

P13 to P17

Output Hi-Z
Input ready

P : Previous
state held
F : Output
held or Hi-Z

Output Hi-
Z/input 0
fixed

Output Hi-Z

8 to 15

P20 to P27

D16 to D23

P20 to P27

18 to 25

P30 to P37

D24 to D31

P30 to P37

P80

RDY

P80

Output Hi-Z
Input ready

P : Previous
state held
F : RDY input

Previous
state held

Output Hi-
Z/input 0
fixed

P : Previous
state held
F : RDY
input

P81

BGRNT

P81

P : Previous
state held
F : H output

L output

P82

BRQ

P82

P : Previous
state held
F : BRQ input
invalid

BRQ input

P83

H output

P : Previous
state held
F : H output

Previous
state held

Output Hi-Z

P84

DQMUU/WR0

P85

DQMUL/WR1

P85

F : H output

P86

DQMLU/WR2

P86

P87

DQMLL/WR3

P87

P90

SYSCLK

Asserted
: L output
Negated
: CLK output

P : Previous
state held
F : SYSCLK
output

P : Previous
state held
F : H or L out-
put

Output Hi-
Z/input 0
fixed

F : CLK
output

P91

MCLKE

H output

F : L output

F : Output
Hi-Z

Output Hi-Z

H output

P92

MCLK

Output Hi-Z
Input ready

P : Previous
state held
F : H output

F : Output
Hi-Z

Output Hi-Z

F : CLK
output

P93

Output Hi-Z
Input ready

Previous
state held

Output Hi-Z Output Hi-Z

Output Hi-Z

P94

SRAS/LBA/

P94

Output Hi-Z
Input ready

P : Previous
state held
F : H output

H output

Output Hi-Z Output Hi-Z

F : H output

P95

SCAS/BAA

P95

Output Hi-Z
Input ready

P : Previous
state held
F : H output

H output

Output Hi-Z Output Hi-Z

H output

P96

SWE/WRn

P96

Output Hi-Z
Input ready

P : Previous
state held
F : SWE
output

Previous
state held

Output Hi-
Z/input 0
fixed

Output Hi-Z

Previous
state held

45 to 52

P40 to P47

A00 to A07

FF output

P : Previous
state held
F : Address
output

The same as
stated left

Output Hi-
Z/input 0
fixed

Output Hi-Z

55 to 62

P50 to P57

A08 to A15

64 to 71

P60 to P67

A16 to A23

76 to 79

AN0 to AN3

input invalid

Previous
state held

input invalid

input in-
valid

Previous
state held

PG0

INT0

PG0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

P : Previous
state held
F : Input
ready

P : Output
Hi-Z
F : Input
ready

Normal
operation

PG1

INT1

PG1

PG2

INT2

PG2

PG3

INT3

PG3

PG4

INT4/ATG

PG4

PG5

INT5/SIN2

PG5

PG6

INT6/SOT2

PG6

PG7

INT7/SCK2

PG7

MB91301/MB91V301

105

(Continued)

P : General-purpose port selected, F : Specified function selected

Note : The bus width is determined after a mode vector fetch.

The bus width at initialization time is 8 bits.

Pin no.

Port

name

Specified

function

name

Function

name

At initialization (INIT)

Sleep
mode

Stop mode

Bus released

(BGRNT)

Function

name

Initial

value

HIZ

=
=
=
=

HIZ

=
=
=
=

Bus width

32 bit

Bus width

8 bit

shared

CS not
shared

PJ0

SIN0

PJ0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

Previous
state held

Output Hi-
Z/input 0
fixed

Normal
operation

PJ1

SOT0

PJ1

PJ2

SCK0

PJ2

PJ3

SIN1

PJ3

PJ4

SOT1

PJ4

PJ5

SCK1

PJ5

PJ6

PPG0

PJ6

PJ7

TRG0

PJ7

PH0

TIN0

PH0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

Previous
state held

Output Hi-
Z/input 0
fixed

Normal
operation

PH1

TIN1/PPG3

PH1

100

PH2

TIN2/TRG3

PH2

103

PB0

DREQ0

PB0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

Previous
state held

Output Hi-
Z/input 0
fixed

Normal
operation

104

PB1

DACK0

PB1

105

PB2

DEOP0

PB2

106

PB3

DREQ1

PB3

107

PB4

DACK1/TRG1

PB4

108

PB5

DEOP1/PPG1

PB5

109

PB6

IOWR

PB6

110

PB7

IORD

PB7

122

PA0

CS0

H output

Output
Hi-Z

F : SREN

0 : H output
SREN

1 :

Output Hi-Z

F : SREN

0 : H output
SREN

1 :

Output Hi-Z

123

PA1

CS1

124

PA2

CS2

125

PA3

CS3

126

PA4

CS4/TRG2

CS4

127

PA5

CS5/PPG2

CS5

128

PA6

CS6

129

PA7

CS7

132 to 139 P00 to P07

D00 to D07

Output Hi-Z
Input ready

P : Previous
state held
F : Output
held or Hi-Z

Output Hi-
Z/input 0
fixed

Output Hi-Z Output Hi-Z

142 to 144 P10 to P12

D08 to D10

MB91301/MB91V301

106

Pin Status List (External bus : 16 bit bus width)

(Continued)

Pin no.

Port

name

Specified

function

name

Function

name

At initialization (INIT)

Sleep
mode

Stop mode

Bus released

(BGRNT)

Function

name

Initial

value

HIZ

=
=
=
=

HIZ

=
=
=
=

Bus width

16 bit

Bus width

8 bit

shared

CS not
shared

1 to 5

P13 to P17

D11 to D15

P13 to P17

Output Hi-Z
Input ready

P : Previous
state held
F : Output
held or Hi-Z

Output Hi-
Z/input 0
fixed

Output Hi-Z Output Hi-Z

8 to 15

P20 to P27

D16 to D23

P20 to P27

18 to 25

P30 to P37

D24 to D31

P30 to P37

P80

RDY

P80

Output Hi-Z
Input ready

P : Previous
state held
F : RDY input

Previous
state held

Output Hi-
Z/input 0
fixed

P : Previ-
ous state
held
F : RDY
input

P81

BGRNT

P81

P : Previous
state held
F : H output

L output

P82

BRQ

P82

P : Previous
state held
F : BRQ
input invalid

BRQ input

P83

H output

P : Previous
state held
F : H output

Previous
state held

Output Hi-Z Output Hi-Z

P84

DQMUU/WR0

P85

DQMUL/WR1

P85

F : H output

P86

DQMLU/WR2

P86

P87

DQMLL/WR3

P87

P90

SYSCLK

Asserted
: L output
Negated
: CLK output

P : Previous
state held
F : SYSCLK
output

P : Previous
state held
F : H or L
output

Output Hi-
Z/input 0
fixed

F : CLK
output

P91

MCLKE

H output

F : L output

F : Output
Hi-Z

Output Hi-Z H output

P92

MCLK

Output Hi-Z
Input ready

P : Previous
state held
F : H output

F : Output
Hi-Z

Output Hi-Z

F : CLK
output

P93

Output Hi-Z
Input ready

Previous
state held

Output Hi-Z Output Hi-Z

P94

SRAS/LBA/

P94

Output Hi-Z
Input ready

P : Previous
state held
F : H output

H output

Output Hi-Z Output Hi-Z F : H output

P95

SCAS/BAA

P95

Output Hi-Z
Input ready

P : Previous
state held
F : H output

H output

Output Hi-Z Output Hi-Z H output

P96

SWE/WRn

P96

Output Hi-Z
Input ready

P : Previous
state held
F : SWE out-
put

Previous
state held

Output Hi-
Z/input 0
fixed

Output Hi-Z

Previous
state held

45 to 52

P40 to P47

A00 to A07

FF output

P : Previous
state held
F : Address
output

The same as
stated left

Output Hi-
Z/input 0
fixed

Output Hi-Z Output Hi-Z

55 to 62

P50 to P57

A08 to A15

64 to 71

P60 to P67

A16 to A23

76 to 79

AN0 to AN3

input invalid

Previous
state held

input invalid

Previous
state held

PG0

INT0

PG0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

P : Previous
state held
F : Input
ready

P : Output
Hi-Z
F : Input
ready

Normal
operation

PG1

INT1

PG1

PG2

INT2

PG2

PG3

INT3

PG3

PG4

INT4/ATG

PG4

PG5

INT5/SIN2

PG5

PG6

INT6/SOT2

PG6

PG7

INT7/SCK2

PG7

MB91301/MB91V301

107

(Continued)

P : General-purpose port selected, F : Specified function selected

Note : The bus width is determined after a mode vector fetch.

The bus width at initialization time is 8 bits.

Pin no.

Port

name

Specified

function

name

Function

name

At initialization (INIT)

Sleep
mode

Stop mode

Bus released

(BGRNT)

Function

name

Initial

value

HIZ

=
=
=
=

HIZ

=
=
=
=

Bus width

16 bit

Bus width

8 bit

shared

CS not
shared

PJ0

SIN0

PJ0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

Previous
state held

Output Hi-
Z/input 0
fixed

Normal
operation

PJ1

SOT0

PJ1

PJ2

SCK0

PJ2

PJ3

SIN1

PJ3

PJ4

SOT1

PJ4

PJ5

SCK1

PJ5

PJ6

PPG0

PJ6

PJ7

TRG0

PJ7

PH0

TIN0

PH0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

Previous
state held

Output Hi-
Z/input 0
fixed

Normal
operation

PH1

TIN1/PPG3

PH1

100

PH2

TIN2/TRG3

PH2

103

PB0

DREQ0

PB0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

Previous
state held

Output Hi-
Z/input 0
fixed

Normal
operation

104

PB1

DACK0

PB1

105

PB2

DEOP0

PB2

106

PB3

DREQ1

PB3

107

PB4

DACK1/TRG1

PB4

108

PB5

DEOP1/PPG1

PB5

109

PB6

IOWR

PB6

110

PB7

IORD

PB7

122

PA0

CS0

H output

Output Hi-Z

F : SREN

0 : H output
SREN

1 :

Output Hi-Z

F : SREN

0 : H output
SREN

1 :

Output Hi-Z

123

PA1

CS1

124

PA2

CS2

125

PA3

CS3

126

PA4

CS4/TRG2

CS4

127

PA5

CS5/PPG2

CS5

128

PA6

CS6

129

PA7

CS7

132 to 139 P00 to P07

D00 to D07

Output Hi-Z
Input ready

P : Previous
state held
F : Output
held or Hi-Z

Output Hi-
Z/input 0
fixed

Output Hi-Z Output Hi-Z

142 to 144 P10 to P12

D08 to D10

P10 to P12

MB91301/MB91V301

108

Pin Status List (External bus : 8 bit bus width)

(Continued)

Pin no.

Port

name

Specified

function

name

Function

name

At initialization (INIT)

Sleep
mode

Stop mode

Bus released

(BGRNT)

Function

name

Initial

value

HIZ

=
=
=
=

HIZ

=
=
=
=

Bus width

8 bit

Bus width

8 bit

shared

CS not
shared

1 to 5

P13 to P17

D11 to D15

P13 to P17

Output Hi-Z
Input ready

P : Previous
state held
F : Output
held or Hi-Z

Output Hi-
Z/input 0
fixed

Output Hi-Z Output Hi-Z

8 to 15

P20 to P27

D16 to D23

P20 to P27

18 to 25

P30 to P37

D24 to D31

P30 to P37

P80

RDY

P80

Output Hi-Z
Input ready

P : Previous
state held
F : RDY input

Previous
state held

Output Hi-
Z/input 0
fixed

P : Previ-
ous state
held
F : RDY
input

P81

BGRNT

P81

P : Previous
state held
F : H output

L output

P82

BRQ

P82

P : Previous
state held
F : BRQ
input invalid

BRQ input

P83

H output

P : Previous
state held
F : H output

Previous
state held

Output Hi-Z Output Hi-Z

P84

DQMUU/WR0

P85

DQMUL/WR1

P85

F : H output

P86

DQMLU/WR2

P86

P87

DQMLL/WR3

P87

P90

SYSCLK

Asserted
: L output
Negated
: CLK output

P : Previous
state held
F : SYSCLK
output

P : Previous
state held
F : H or L
output

Output Hi-
Z/input 0
fixed

F : CLK
output

P91

MCLKE

H output

F : L output

F : Output
Hi-Z

Output Hi-Z H output

P92

MCLK

P92

Output Hi-Z
Input ready

P : Previous
state held
F : H output

F : Output
Hi-Z

Output Hi-Z

F : CLK
output

P93

Output Hi-Z
Input ready

Previous
state held

Output Hi-Z Output Hi-Z

P94

SRAS/LBA/

P94

Output Hi-Z
Input ready

P : Previous
state held
F : H output

H output

Output
Hi-Z

Output Hi-Z F : H output

P95

SCAS/BAA

P95

Output Hi-Z
Input ready

P : Previous
state held
F : H output

H output

Output
Hi-Z

Output Hi-Z H output

P96

SWE/WRn

P96

Output Hi-Z
Input ready

P : Previous
state held
F : SWE out-
put

Previous
state held

Output Hi-
Z/input 0
fixed

Output Hi-Z

Previous
state held

45 to 52

P40 to P47

A00 to A07

FF output

P : Previous
state held
F : Address
output

The same as
stated left

Output Hi-
Z/input 0
fixed

Output Hi-Z Output Hi-Z

55 to 62

P50 to P57

A08 to A15

64 to 71

P60 to P67

A16 to A23

76 to 79

AN0 to AN3

input invalid

Previous
state held

input
invalid

Previous
state held

PG0

INT0

PG0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

P : Previous
state held
F : Input
ready

P : Output
Hi-Z
F : Input
ready

Normal
operation

PG1

INT1

PG1

PG2

INT2

PG2

PG3

INT3

PG3

PG4

INT4/ATG

PG4

PG5

INT5/SIN2

PG5

PG6

INT6/SOT2

PG6

PG7

INT7/SCK2

PG7

MB91301/MB91V301

109

(Continued)

P : General-purpose port selected, F : Specified function selected

Note : The bus width is determined after a mode vector fetch.

The bus width at initialization time is 8 bits.

Pin no.

Port

name

Specified

function

name

Function

name

At initialization (INIT)

Sleep
mode

Stop mode

Bus released

(BGRNT)

Function

name

Initial

value

HIZ

=
=
=
=

HIZ

=
=
=
=

Bus width

8 bit

Bus width

8 bit

shared

CS not
shared

PJ0

SIN0

PJ0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

Previous
state held

Output Hi-
Z/input 0
fixed

Normal
operation

PJ1

SOT0

PJ1

PJ2

SCK0

PJ2

PJ3

SIN1

PJ3

PJ4

SOT1

PJ4

PJ5

SCK1

PJ5

PJ6

PPG0

PJ6

PJ7

TRG0

PJ7

PH0

TIN0

PH0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

Previous
state held

Output Hi-
Z/input 0
fixed

Normal
operation

PH1

TIN1/PPG3

PH1

100

PH2

TIN2/TRG3

PH2

103

PB0

DREQ0

PB0

Output Hi-Z
Input ready

P : Previous
state held
F : Normal
operation

Previous
state held

Output Hi-
Z/input 0
fixed

Normal
operation

104

PB1

DACK0

PB1

105

PB2

DEOP0

PB2

106

PB3

DREQ1

PB3

107

PB4

DACK1/TRG1

PB4

108

PB5

DEOP1/PPG1

PB5

109

PB6

IOWR

PB6

110

PB7

IORD

PB7

122

PA0

CS0

H output

Output Hi-Z

F : SREN

0 : H output
SREN

1 :

Output Hi-Z

F : SREN

0 : H output
SREN

1 :

Output Hi-Z

123

PA1

CS1

124

PA2

CS2

125

PA3

CS3

126

PA4

CS4/TRG2

CS4

127

PA5

CS5/PPG2

CS5

128

PA6

CS6

129

PA7

CS7

132 to 139 P00 to P07

D00 to D07

Output Hi-Z
Input ready

P : Previous
state held
F : Output
held or Hi-Z

Output Hi-
Z/input 0
fixed

Output Hi-Z Output Hi-Z

142 to 144 P10 to P12

D08 to D10

P10 to P12

MB91301/MB91V301

110

EXAMPLE CHARACTERISTICS

ICC

Internal frequency (PLL On)

External VCC

3.6 V, Temp

ICC

Exteranal VCC (PLL On)

Internal frequency

68 MHz, Temp

Internal frequency [MHz]

External VCC [V]

VOL

External VCC

Internal frequency

68 MHz, Temp

VOH

External VCC

Internal frequency

68 MHz, Temp

External VCC [V]

IIL

External VCC

Internal frequency

68 MHz, Temp

External VCC [V]

140

120

100

ICC
ICCS

ICC [mA]

140

120

100

2.7

3.3

3.6

3.9

ICC
ICCS

ICC [mA]

0.8

0.6

0.4

0.2

2.7

3.3

3.6

3.9

VOL [V]

2.7

3.3

3.6

3.9

VOH [V]

100

200

300

400

2.7

3.3

3.6

3.9

IIL [

MB91301/MB91V301

112

PACKAGE DIMENSIONS

144-pin Plastic LQFP

(FPT-144P-M12)

Note 1) * : These dimensions include resin protrusion.

Resin protrusion is

0.25 (.010) Max (each side) .

Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.

Dimensions in mm (inches)

179-pin Ceramic PGA

(PGA-179C-A03)

Dimensions in mm (inches)

2003 FUJITSU LIMITED F144024S-c-3-3

.059

.004

+.008

0.10

+0.20

1.50

Details of "A" part

0~8

(Mounting height)

0.60±0.15

(.024±.006)

0.25(.010)

(.004±.002)

0.10±0.05

(Stand off)

0.08(.003)

0.145

0.03

+.002
.001

.006

+0.05

"A"

.007±.001

0.18±0.035

0.07(.003)

LEAD No.

0.40(.016)

INDEX

144

109

108

18.00±0.20(.709±.008)SQ

16.00

.630

.004

+.016

0.10

+0.40

1994 FUJITSU LIMITED R179004SC-3-2

INDEX AREA

6.10(.240)

MAX

1.27±0.25

.018

.002

+.007

0.05

+0.18

0.46

.134

.014

+.016

0.36

+0.41

3.40

1.27(.050)TYP DIA

35.56(1.400)

REF

INDEX

DIA

38.10±0.51

(1.500±.020)

(.050±.010)

2.54±0.25

(.100±.010)

MB91301/MB91V301

FUJITSU LIMITED

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party's
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0302

FUJITSU LIMITED Printed in Japan

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91V301

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91V301