OVERVIEW
GA3220 is a system-in-a-package (SiP)
signal processing platform specifically
designed for hearing instruments which
require high precision processing and ultra
low power consumption. The platform
delivers high-performance audio
processing with superior power efficiency
enabling the implementation of advanced
hearing instrument algorithms such as next generation adaptive noise
reduction and environmental classification algorithms.
The GA3220 platform is comprised of three chips as illustrated in Figure1.
The GC5002 DSP chip contains both programmable instruction set DSP
cores and high performance hard-
wired co-processors. It provides
extensive computational capability
without compromising battery life.
The unique architecture of the
GC5002 simultaneously offers the
flexibility of a programmable
platform and the performance of
hard-wired design. The chip utilizes
a distributed and re-configurable
architecture which enables
hardware scalability and ensures
minimum power consumption while implementing advanced signal
processing algorithms.
The second chip, GC5055, is a programmable high fidelity audio Codec
designed specifically for digital hearing instrument applications. This chip
provides industry-standard interfaces for transducers, switches, volume
controls and programmer boxes. It also provides serial communication
ports for interfacing with third-party DSP chips and serial EEPROMs.
The GA3220 platform employs ThinSTAXTM advanced packaging
technology which makes it incredibly compact and suitable for CIC
instruments.
BENEFITS
The most versatile SiP platform - fits into
any shell size from CIC to BTE
Single programmable platform enables
product implementation for different
market segments
Reduced product development and
manufacturing costs for OEMs through
product consolidation
Improved time-to-market and fast
response to changing market needs
Re-configurable and distributed
processing architecture allows easy
product enhancements and provides full
computational power scalability
Flexible architecture enables easy
integration of a third party IP-block
(e.g., proprietary feedback cancellation
or directional processing to the system)
Hearing instrument-centric instruction
set based DSP allows OEMs to
implement any proprietary algorithms
and provide extensive processing power
to support any leading-edge algorithm
0.13u silicon technology facilitates high-
end product implementation without
sacrificing good battery life
State of the art analog chip design and
high precision digital processing
ensures the highest sound quality
Fully integrated development
environment (GUIDE) provides fast and
easy development
continued on other side
Figure 1
GA3220
TM
GA3220
Programmable Signal Processing Platform for Hearing Instruments
h i p i n f o @ g e n n u m . c o m w w w . g e n n u m . c o m
tel: +1 (905) 632-2996 fax: +1 (905) 632-2814
FEATURES
CIC size package (hybrid size < 215x124x69 mil)
Ultra low power architecture
256K SPI EEPROM system memory
Complete integrated development kit (GUIDE) supports
development from concept to final product
Programmable and re-configurable GC5002 DSP chip
- Leading edge 0.13
technology
- As low as 0.04mW/MMAC average power consumption
for the programmable blocks (
DSP and filter engines)
- 42MIPS processing power at 2MHz
- A programmable main DSP for system configuration and
control
- Four programmable, dual-MAC
DSPs for numerically
intensive operations
- Four custom programmable filter engines optimized for
digital filtering operations
SYSTEM OVERVIEW
MDSP
(controller)
Pre-
Processing
Block
Post-
Processing
Block
MUX
ADC
ADC
DAC
EEPROM
Interfaces
I2S
SPI
PCM
Debug
SDA
GPIO
Time Domain
Cluster
Frequency Domain
Cluster
Input
Cluster
Output
Cluster
DSP
TDFB
DSP
FFT/IFFT
DSP
Feng
DSP
Feng
FBC
Feng
Feng
OCL
- Task specific hardware accelerators for
common audio processing tasks (FFT/IFFT,
Feedback Canceller, OCL and Time Domain
Filter Bank )
- 10.7K words of data RAM and 7.7K words of
program RAM.
- Programmable on-chip clock frequency
between 2MHz and 10MHz.
- 20 bit audio precision
- Power saving sleep modes
- General Purpose I/O port for application
development or custom applications
- debug port supports in-circuit emulation (ICE)
Hi-Fidelity GC5055 CODEC Chip
- 0.18u technology
- Dual A/Ds, D/A
- 95 dB input dynamic range
- 83 dB output dynamic range
- Programmable sampling between 8-48kHz
- FRONTWAVETM Directional processing
- Four analog inputs (Fmic, Rmic, Tcoil, Direct
Audio Input-DAI)
- Internal/External Volume control
- AGC-O and tone generation
- Drives zero-bias 2-terminal receivers
FEATURES continued
2004 Gennum Corporation. Printed in Canada
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