GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com

www.gennum.com

Revision Date: April 2002

Document No. 521 - 33 - 05

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DATA SHEET

FEATURES

· 4:2:2 to over-sampled RGB or YC

conversion in a

single device

· single 10 bit 4:2:2 input

· internal 4:2:2 de-multiplexer

· 4:2:2 to 8:8:8 interpolation filters

· internal YC

CR to RG

color space conversion

· optional YC

(8:8:8) output mode

· setup insertion in Luminance channel under user

control

· user selectable digital SIN X/X correction

· rounding to 10/8 bit resolution per output channel

· 40 MHz maximum clock rate

· single +5 V power supply

APPLICATIONS

· Over-Sampling 4:2:2 to Analog RGB Conversions for

video monitoring

· Over-Sampling 4:2:2 to Analog YCBCR Conversions for

video monitoring

DEVICE DESCRIPTION

The GF9103 is specifically designed to simplify conversions
from 4:2:2 component digital video to analog RGB or
analog YC

component video. The GF9103 simplifies

this process by performing 4:2:2 to 8:8:8 interpolation,
digital color space conversion and digital SIN X/X
correction in a single device. Immediately following the
GF9103, three over-sampled channels of RGB or YC

data may be passed through Digital to Analog converters
and simplified analog reconstruction filters.

The GF9103 accepts a single 10 bit stream of 4:2:2 data
and internally de-multiplexes it into three 10 bit channels of
YC

data. The YC

data is then passed through

three linear phase FIR filters that over-sample the Y data by
a factor of 2 and the C

and C

data by a factor of 4.

While operating in an over-sampled RGB output mode, the
interpolated YC

data is passed through the internal

color space converter to convert the YC

data to RGB

data according to CCIR-601. Alternatively, the color space
converter may be bypassed to obtain over-sampled YC

(8:8:8) output data. While operating in YC

output mode,

setup may be dynamically inserted into the Luminance
channel.

Prior to output rounding, over-sampled YC

or RGB data

may be corrected for SIN X/X characteristics of D/A
conversion. Output data may be rounded to 10 or 8 bit
resolution per channel. C

and C

may be presented as

signed or unsigned data.

The GF9103 is packaged in a 68 pin PLCC package,
operates with a single +5 V power supply and typically
consumes only 85 mA of current when operated at 27 MHz.

FUNCTIONAL BLOCK DIAGRAM

ORDERING INFORMATION

PART NUMBER

PACKAGE

TEMPERATURE RANGE

GF9103-CPS

68 pin PLCC

0° to 70° C

GF9103-CTS

68 pin PLCC Tape

0° to 70° C

CLIP & ROUND

SELECT_MATRIX

SETUP

SIN X/X

MULTIPLEXED

4:2:2 DATA
STREAM IN

YCBCR

RGB

MATRIX

BYPASS

4:2:2

DEMUX

SYNC

CLK

Y/G

CR/R

CB/B

Y/G

CB/B

CR/R

Y/G

CB/B

CR/R

Y/G

CB/B

CR/R

CB/B

CR/R

2's COMP

CONVERT

2's COMP

0XOWLGEN

GF9103 Over-Sampling

Color Space Converter for

Video Monitoring

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PIN DESCRIPTION

PIN NO.

SYMBOL

DESCRIPTION

10, 18, 27, 36, 44, 52,
61, 68

±5 V ± 5% power supply.

1, 6, 7, 9, 26, 30, 35,
40, 43, 60, 64

GND

Ground.

SCAN_EN

Set Low.

8, 11-17, 19, 20

9..0

Input Data Port: Input data port with internal pull-downs. Input data is assumed to be a
multiplexed stream of C

[Y] C

..., where [Y] denotes an isolated Luminance sample.

is the Most Significant Bit and SI

is the Least Significant Bit.

Output Enable: Active low input with internal pull-up. When OE is high, the output data ports
are in high impedance state.

59-53, 51-49

SOA

9..0

Output Data Port A: Depending on device configuration, SOA

9..0

may output over-sampled

Y or G video. SOA

is the Most Significant Bit and SOA

is the Least Significant Bit.

48-45, 42, 41, 39-37,
34

SOB

9..0

Output Data Port B: Depending on device configuration, SOB

9..0

may output over-sampled

or B video. SOB

is the Most Significant Bit and SOB

is the Least Significant Bit.

33-31, 29, 28, 25-21

SOC

9..0

Output Data Port C: Depending on device configuration, SOC

9..0

may output over-sampled

or R video. SOC

is the Most Significant Bit and SOC

is the Least Significant Bit.

CLK

System Clock: All timing information relative to rising edge of clock.

SYNC

Synchronization: Control signal input with internal pull-up. This input is used to synchronize
the incoming data by holding SYNC high on clock period N and low on clock period N+1
when the first C

sample is presented to the SI

9..0

inputs. SYNC may be held low until re-

synchronization is desired or may be toggled at every occurrence of a C

sample.

SELECT_MATRIX

Select Color Space Conversion: Control signal input with internal pull-down.
SELECT_MATRIX is used to enable and disable the internal YC

to RGB color space

converter. Color space conversion is enabled while SELECT_MATRIX is high and is
disabled while SELECT_MATRIX is low.

BYPASS

Bypass SIN X/X Correction: Control signal input with internal pull-up. When BYPASS is
high, SIN X/X correction for the three output channels is enabled. While BYPASS is low, SIN
X/X correction is by-passed.

SETUP

Setup: Control signal input with internal pull-down. SETUP is used to enable and disable
setup insertion in the Luminance channel.

CONVERT

Two's Complement Conversion: Control signal input with internal pull-up. While CONVERT

is high, SOB

9..0

and SOC

9..0

output signed (two's complement) digital data. While

CONVERT is low, SOB

9..0

and SOC

9..0

output unsigned (offset binary) data. When

operating in RGB output mode, the CONVERT pin is over-ridden and both SOB

9..0

and

SOC

9..0

output unsigned digital data. SOA

9..0

outputs unsigned digital data in all operating

modes.

RND10/8

Output Rounding: Control signal input with internal pull-up. RND10/8 selects rounding to
10 bit resolution per channel when high and rounding to 8 bit resolution per channel when
low.

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DEVICE DESCRIPTION

The GF9103 is composed of five main sections:

1. 4:2:2 De-Multiplexer

2. FIR Filtering and Setup Insertion

3. Color Space Conversion

4. Digital SIN X/X Correction

5. Output Processing

4:2:2 DE-MULTIPLEXER

The de-multiplexer accepts data multiplexed in a SMPTE
125M compliant format from the

SI9..0

input data port.

SI9

the Most Significant Bit and

SI0

is the Least Significant Bit.

The input data stream is assumed to be a multiplexed
stream of C

Y C

[Y] C

..., where the three words C

Y C

refer to cosited samples and where [Y] refers to an isolated
Luminance sample. When operating the GF9103 with 8 bit
input data,

SI9..2

should be used to present data to the

device and

SI1..0

should be set low.

At least once during a power cycle, the GF9103 must be
synchronized to the incoming data stream. The GF9103 is
synchronized by holding SYNC high on clock period N and
low on clock period N+1 when the first C

sample is

presented to the

SI9..0

inputs. SYNC may be held low until

re-synchronization is desired, or it may be toggled at every
occurrence of a C

sample. Refer to the timing diagram in

Figure 9 for required operation of the SYNC control signal.

The internal de-multiplexer will de-multiplex all data in the
input data stream including any ancillary, EDH,VITC, and
EAV/SAV ... signals that may be present. Since this data is
passed directly to the interpolation filters in the same way
that active video would be, it is recommended that such
data be replaced with appropriate blanking levels prior to
entering the GF9103.

The output of the 4:2:2 de-multiplexer consists of three 10
bit channels of YC

data. All three channels are then fed

to their respective interpolation filter.

INTERPOLATION FILTERS

Within the interpolation stage, the Luminance data is over-
sampled by a factor of two and the C

and C

data is over-

sampled by a factor of four so that the 4:2:2 data is
converted to 8:8:8 data. By over-sampling the 4:2:2 data to
8:8:8 data, the size, cost and complexity of the analog
reconstruction filters following Digital to Analog converters
are reduced.

The Luminance data is over-sampled by a linear phase FIR
filter providing 0.0 dB DC gain, +0.038/-0.025 pass- band
ripple [0.0 s to 0.21 s], 6 dB attenuation at s/4, and 47
dB stopband attenuation [0.30 s to 0.50 s]. Figure 3 and
Figure 4 present the frequency response of the Luminance
interpolation filter.

The C

and C

data is over-sampled by a linear phase FIR

filter providing 0.0 dB DC gain, passband ripple of +0.2 dB/-
0.2 dB [0.0 to 0.07 s], 6 dB attenuation at s/8 and a
stopband attenuation of 28 dB [ 0.17s to 0.50 s].

Figure 5 and Figure 6 present the frequency response of the
C

and C

interpolation filters.

Following the interpolation process, a DC offset may be
introduced into the Luminance channel. Setup insertion is
enabled and disabled by the SETUP control signal. While
SETUP is high, the Luminance data is scaled by a factor of
+947/1024 and an offset of +71 (decimal) is added. While
SETUP is low, no scaling or offset is applied and the data
passes through the stage unmodified. The timing diagram
in Figure 10 demonstrates the operation of the SETUP
control signal.

COLOR SPACE CONVERSION

Two operating modes exist for the color space converter
section. These two modes are controlled by the
SELECT_MATRIX control signal. While SELECT_MATRIX is
low, the de-matrixing 3 x 3 multiplier is bypassed so that
over-sampled Y C

data is passed through the stage

unmodified. While SELECT_MATRIX is high, the 3 x 3
multiplier implements the following color space conversion:

SIN X/X CORRECTION

While BYPASS is high, SIN X/X correction is enabled on
each of the three output channels. SIN X/X correction is
implemented by passing the data through a FIR filter with
the frequency response shown in Figure 7. While BYPASS is
low, the FIR filter is bypassed and each channel is passed
directly to the output processing section. Total latency
through the device is 22 clock cycles when BYPASS is low
and 24 clock cycles when BYPASS is high.

OUTPUT PROCESSING

Output data may be rounded to 10 or 8 bit accuracy.
RND10/8

should be set high for 10 bit output rounding and

set low for 8 bit output rounding. Rounding to 8 bit accuracy
is accomplished by adding a rounding bit to SO

and then

zeroing both SO

and SO

and C

data may be output as signed (two's

complement) or unsigned (offset binary) data depending on
the state of the CONVERT control signal. When CONVERT
is set high, the C

and C

channels are output as signed

(two's complement) data. When CONVERT is set low, C

and C

are output as unsigned (offset binary) data,

obtained by inverting the sign bit of the two's complement
number. When operating in RGB output mode, the
CONVERT pin is over-ridden and RGB data is always
output as unsigned (offset binary) data.

-689/2048

-1430/2048

3548/2048

2807/2048

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CONTROL SIGNAL/OPERATING MODE SUMMARY

SYNC

The SYNC control signal provides synchronization for the internal 4:2:2 de-multiplexer. SYNC should be held high on clock
period N and low on clock period N+1 when the first C

sample is presented to the SI

9..0

inputs. SYNC may be held low until

re-synchronization is desired or may be toggled at every occurrence of a C

sample.

SELECT_MATRIX AND SETUP

SELECT_MATRIX and SETUP select the color space conversion and offset insertions which the GF9103 is to perform. The
following chart presents the available color space conversions and the corresponding states of the SELECT_MATRIX and
SETUP control pins. SETUP is a dynamic pin that may be modified every clock cycle.

SELECT_MATRIX

SETUP

DESCRIPTION

Selects output to be over-sampled YC

with no setup in Y channel.

Selects output to be over-sampled YC

with a scaling factor of

+947/1024 and an offset of +71 (decimal) applied to the Y channel.

Selects output to be over-sampled RGB with no setup.

SIN X/X CORRECTION

BYPASS

DESCRIPTION

SIN X/X correction enabled on all output data channels. Latency through the device is 24 clock cycles.

SIN X/X correction disabled. Latency through the device is 22 clock cycles.

OUTPUT ROUNDING

RND10/8

DESCRIPTION

Output data rounded to 10 bit resolution per channel.

Output data rounded to 8 bit resolution per channel.

TWO'S COMPLEMENT OUTPUT CONVERSION

CONVERT

SELECT_MATRIX

DESCRIPTION

SOB

9..0

and SOC

9..0

output signed (two's complement) C

and C

data.

SOB

9..0

and SOC

9..0

output unsigned (offset binary) C

and C

data.

SOB

9..0

and SOC

9..0

output unsigned B and R data.

OUTPUT ENABLE

DESCRIPTION

All output data ports are enabled.

All output data ports are in high impedance state.

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