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GF9330 High Performance
HDTV/SDTV Deinterlacer
GF9330 Data Sheet
1 of 42
Proprietary and Confidential
18283 - 4
June 2004
Features
10/8-bit progressive scan output up to 1080p60
support for multiplexed and non-mutiplexed Y/C video
multi-directional edge detection processing
adaptive inter-field motion detection
seamless interface to Gennum's GF9331 motion co-
processor
fully configurable to support custom video modes
3:2 film mode operation for HDTV/SDTV inputs
programmable noise reduction and detail enhancement
de-interlace, pass-through and film rate down conversion
modes of operation
seamless interface to popular ADCs and NTSC/PAL
decoders
ability to extract HVF information from embedded TRS
selectable rounding and clipping of output data
selectable blanking of active video lines
HVF output signals with programmable output video
cropping
serial/parallel host interface
3.3V supply for device I/O and 2.5V for core logic
5V tolerant inputs
Applications
HDTV Up/Down Converters
Production Equipment
Video Walls
Projection Systems
Plasma Displays
LCD TVs
Home Theatre Systems
HD DVD Players
Device Overview
The GF9330 is a 10-bit high performance VDSP engine that
performs high quality motion adaptive de-interlacing of
interlaced digital video signals. The GF9330 supports
standard definition (SDTV) and high definition (HDTV) signal
formats and clock rates up to 1080p60 with support for
arbitrary display modes.
The GF9330 uses multi-directional adaptive filters for edge
processing, an adaptive vertical motion filter and an adaptive
inter-field motion filter. The GF9330 features detail
enhancement and noise reduction capabilities. The GF9330
also supports 3:2 pull-down, static/freeze-frame detection and
compensation and film rate conversions. The GF9330 may
operate as a stand-alone de-interlacer or may be used with
the GF9331 Motion Co-processor to enable higher quality HD/
SD de-interlacing with edge and vertical motion detection. The
two devices can be configured in tandem such that the
GF9331 sends edge detection and vertical motion filter control
information to the GF9330. These control signals adaptively
switch the GF9330's internal filters on a pixel-by-pixel basis.
The GF9330 integrates all required line delays and
seamlessly interfaces to off chip SDRAMs that form the
required field delays. The device may also operate in by-pass
mode should no processing of the input signal be desired.
Ordering Information
Block Diagram
Part Number
Package
Temp. Range
GF9330-CBP
328 PIN BGA
0
o
C to 70
o
C
Noise
Reducer
Detail
Enhancer
3:2
Pulldown
Detector
Inter-field
Motion
Detector
Edge Adaptive
Interpolator
Vertical Motion
Adaptive Interpolator
Inter-field Motion
Adaptive Interpolator
Field Merging
Selector
Output
Processing
Host
Interface
Timing
Generator
External Memory Interface
Input
Processing
Control bus from GF9331
Processed Y/C
Y/C
GF9330 Data Sheet
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Proprietary and Confidential
18283 - 4
June 2004
Contents
Contents .......................................................................................................................2
1. Pin Descriptions ........................................................................................................3
2. Electrical Characteristics...........................................................................................8
2.1 5V Tolerant Inputs ...........................................................................................8
2.2 ESD Tolerance ................................................................................................8
2.3 3.3V Supply for Device I/0 and 2.5V for Core Logic .......................................8
3. Detailed Device Description ....................................................................................12
3.1 Supported Input Video Formats ....................................................................12
3.2 Input Synchronization ...................................................................................14
3.3 Seamless Interface to the GF9331 Motion Co-processor for Directional
Filter Control .................................................................................................17
3.4 Seamless Interface to External SDRAMs .....................................................18
3.5 Host Interface ................................................................................................18
3.6 Closed Caption Blanking ...............................................................................30
3.7 Programmable Noise Reduction and Detail Enhancement ...........................30
3.8 RESET ..........................................................................................................31
3.9 Modes of Operation ......................................................................................31
3.10 Output Data Formats ..................................................................................33
3.11 Sequence Detection ....................................................................................37
4. Package Dimensions ..............................................................................................41
Revision History .........................................................................................................42
GF9330 Data Sheet
3 of 42
Proprietary and Confidential
18283 - 4
June 2004
1. Pin Descriptions
Figure 1-1: Top View Pin Out 328 BGA
A
B
C
D
J
K
E
F
G
H
L
M
N
P
W
Y
R
T
U
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RESET
Y_IN9
S2_DAT0
S2_DAT1
Y_IN8
Y_IN5
Y_IN7
Y_IN4
S2_DAT2
S2_DAT3
S2_DAT4
S2_DAT5
Y_IN6
Y_IN3
S2_DAT6
S2_DAT7
S2_DAT8
S2_DAT9
S2_DAT12
S2_DAT13
S2_DAT10
S2_DAT11
S2_DAT14
S2_DAT15
S2_DAT16
S2_DAT17
S2_DAT20
S2_DAT21
S2_DAT18
S2_DAT19
S2_DAT22
S2_DAT23
S2_DAT25
S2_DAT26
S2_DAT29
S2_DAT30
S2_DAT27
S2_DAT28
S2_DAT31
S2_DAT32
S2_DAT36
S2_DAT35
S2_CLK
S2_DAT39
S2_DAT34
S2_DAT33
S2_DAT38
S2_DAT37
S2_DAT44
S2_DAT43
S2_ADDR0
S2_DAT47
S2_DAT42
S2_DAT41
S2_DAT46
S2_DAT45
S2_ADDR4
S2_ADDR3
S2_ADDR8
S2_ADDR7
S2_ADDR2
S2_ADDR1
S2_ADDR6
S2_ADDR5
S2_ADDR12
S2_ADDR11
S2_CS
S2_CAS
S2_ADDR10
S2_ADDR9
S2_ADDR13
Y1_OUT11
S2_WE
S2_RAS
VCLK_OUT
LOCK_32
XSEQ1
XSEQ3
XSEQ0
XSEQ2
Y_IN2
VCLK_IN
Y_IN1
MODE2
SER_MD
MEMCLK_IN
STD4
STD1
Y_IN0
MODE1
HOST_EN
MODE0
STD3
STD0
STD2
XVOCLK_SL
GND
VDD_CLKD
VDD_INT
VDD_INT
VSS_CLKD
GND
VDD_INT
GND
VDD_IO
VDD_IO
S2_DAT24
GND
VDD_IO
GND
VDD_INT
S2_DAT40
GND
GND
VDD_IO
VDD_IO
GND
VDD_INT
GND
VDD_INT
GND
NC
Y1_OUT4
Y1_OUT5
Y1_OUT0
Y2_OUT8
Y1_OUT1
Y2_OUT9
Y1_OUT9
Y1_OUT6
Y1_OUT10
Y1_OUT7
Y1_OUT2
Y2_OUT10
Y1_OUT3
Y2_OUT11
XVOCLK_IN
C_IN7
LOCK_22
C_IN6
C_IN0
FIL_SEL0
C_IN1
FIL_SEL1
C_IN9
C_IN5
C_IN8
C_IN4
C_IN2
FIL_SEL2
C_IN3
FIL_SEL3
VDD_IO
GND
VDD_INT
GND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
TGND
VDD_IO
GND
GND
VDD_IO
Y2_OUT4
NC
Y2_OUT5
Y2_OUT1
NC
C1_OUT9
Y2_OUT0
C1_OUT8
Y2_OUT6
Y2_OUT2
Y2_OUT7
Y2_OUT3
C1_OUT11
C1_OUT7
C1_OUT10
C1_OUT6
FVH_EN
A_D
F_IN
CS
DAT_IO4
DAT_IO0
DAT_IO5
DAT_IO1
V_IN
R_W
H_IN
FF_EN
DAT_IO6
DAT_IO2
DAT_IO7
DAT_IO3
VDD_IO
GND
GND
NC
GND
VDD_INT
VDD_INT
VDD_IO
VDD_IO
S1_DAT41
GND
VDD_IO
GND
VDD_INT
S1_DAT25
GND
GND
GND
VDD_INT
VDD_IO
VDD_IO
VDD_INT
GND
C1_OUT5
C1_OUT1
C1_OUT4
C1_OUT0
C2_OUT9
NC
C2_OUT8
C2_OUT5
C1_OUT3
C2_OUT11
C1_OUT2
C2_OUT10
C2_OUT7
C2_OUT4
C2_OUT6
C2_OUT3
TDI
TCLK
TMS
GND
GND
S1_RAS
S1_WE
S1_ADDR13
GND
GND
GND
S1_ADDR10
S1_CAS
S1_CS
S1_ADDR11
S1_ADDR12
S1_ADDR6
S1_ADDR7
S1_ADDR2
S1_ADDR3
S1_ADDR8
S1_ADDR9
S1_ADDR4
S1_ADDR5
S1_DAT46
S1_DAT47
S1_DAT42
S1_DAT43
S1_ADDR0
S1_ADDR1
S1_DAT44
S1_DAT45
S1_DAT37
S1_DAT38
S1_DAT34
S1_DAT35
S1_DAT39
S1_DAT40
S1_DAT36
S1_CLK
S1_DAT33
S1_DAT32
S1_DAT29
S1_DAT28
S1_DAT31
S1_DAT30
S1_DAT27
S1_DAT26
S1_DAT24
S1_DAT23
S1_DAT20
S1_DAT19
S1_DAT22
S1_DAT21
S1_DAT18
S1_DAT17
S1_DAT16
S1_DAT15
S1_DAT12
S1_DAT11
S1_DAT14
S1_DAT13
S1_DAT10
S1_DAT9
S1_DAT8
S1_DAT7
C2_OUT2
S1_DAT4
S1_DAT6
S1_DAT5
S1_DAT3
S1_DAT2
C2_OUT1
F_OUT
C2_OUT0
H_OUT
S1_DAT1
S1_DAT0
V_OUT
TDO
Y1_OUT8
TOP VIEW
GF9330 PIN OUT
328 BGA
VDD_IO: +3.3V
VDD_INT: +2.5V
GND/TGND: 0V
NC: No Connection
GF9330 Data Sheet
4 of 42
Proprietary and Confidential
18283 - 4
June 2004
Table 1-1: Pin Descriptions
Symbol
Pin Grid
Type
Description
RESET
A1
I
Active low, asynchronous RESET. Resets all internal logic to default
conditions. Should be applied on power up.
VCLK_IN
F1
I
Video input clock. When the input is SDTV the input clock will be 27, 36, 54 or
72MHz. When the input format is HDTV, the input clock will be 74.25 or 74.25/
1.001MHz.
MEMCLK_IN
H1
I
Memory clock for SDRAM operation to support HD modes, 90MHz input
(supplied by an off-chip crystal oscillator).
XVOCLK_IN
J1
I
External video output clock. This input may be used instead of the internal
VCLK_IN clock doubler to supply the video output clock VCLK_OUT.
XVOCLK_SL
H4
I
Control signal input. When HIGH, selects XVOCLK_IN; when LOW, selects
the internal VCLK_IN clock doubler for generation of the video output
VCLK_OUT signal.
Y_IN[9:0]
B1, C1, C2, C3, D1, D2,
D3, E1, E2, E3
I
10/8-bit input bus for separate luminance or multiplexed luminance and colour
difference video data. When supplying 8-bit data to the GF9330, Y_IN[1:0] will
be set LOW and the 8-bit data supplied to Y_IN[9:2].
C_IN[9:0]
J3, J4, K1, K2, K3, K4, L4,
L3, L2, L1
I
10/8-bit input bus for colour difference for video data. When supplying 8-bit
data to the GF9330, C_IN[1:0] will be set LOW and the 8-bit data supplied to
C_IN[9:2].
FIL_SEL[3:0]
M4, M3, M2, M1
I
Filter selection control bus. FIL_SEL[3:0] are used to switch the GF9330's
internal directional filters on a pixel by pixel basis. FIL_SEL[3:0] is supplied by
the GF9331.
F_IN
N2
I
Video timing control. F_IN identifies the ODD and EVEN fields in the incoming
video signal. F_IN will be LOW in Field 1 and HIGH in Field 2.
V_IN
N3
I
Video timing control. V_IN represents the vertical blanking signal associated
with the incoming video signal. V_IN is HIGH during the vertical blanking
interval and LOW during active video.
H_IN
N4
I
Video timing control. H_IN represents the horizontal blanking signal
associated with the incoming video signal. H_IN is HIGH during horizontal
blanking and LOW during active video.
FVH_EN
N1
I
Control signal input. When HIGH, the F_IN, V_IN, and H_IN input pins will be
used for video data signalling. When LOW, embedded TRS's will be detected
for video data timing.
FF_EN
P4
I
Control signal input. When HIGH, FF_EN enables the GF9330's internal
freeze frame compensation. See
3.11.4 Static and Freeze Frame Detection/
Compensation
.
LOCK_22
J2
I
Control signal input. For 2:2 pull-down compensation, the LOCK_22 pin will be
used to identify the presence of a 2:2 sequence in the input video stream.
STD[4:0]
G2, G3, G4, H2, H3
I
Video format definition. Defines the video standard when operating without the
host interface. See
Table 3-1: Encoding of STD[4:0] for Selecting Input Data
Format
.
MODE[2:0]
F2, F3, F4
I
Operating mode selection. Defines the mode of operation when operating
without the host interface. See
3.9 Modes of Operation
.
GF9330 Data Sheet
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Proprietary and Confidential
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June 2004
HOST_EN
E4
I
Host interface enable. When set HIGH, the GF9330 will be configured through
the host interface. On a high to low transition of HOST_EN the GF9330 will
replace all register settings in the host interface with the values present on the
external pins of the device including: STD[4:0], MODE[2:0], FVH_EN, FF_EN
and XVOCLK_SL.
SER_MD
G1
I
Host interface mode selection. Enables serial mode operation when HIGH.
Enables parallel mode operation when LOW.
CS
P2
I
Functions as an active low chip select input for host interface parallel mode
operation. Functions as a serial clock input for host interface serial mode
operation.
DAT_IO[7:0]
R4, R3, R2, R1, T4, T3,
T2, T1
I/O
Host interface bi-directional data bus for parallel mode. In serial mode, DAT[7]
serves as the serial data output pin and DAT[0] serves as the serial data input
pin.
R_W
P3
I
Host interface Read/Write control for parallel mode. A read cycle is defined
when HIGH, a write cycle is defined when LOW.
A_D
P1
I
Host interface Address/Data control for parallel mode. The data bus contains
an address when HIGH, a data word when LOW. In serial mode, this pin
serves as the chip select (active low).
VCLK_OUT
A20
O
Video output clock. Output frequency based on selected output standard. See
3.9 Modes of Operation
.
Y1_OUT[11:0]
D18, E20, E19, E18, F20,
F19, F18, F17, G20, G19,
G18, G17
O
Output data bus for separate luminance or multiplexed luminance and colour
difference video data. See
3.10.2 12-bits Output Resolution
.
Y2_OUT[11:0]
H20, H19, H18, H17, J20,
J19, J18, J17, K20, K19,
K18, L18
O
Output data bus for luminance video data during dual pixel mode operation.
See
3.10.2 12-bits Output Resolution
.
C1_OUT[11:0]
L19, L20, M17, M18, M19,
M20, N17, N18, N19, N20,
P17, P18
O
Output data bus for colour difference video data.
See
3.10.2 12-bits Output Resolution
.
C2_OUT[11:0]
P19, P20, R17, R18, R19,
R20, T18, T19, T20, U18,
U19, U20
O
Output data bus for colour difference video data during dual pixel mode
operation. See
3.10.2 12-bits Output Resolution
.
LOCK_32
B20
O
Control signal output. When the GF9330's internal algorithm detects a 3:2
sequence in the video stream the LOCK_32 signal is set HIGH. Otherwise,
LOCK_32 is LOW.
XSEQ[3:0]
D19, D20, C19, C20
I/O
Control signal input/output. For external 3:2 sequence detection, the
XSEQ[3:0] pins will be used to provide the 3:2 sequence information. For
internal 3:2 detection the XSEQ[3:0] pins output the detected 3:2 sequence
information. See
Figure 3-12: Sequence Detection Input Signals
.
H_OUT
V20
O
Output control signal. H_OUT is HIGH during horizontal blanking.
F_OUT
V19
O
Output control signal. F_OUT is LOW during field 1 and HIGH during field 2.
V_OUT
W20
O
Output control signal. V_OUT is HIGH during vertical blanking.
S1_CLK
Y10
O
SDRAM bank 1 clock.
S1_CS
Y3
O
Active low SDRAM chip select for Field Buffer 1.
Table 1-1: Pin Descriptions (Continued)
Symbol
Pin Grid
Type
Description
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