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GS1531 HD-LINXTM II

Multi-Rate Serializer

GS1531 Data Sheet

30573 - 4

July 2005

1 of 49

Key Features
·

SMPTE 292M and SMPTE 259M-C compliant
scrambling and NRZ

NRZI encoding (with

bypass)

DVB-ASI sync word insertion and 8b/10b encoding

Superior rejection of jitter on input PCLK

user selectable additional processing features
including:

· CRC, ANC data checksum, and line number

calculation and insertion

· TRS and EDH packet generation and insertion
· illegal code remapping

internal flywheel for noise immune TRS generation

20-bit / 10-bit CMOS parallel input data bus

148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital input

automatic standards detection and indication

1.8V core power supply and 3.3V charge pump
power supply

3.3V digital I/O supply

JTAG test interface

Available in a Pb-free package

small footprint (11mm x 11mm)

Applications
·

SMPTE 292M Serial Digital Interfaces

SMPTE 259M-C Serial Digital Interfaces

DVB-ASI Serial Digital Interfaces

Description
The GS1531 is a multi-standard serializer with an
integrated cable driver. When used in conjunction with
the GO1525 Voltage Controlled Oscillator, a transmit
solution can be realized for HD-SDI, SD-SDI and
DVB-ASI applications.

The device features an internal PLL, which can be
configured for loop bandwidth as narrow as 100kHz.
Thus the GS1531 can tolerate substantive jitter on the
input PCLK and still provide output jitter well within
SMPTE specification. Connect the output clocks from
Gennum's GS4911 clock generator directly to the
GS1531's PCLK input and configure the GS1531's loop
bandwidth accordingly.

In addition to serializing the input, the GS1531 performs
NRZ-to-NRZI encoding and scrambling as per SMPTE
292M/259M-C when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will insert K28.5
sync characters and 8b/10b encode the data prior to
serialization.

Parallel data inputs are provided for 10-bit multiplexed
or 20-bit demultiplexed formats at both HD and SD
signal rates. An appropriate parallel clock input signal is
also required.

The integrated cable driver features an output mute on
loss of parallel clock, high impedance mode, adjustable
signal swing, and automatic dual slew rate selection
depending on HD/SD operational requirements.

The GS1531 also includes a range of data processing
functions including automatic standards detection and
EDH support. The device can also insert TRS signals,
calculate and insert line numbers and CRC's, re-map
illegal code words and insert SMPTE 352M payload
identifier packets. All processing features are optional
and may be enabled/disabled via external control pin(s)
and/or host interface programming.

GS1531 Data Sheet

30573 - 4

July 2005

3 of 49

Contents

Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out .....................................................................................................................5

1.1 Pin Assignment ...............................................................................................5
1.2 Pin Descriptions ..............................................................................................6

2. Electrical Characteristics........................................................................................13

2.1 Absolute Maximum Ratings ..........................................................................13
2.2 DC Electrical Characteristics ........................................................................13
2.3 AC Electrical Characteristics.........................................................................14
2.4 Solder Reflow Profiles...................................................................................16

3. Input/Output Circuits ..............................................................................................17

3.1 Host Interface Maps......................................................................................19

3.1.1 Host Interface Map (Read Only Registers).........................................20
3.1.2 Host Interface Map (R/W Configurable Registers) .............................21

4. Detailed Description ...............................................................................................22

4.1 Functional Overview .....................................................................................22
4.2 Parallel Data Inputs.......................................................................................22

4.2.1 Parallel Input in SMPTE Mode............................................................23
4.2.2 Parallel Input in DVB-ASI Mode..........................................................23
4.2.3 Parallel Input in Data-Through Mode..................................................23
4.2.4 Parallel Input Clock (PCLK) ................................................................24

4.3 SMPTE Mode................................................................................................25

4.3.1 Internal Flywheel.................................................................................25
4.3.2 HVF Timing Signal Extraction.............................................................25

4.4 DVB-ASI mode..............................................................................................27

4.4.1 Control Signal Inputs ..........................................................................27

4.5 Data-Through Mode......................................................................................28
4.6 Additional Processing Functions...................................................................28

4.6.1 Input Data Blank .................................................................................28
4.6.2 Automatic Video Standard Detection..................................................28
4.6.3 Packet Generation and Insertion ........................................................30

4.7 Parallel-To-Serial Conversion .......................................................................37
4.8 Serial Digital Data PLL..................................................................................38

4.8.1 External VCO......................................................................................38
4.8.2 Lock Detect Output .............................................................................38

4.9 Serial Digital Output ......................................................................................39

4.9.1 Output Swing ......................................................................................39
4.9.2 Serial Digital Output Mute...................................................................39

4.10 GSPI Host Interface ....................................................................................40

GS1531 Data Sheet

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July 2005

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4.10.1 Command Word Description.............................................................40
4.10.2 Data Read and Write Timing ............................................................41
4.10.3 Configuration and Status Registers ..................................................42

4.11 JTAG...........................................................................................................42
4.12 Device Power Up ........................................................................................44
4.13 Device Reset...............................................................................................44

5. Application Reference Design................................................................................45

5.1 Typical Application Circuit.............................................................................45

6. References & Relevant Standards.........................................................................46
7. Package & Ordering Information............................................................................47

7.1 Package Dimensions ....................................................................................47
7.2 Packaging Data.............................................................................................48
7.3 Ordering Information .....................................................................................48

8. Revision History .....................................................................................................49

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS1531

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS1531