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GS1578A HD-LINX II
Multi-Rate Dual Slew-Rate Cable Driver
GS1578A Data Sheet
33657 - 4
March 2006
1 of 15
Features
SMPTE 292M, SMPTE 344M and SMPTE 259M
compliant
Dual coaxial cable driving outputs with selectable
slew rate
50
differential PECL input
Pb-free and RoHS compliant
Seamless interface to other HD-LINX II family
products
Single 3.3V power supply operation
Operating temperature range: 0C to 70C
Applications
SMPTE 292M, SMPTE 344M and SMPTE 259M
Coaxial Cable Serial Digital Interfaces.
Description
The GS1578A is a second generation high-speed
BiCMOS integrated circuit designed to drive one or two
75
co-axial cables.
The GS1578A may drive data rates up to 1.485Gb/s
and provides two selectable slew rates in order to
achieve compliance to SMPTE 259M, SMPTE 344M
and SMPTE 292M.
The GS1578A accepts a LVPECL level differential input
that may be AC coupled. External biasing resistors at
the inputs are not required.
Power consumption is typically 168mW using a 3.3V
power supply. The GS1578A is Pb-free, and the
encapsulation compound does not contain halogenated
flame retardant.
This component and all homogeneous subcomponents
are RoHS compliant.
Functional Block Diagram
SDO
R
SET
SDO
SDI
SDI
SD/HD
BANDGAP REFERENCE AND BIASING CIRCUIT
OUTPUT STAGE &
CONTROL
INPUT
DIFFERENTIAL
PAIR
GS1578A Data Sheet
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March 2006
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Contents
Features ........................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out ......................................................................................................................3
1.1 Pin Assignment ...............................................................................................3
1.2 Pin Descriptions ..............................................................................................3
2. Electrical Characteristics...........................................................................................4
2.1 Absolute Maximum Ratings ............................................................................4
2.2 Solder Reflow Profiles .....................................................................................4
2.3 DC Electrical Characteristics ..........................................................................5
2.4 AC Electrical Characteristics ...........................................................................6
3. Input / Output Circuits ...............................................................................................7
4. Detailed Description ..................................................................................................8
4.1 Input Interfacing ..............................................................................................8
4.2 Output Interfacing ...........................................................................................8
4.3 Output Return Loss Measurement ................................................................11
4.4 Output Amplitude (RSET) .............................................................................11
5. Application Information............................................................................................12
5.1 PCB Layout ...................................................................................................12
5.2 Typical Application Circuit .............................................................................12
6. Package & Ordering Information.............................................................................13
6.1 Package Dimensions ....................................................................................13
6.2 Recommended PCB Footprint ......................................................................14
6.3 Packaging Data .............................................................................................14
6.4 Ordering Information .....................................................................................14
7. Revision History ......................................................................................................15
GS1578A Data Sheet
33657 - 4
March 2006
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1. Pin Out
1.1 Pin Assignment
Figure 1-1: 16-Pin QFN
1.2 Pin Descriptions
GS1578A
(top view)
1
V
EE
SDI
SDI
2
3
4
SDO
SDO
VCC
12
11
10
9
5
7
6
8
NC
NC
NC
NC
13
14
15
16
Center Pad
(bottom of package)
NC
NC
NC
NC
RSET
SD / HD
Table 1-1: Pin Descriptions
Pin Number
Name
Timing
Type
Description
1,2
SDI, SDI
Analog
Input
Serial digital differential input.
3
V
EE
Power
Most negative power supply connection. Connect to GND.
4
R
SET
Analog
Input
External output amplitude control resistor.
5,6,7,8,13,14,
15,16
NC
No Connect. Not bonded internally.
9
V
CC
Power
Most positive power supply connection. Connect to +3.3V.
10
SD/HD Non
Synchronous
Input
Output slew rate control. When set HIGH, the output will meet
SMPTE 259M rise/fall time specifications. When set LOW, the
serial outputs will meet SMPTE 292M rise/fall time
specifications.
11,12
SDO, SDO
Analog
Output
Serial digital differential output.
Center Pad
Power
Connect to most negative power supply plane following the
recommendations in
Recommended PCB Footprint on
page 14
.
GS1578A Data Sheet
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March 2006
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both
standard eutectic and Pb-free solder reflow profiles. MSL qualification was
performed using the maximum Pb-free reflow profile shown in
Figure 2-1
.The
recommended standard Pb reflow profile is shown in
Figure 2-2
.
Figure 2-1: Maximum Pb-free Solder Reflow Profile (Preferred)
Parameter
Value
Supply Voltage
-0.5V to 3.6 V
DC
Input ESD Voltage
2kV
Storage Temperature Range
-50C < T
s
< 125C
Input Voltage Range (any input)
-0.3 to (V
CC
+0.3)V
Operating Temperature Range
0C to 70C
Solder Reflow Temperature
260C
25C
150C
200C
217C
260C
250C
Time
Temperature
8 min. max
60-180 sec. max
60-150 sec.
20-40 sec.
3C/sec max
6C/sec max
GS1578A Data Sheet
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March 2006
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Figure 2-2: Standard Pb Reflow Profile (Pb-free package)
2.3 DC Electrical Characteristics
25C
100C
150C
183C
230C
220C
Time
Temperature
6 min. max
120 sec. max
60-150 sec.
10-20 sec.
3C/sec max
6C/sec max
Table 2-1: DC Electrical Characteristics
V
DD
= 3.3V, T
A
= 0C to 70C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply Voltage
V
CC
3.135
3.3
3.465
V
Power Consumption
P
D
T
A
= 25C
168
mW
Supply Current
I
s
T
A
= 25C
51
64
mA
Output Voltage
V
CMOUT
Common mode
V
CC
- V
OUT
V
Input Voltage
V
CMIN
Common mode
1.6 +
V
SDI
/2
V
CC
-
V
SDI
/2
V
SD/HD Input
V
IH
2.4
V
V
IL
0.8
V
GS1578A Data Sheet
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March 2006
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2.4 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
V
DD
= 3.3V, T
A
= 0C to 70C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Serial input data rate
DR
SDO
1.485
Gb/s
1
Additive jitter
1.485Gb/s
22
ps
p-p
270Mb/s
20
ps
p-p
Rise/Fall time
t
r
, t
f
SD/HD=0
220
ps
2
t
r
, t
f
SD/HD=1
400
800
ps
2
Mismatch in rise/fall time
t
r
, t
f
30
ps
Duty cycle distortion
SD/HD=0
30
ps
SD/HD=1
100
ps
Overshoot
SD/HD=0
10
%
SD/HD=1
8
%
Output Return Loss
ORL
15
dB
Output Voltage Swing
V
OUT
Single Ended into 75
external load
R
SET
= 750
750
800
850
mV
p-p
Input Voltage Swing
V
SDI
Differential
300
2000
mV
p-p
NOTES:
1. The input coupling capacitor must be set accordingly for lower data rates.
2. Rise/Fall time measured between 20% and 80%.
GS1578A Data Sheet
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March 2006
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3. Input / Output Circuits
Figure 3-1: Differential Input Stage (SDI/SDI)
Figure 3-2: Differential Output Stage (SDO/SDO)
Figure 3-3: Slew Rate Select Input Stage
V
CC
V
CC
SDI
SDI
10k
10k
5k
10k
V
cc
I
REF
SDO SDO
SD/HD
V
CC
On Chip
Reference
GS1578A Data Sheet
33657 - 4
March 2006
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4. Detailed Description
4.1 Input Interfacing
SDI/SDI are high impedance differential inputs. The equivalent input circuit is shown
in
Figure 3-1
.
Several conditions must be observed when interfacing to these inputs:
The differential input signal amplitude must be between 300 and 2000mVpp.
The common mode voltage range must be as specified in the
DC Electrical
Characteristics on page 5
.
For input trace lengths longer than approximately 1cm, the inputs should be
terminated as shown in the Typical Application Circuit.
The GS1578A inputs are self-biased, allowing for simple AC coupling to the device.
For serial digital video, a minimum capacitor value of 4.7F should be used to allow
coupling of pathological test signals. A tantalum capacitor is recommended.
SD/HD Input Pin
The GS1578A SDO rise and fall times can be set to comply with both SMPTE
259M/344M and SMPTE 292M. For all SMPTE 259M standards, or any data rate
that requires longer rise and fall time characteristics, the SD/HD pin must be set
HIGH by the application layer. For SMPTE 292M standards and signals which
require faster rise and fall times, this pin should be set LOW.
4.2 Output Interfacing
The GS1578A outputs are current mode, and will drive 800mV into a 75
load.
These outputs are protected from accidental static damage with internal static
protection diodes.
The SMPTE 292M, SMPTE 344M and SMPTE 259M standards require that the
output of a cable driver have a source impedance of 75
and a return loss of at
least 15dB between 5MHz and 1.485GHz.
In order for an SDI output circuit using the GS1578A to meet this specification, the
output application circuit shown in
Typical Application Circuit on page 12
is
recommended.
The value of L
COMP
will vary depending on the PCB layout, with a typical value of
5.6nH. A 4.7F capacitor is used for AC coupling the output of the device. This
value is chosen to ensure that pathological signals can be coupled without a
significant DC component occurring. Please see
Application Information on
page 12
for more details.
GS1578A Data Sheet
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March 2006
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Figure 4-1: Output signal for 270Mb/s input
Figure 4-2: Output signal for 1.485Gb/s input
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March 2006
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The output protection diodes act as a varactor (voltage controlled capacitor) as
shown in
Figure 4-3
. Therefore, when measuring return loss at the GS1578A
output, it is necessary to take the measurement for both a logic high and a logic low
output condition.
Consequently, the output capacitance of the device is dependent on the logic state
of the output.
Figure 4-3: Static Protection Diodes
SDO
SDO
GS1578A
GS1578A Data Sheet
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March 2006
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4.3 Output Return Loss Measurement
To perform a practical return loss measurement, it is necessary to force the
GS1578A output to a DC high or low condition. The actual measured return loss
will be based on the outputs being static at V
CC
or V
CC
-1.6V. Under normal
operating conditions the outputs of the device swing between V
CC
-0.4V and
V
CC
-1.2V, so the measured value of return loss will not represent the actual
operating return loss.
A simple method of calculating the values of actual operating return loss is to
interpolate the two return loss measurements. In this way, the values of return loss
are estimated at V
CC
-0.4V and V
CC
-1.2V based on the measurements at V
CC
and
V
CC
-1.6V.
The two values of return loss (high and low) will typically differ by several decibels.
If the measured return loss is R
H
for logic high and R
L
for logic low, then the two
values can be interpolated as follows:
R
IH
= R
H
- (R
H
-R
L
)/4 and
R
IL
= R
L
+(R
H
-R
L
)/4
where R
IH
is the interpolated logic high value and R
IL
is the interpolated logic low
value.
For example, if R
H
= -18dB and R
L
= -14dB, then the interpolated values are
R
IH
= -17dB and R
IL
= -15dB.
4.4 Output Amplitude (RSET)
The output amplitude of the GS1578A is set to 800mV
p-p
with a tolerance of 7%
using an RSET resistor of 750
. A 1% SMT resistor should be used.
The R
SET
resistor is part of the high speed output circuit of the GS1578A. The
resistor should be placed as close as possible to the R
SET
pin. In addition, the PCB
capacitance should be minimized at this node by removing the PCB groundplane
beneath the R
SET
resistor and the R
SET
pin.
NOTE: Only an R
SET
value of 750
1% should be used. Using other values for
R
SET
is not recommended.
GS1578A Data Sheet
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March 2006
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5. Application Information
5.1 PCB Layout
Special attention must be paid to component layout when designing serial digital
interfaces for HDTV.
An FR-4 dielectric can be used, however, controlled impedance transmission lines
are required for PCB traces longer than approximately 1cm. Note the following
PCB artwork features used to optimize performance:
The PCB trace width for HD rate signals is closely matched to SMT
component width to minimize reflections due to changes in trace impedance.
The PCB groundplane is removed under the GS1578A output components to
minimize parasitic capacitance.
The PCB ground plane is removed under the GS1578A R
SET
pin and resistor
to minimize parasitic capacitance.
Input and output BNC connectors are surface mounted in-line to eliminate a
transmission line stub caused by a BNC mounting via high speed traces which
are curved to minimize impedance variations due to change of PCB trace
width.
5.2 Typical Application Circuit
Figure 5-1: Typical Application Circuit
SD/HD
GS1578A
1
2
3
4
12
11
10
9
SDI
SDI
VEE
RSET
SDO
SDO
SD/HD
VCC
10n
75
5.6n
4u7
BNC
VCC
75
5.6n
10n
75
4u7
49.9
750
10n
49.9
4u7
75
BNC
VCC
4u7
VCC
* TYPICAL VALUE: VARIES WITH LAYOUT
DIFFERENTIAL
DATA INPUT
*
*
NOTE: All resistors in Ohms, capacitors in Farads,
and inductors in Henrys, unless otherwise noted.
GS1578A Data Sheet
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March 2006
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6. Package & Ordering Information
6.1 Package Dimensions
4.00+/-0.05
B
4.00+/-0.05
2X
2X
0.15
0.15
C
C
0.10 C
16X
0.08 C
SEATING PLANE
0.85+/-0.05
0.00-0.05
0.65/2
0.65
DETAIL B
SCALE:NTS
DATUM A OR B
TERMINAL TIP
0.20 REF
DATUM B
0.65
16X
0.35+/-0.05
0.10
0.05
C
A B
C
DATUM A
2.76+/-0.10
0.40+/-0.05
2.76+/-0.10
DETAIL B
CENTER TAB
PIN 1 AREA
A
C
GS1578A Data Sheet
33657 - 4
March 2006
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6.2 Recommended PCB Footprint
The Center Pad should be connected to the most negative power supply plane
(VEE) by a minimum of 5 vias.
NOTE: Suggested dimensions only. Final dimensions should conform to customer
design rules and process optimizations.
6.3 Packaging Data
6.4 Ordering Information
0.35
0.55
2.76
3.70
2.76
3.70
NOTE: All dimensions
are in millimeters.
0.65
CENTER PAD
Parameter
Value
Package Type
4mm x 4mm 16-pin QFN
Package Drawing Reference
JEDEC M0220
Moisture Sensitivity Level
3
Junction to Case Thermal Resistance,
j-c
31.0C/W
Junction to Air Thermal Resistance,
j-a
(at zero airflow)
43.8C/W
Psi
11.0C/W
Pb-free and RoHS compliant
Yes
Part Number
Package
Temperature Range
GS1578A
GS1578ACNE3
16-pin QFN
0C to 70C
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
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Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
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25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the
circuits or devices described herein. The sale of the circuit or device described herein does not imply any
patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.
GENNUM and the G logo are registered trademarks of Gennum Corporation.
Copyright 2005 Gennum Corporation. All rights reserved. Printed in Canada.
www.gennum.com
GS1578A Data Sheet
33657 - 4
March 2006
15
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DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes to the product at any time without notice to improve reliability,
function or design, in order to provide the best product possible.
7. Revision History
Version
ECR
PCN
Date
Changes and/or Modifications
A
135502
February 2005
New document.
0
136045
February 2005
Convert to Preliminary Data Sheet.
1
137132
June 2005
Converted to Data Sheet. Changed title
of
Figure 2-2
to clarify that it is the Pb
reflow profile. Updated SD additive jitter
number in the AC electrical
characteristics table to be typically
20ps
p-p
. Updated dimensions on center
pad of the PCB footprint in
Section 6.2
to match the dimensions of the center
pad of the device. Corrected part
number in ordering information.
Rephrased the RoHS Compliant
statement.
2
137885
September 2005
Corrected process to BiCMOS. Updated
eye diagrams in
Section 4.2
.
3
139113
38124
January 2006
Corrected Input Differential Swing to
2200mV.
4
139637
38695
March 2006
Corrected pad standoff height and
tolerances for pad width & package
dimension. Corrected pad shape.
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