GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: November 2000
Document No. 522 - 80 - 00
PRELIMINARY DATA SHEET
G
S
7
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FEATURES
SMPTE 259M-C compliant (270Mb/s)
automatic cable equalization (typically greater than
350m of high quality cable)
serial data outputs muted and serial clock remains
active when input data is lost
operation independent of SAV/EAV sync signals
signal strength indicator output
carrier detect with programmable threshold level
power savings mode (output serial clock disable)
large IJT, typically 0.56UI beyond loop bandwidth
robust lock detect
APPLICATIONS
Cable equalization plus clock and data recovery for all high
speed serial digital interface applications involving SMPTE
259M-C.
DESCRIPTION
The GS7025 provides automatic cable equalization and
high performance clock and data recovery for serial digital
signals. The GS7025 receives either single-ended or
differential serial digital data and outputs differential clock
and retimed data signals at PECL levels (800mV). The on-
board cable equalizer provides up to 35dB of gain at
135MHz which typically results in equalization of greater
than 350m of high quality cable at 270Mb/s.
The GS7025 requires only one external resistor to set the
VCO centre frequency and provides adjustment free
operation.
The GS7025 has dedicated pins to indicate signal
strength, carrier detect, and LOCK. Optional external
resistors allow the carrier detect threshold level to be
customized to the user's requirement. In addition, the
GS7025 provides an 'Output Eye Monitor Test' (OEM_TEST)
for diagnostic testing of signal integrity after equalization,
prior to reslicing. The serial clock outputs can also be
disabled to reduce power. The GS7025 operates from a
single +5 or -5 volt supply.
BLOCK DIAGRAM
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
GS7025-CQM
44 pin MQFP Tray
0C to 70C
GS7025-CTM
44 pin MQFP Tape
0C to 70C
LF+ LFS LF-
CBG R
VCO
CARRIER DETECT
PHASELOCK
HARMONIC
FREQUENCY
ACQUISITION
VCO
LOCK
SDO
SDO
CLK_EN
SCO
SCO
MUTE
C
OSC
PHASE
DETECTOR
LOGIC
+
-
SDI
SDI
OEM_TEST
AGC CAP CD_ADJ
AUTO EQ
CONTROL
EYE
MONITOR
VARIABLE
GAIN EQ
STAGE
CHARGE
PUMP
+
-
+ -
SSI/CD
A/D
ANALOG
DIGITAL
MUX
DDI
DDI
PRO-LINX
TM
GS7025
Serial Digital Receiver
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ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage (V
S
)
5.5V
Input Voltage Range (any input)
V
CC
+ 0.5 to V
EE
- 0.5V
Operating Temperature Range
0C
T
A
70C
Storage Temperature Range
-65C
T
S
150C
Lead Temperature (soldering, 10 sec)
260C
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V, T
A
= 25C unless otherwise stated, R
LF
= 1.8k, C
LF1
= 15nF, C
LF2
= 3.3pF
PARAMETER
CONDITION
MIN
TYPICAL
1
MAX
UNITS
NOTES
TEST LEVEL
Supply Voltage
4.75
5
5.25
V
1
Supply Current
CLK_EN = 0
-
115
mA
1
CLK_EN = 1
-
125
SDI Common Mode Voltage
-
2.5
-
V
1
DDI Common Mode Input
Voltage Range
V
EE
+(V
DIFF
/2)
0.4 to 4.6
V
CC
-(V
DIFF
/2)
V
2
1
DDI Differential Input Drive
200
800
2000
mV
1
SSI/CD Output Current
Source,
C
LMAX
= 50pF,
R
L
= open cct.
-
-
18
A
3
Source,
C
LMAX
= 50pF,
R
L
=5K
-
-
110
A
3
Sink
-
1.0
1.5
mA
3
AGC Common Mode Voltage
-
2.7
-
V
1
OEM_TEST Bias Potential
-
4.5
-
V
5
1
A/D
High
2.0
-
-
V
1
Low
-
-
0.8
270, CLK_EN, IN _ENABLE
Input Voltage
High
2.0
-
-
V
1
Low
-
-
0.8
CLK_EN Input Voltage
High
2.5
-
-
V
1
Low
-
-
0.8
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LOCK Output Sink Current
500
-
-
A
3
1
CLK_EN Source Current
Low
-
26
55
A
1
NOTES
1. TYPICAL - measured on characterization board.
2. V
DIFF
is the differential input signal swing.
3. LOCK is an open collector output and requires an external pullup resistor.
4. If OEM_TEST is permanently enabled, operating temperature range is limited from 0C to 60C inclusive.
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
AC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V, V
EE
= 0V, T
A
= 25C unless otherwise stated, R
LF
= 1.8k, C
LF1
= 15nF, C
LF2
= 3.3pF
PARAMETER
CONDITIONS
MIN
TYPICAL
1
MAX
UNITS
NOTES
TEST
LEVEL
Serial Data Rate
SDI
-
270 (only)
-
Mb/s
1
Maximum Equalizer Gain
(see Figure 3)
@ 135MHz
-
35
-
dB
7
Additive Jitter
[Pseudorandom (2
23
-1)]
270Mb/s, 300m
(Belden 8281)
-
300
-
ps p-p
2, 7
3
Intrinsic Jitter
[Pseudorandom (2
23
-1)]
270Mb/s
-
185
-
ps p-p
2, 6
4
Intrinsic Jitter
[Pathological (SDI checkfield)]
270Mb/s
-
462
-
ps p-p
2, 6
1
Input Jitter Tolerance
270Mb/s
0.40
0.56
-
UI p-p
3, 6
1
Lock Time -
Synchronous Switch
t
switch
< 0.5s, 270Mb/s
-
1
-
s
4
7
0.5s< t
switch
<10ms
-
1
-
ms
t
switch
> 10 ms
-
4
-
ms
Carrier Loss Time
0.5
1
2
s
5
7
SDO to SCO Synchronization
-200
0
200
ps
7
SDO, SCO Output Signal Swing
75
DC load
600
800
1000
mV p-p
1
SDO, SCO Rise & Fall times
20%-80%
200
300
400
ps
7
SDI/SDI Input Resistance
-
10
-
k
7
6
SDI/SDI Input Capacitance
-
1.0
-
pF
7
6
SDI/SDI Input Return Loss
at 270MHz
15
20
-
dB
7
6
DC ELECTRICAL CHARACTERISTICS (continued)
V
CC
= 5.0V, T
A
= 25C unless otherwise stated, R
LF
= 1.8k, C
LF1
= 15nF, C
LF2
= 3.3pF
PARAMETER
CONDITION
MIN
TYPICAL
1
MAX
UNITS
NOTES
TEST LEVEL
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Fig. 1 Test Setup for Figures 5 and 6
Carrier Detect Response Time
Carrier Applied,
C
L
<50pF, R
L
=open cct.
-
3
-
s
7
6
Carrier Removed,
C
L
<50pF, R
L
=open cct.
-
30
-
NOTES
1. TYPICAL - measured on characterization board.
2. Characterized 6 sigma rms.
3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz).
4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie. line 10 switching
for component NTSC).
5. Carrier Loss Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed.
6. Using the DDI input, A/D=0.
7. Using the SDI input, A/D=1.
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
AC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V, V
EE
= 0V, T
A
= 25C unless otherwise stated, R
LF
= 1.8k, C
LF1
= 15nF, C
LF2
= 3.3pF
PARAMETER
CONDITIONS
MIN
TYPICAL
1
MAX
UNITS
NOTES
TEST
LEVEL
CHARACTERIZATION
BOARD
GS9028
CABLE
DRIVER
TEKTRONIX
GigaBERT
1400
ANALYZER
TEKTRONIX
GigaBERT
1400
TRANSMITTER
BELDEN 8281
CABLE
DATA
DATA
CLOCK
TRIGGER
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PIN CONNECTIONS
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
1, 2
DDI/DDI
I
Digital data inputs (Differential ECL/PECL).
3, 44
V
CC
_75
I
Power supply connection for internal 75
pullup resistors connected to DDI/DDI.
4, 8, 13, 22, 35
V
CC
I
Most positive power supply connection.
5, 9, 14, 18, 27, 30,
33, 34, 37
V
EE
I
Most negative power supply connection.
6, 7
SDI/SDI
I
Differential analog data inputs.
10
CD_ADJ
I
Carrier detect threshold adjust.
11, 12
AGC-, AGC+
I
External AGC capacitor.
15, 16, 17
LF+, LFS, LF-
I
Loop filter component connection.
19
R
VCO
_RTN
I
R
VCO
Return.
20
R
VCO
I
Frequency setting resistor.
21
CBG
I
Internal bandgap voltage filter capacitor.
23, 25, 26
nc
-
No connect - Do not connect to power or ground. Leave floating.
24
270
I
270Mb/s Data Rate Select - Always set high.
28, 29
SCO/SCO
O
Serial clock output. SCO/SCO are differential current mode outputs and require
external 75
pullup resistors.
31, 32
SDO/SDO
O
Equalized and reclocked serial digital data outputs. SDO/SDO are differential current
mode outputs and require external 75
pullup resistors.
SDO
SDO
V
EE
SCO
SCO
V
EE
nc
nc
270
nc
GS7025
TOP VIEW
AGC+
V
CC
V
EE
LF+
LFS
LF-
V
EE
R
VCO
_RTN
R
VCO
CBG
V
CC
DDI
DDI
V
CC_75
V
CC
V
EE
SDI
SDI
V
CC
V
EE
CD_ADJ
AGC-
V
CC_75
OEM_TEST
MOD
A/D
SSI/CD
LOCK
C
OSC
V
EE
CLK_EN
V
CC
V
EE
V
EE
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18 19
20
21 22
44
43
42
41
40
39
38 37
36
35 34
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36
CLK_EN
I
Clock enable. When HIGH, the serial clock outputs are enabled.
38
C
OSC
I
Timing control capacitor for internal system clock.
39
LOCK
O
Lock indication. When HIGH, the GS7025 is locked. LOCK is an open collector output
and requires an external 10k
pullup resistor.
40
SSI/CD
O
Signal strength indicator/Carrier detect.
41
A/D
I
Analog/Digital select.
42
MOD
I
270 Mb/s modulus select - Always set high.
43
OEM_TEST
O
Output `Eye' monitor test. Single-ended current mode output that requires an external
50
pullup resistor. This feature is recommended for debugging purposes only. If
enabled during normal operation, the maximum operating temperature is rated to
60C.
PIN DESCRIPTIONS (continued)
NUMBER
SYMBOL
TYPE
DESCRIPTION
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TYPICAL PERFORMANCE CURVES (V
S
= 5V, T
A
= 25C unless otherwise shown)
Fig. 2 SSI/CD Voltage vs. Cable Length
(Belden 8281) (CD_ADJ = 0V)
Fig. 3 Equalizer Gain vs. Frequency
Fig. 4 Carrier Detect Adjust Voltage Threshold Characteristics
Fig. 5 Typical Additive Jitter vs. Input Cable Length (Belden 8281)
Pseudorandom (2
23
-1)
Fig. 6 Intrinsic Jitter (2
23
- 1 Pattern) 270Mb/s
Fig. 7 Typical IJT vs. Temperature (V
CC
= 5.0V) (Characterized)
0 50 100 150 200 250 300 350 400 450 500
5.00
4.50
4.00
3.50
3.00
2.50
CABLE LENGTH (m)
SSI/CD OUTPUT VOLTAGE (V)
0
5
10
15
20
25
30
35
40
45
50
1
10
100
1000
GAIN (dB)
FREQUENCY (MHz)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
200 250 300 350 400
CABLE LENGTH (m)
CD_ADJ VOLTAGE (V)
JITTER (ps p-p)
CABLE LENGTH (m)
450
400
350
300
250
200
150
100
50
0
0
50
100
150
200
250
300
350
400
270Mb/s
(Characterized)
0.200
0.250
0.300
0.350
0.400
0.450
0.500
0.550
0.600
0
10
20
30
40
50
60
70
TEMPERATURE (C)
IJT (UI)
270Mb/s
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DETAILED DESCRIPTION
The GS7025 Serial Digital Receiver is a bipolar integrated
circuit containing a built-in cable equalizer and reclocker.
Serial digital signals are applied to either the analog
SDI/SDI or digital DDI/DDI inputs. Signals applied to the
SDI/SDI inputs are equalized and then passed to a
multiplexer. Signals applied to the DDI/DDI inputs bypass
the equalizer and go directly to the multiplexer. The
analog/digital select pin (A/D) determines which signal is
then passed to the reclocker.
Packaged in a 44 pin MQFP, the receiver operates from a
single 5V supply at a data rate of 270Mb/s.
1. CABLE EQUALIZER
The automatic cable equalizer is designed to equalize a
serial digital data rate of 270Mb/s.
The serial data signal is connected to the input pins
(SDI/SDI) either differentially or single-endedly. The input
signal passes through a variable gain equalizing stage
whose frequency response closely matches the inverse
cable loss characteristic. In addition, the variation of the
frequency response with control voltage imitates the
variation of the inverse cable loss characteristic with cable
length. The gain stage provides up to 35dB of gain at
135MHz which typically results in equalization of greater
than 350m of Belden 8281 cable at 270Mb/s.
The edge energy of the equalized signal is monitored by a
detector circuit which produces an error signal
corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is
integrated by an external differential AGC filter capacitor
(AGC+/AGC-) providing a steady control voltage for the
gain stage. As the frequency response of the gain stage is
automatically varied by the application of negative
feedback, the edge energy of the equalized signal is kept
at a constant level which is representative of the original
edge energy at the transmitter.
The equalized signal is also DC restored, effectively
restoring the logic threshold of the equalized signal to its
corrective level irrespective of shifts due to AC coupling.
1-1. Signal Strength Indication/Carrier Detect
The GS7025 incorporates an analog signal strength
indicator/carrier detect (SSI/CD) output indicating both the
presence of a carrier and the amount of equalization
applied to the signal. The voltage output of this pin versus
cable length (signal strength) is shown in Figure 2 and
Figure 8.
With 0m of cable (800mV input signal levels), the SSI/CD
output voltage is approximately 4.5V. As the cable length
increases, the SSI/CD voltage decreases linearly providing
accurate correlation between the SSI/CD voltage and cable
length.
Fig. 8 SSI/CD Voltage vs. Cable Length
When the signal strength decreases to the level set at the
"Carrier Detect Threshold Adjust" pin, the SSI/CD voltage
goes to a logic "0" state (0.8 V) and can be used to drive
other TTL/CMOS compatible logic inputs. In addition, when
loss of carrier is detected, the SDO/SDO outputs are muted
(set to a known static state).
1-2. Carrier Detect Threshold Adjust
This feature has been designed for use in applications such
as routers where signal crosstalk and circuit noise cause
the equalizer to output erroneous data when no input signal
is present. The use of a Carrier Detect function with a fixed
internal reference does not solve this problem since the
signal to noise ratio on the circuit board could be
significantly less than the default signal detection level set
by the on chip reference. To alleviate this problem, the
GS7025 provides a user adjustable threshold to meet the
unique conditions that exist in each user's application.
Override and internal default settings have also been
provided to give the user total flexibility.
The threshold level at which loss of carrier is detected is
adjustable via external resistors at the CD_ADJ pin (
see
Figure 4). The control voltage at the CD_ADJ pin is set by a
simple resistor divider circuit (
see Typical Application
Circuit). The threshold level is adjustable from 200m to
350m. By default (no external resistors), the threshold is
typically 320m. In noisy environments, it is not
recommended to leave this pin floating. Connecting this pin
to V
EE
disables the SDO/SDO muting function and allows for
maximum possible cable length equalization.
1-3. Output Eye Monitor Test
The GS7025 also provides an 'Output Eye Monitor Test'
(OEM_TEST) which allows the verification of signal integrity
after equalization, prior to reslicing. The OEM_TEST pin is
an open collector current output that requires an external
50
pullup resistor. When the pullup resistor is not used,
the OEM_TEST block is disabled and the internal
OEM_TEST circuit is powered down. The OEM_TEST
0
1
2
3
4
5
50
100
150
200
250
300
350
400
450
500
SSI/CD OUTPUT VOLTAGE (V)
CABLE LENGTH (m)
0
CD_ADJ
CONTROL RANGE
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provides a 100mVp-p
signal when driving a 50
oscilloscope input. Due to additional power consumed by
this diagnostic circuit, it is not recommended for continuous
operation.
2. RECLOCKER
The reclocker receives a differential serial data stream from
the internal multiplexer. It locks an internal clock to the
incoming data. It outputs the differential PECL retimed data
signal on SDO/SDO. It outputs the recovered clock on SCO/
SCO. The timing between the output and clock signals is
shown in Figure 9.
Fig. 9 Output and Clock Signal Timing
The reclocker contains three main functional blocks: the
Phase Locked Loop, Frequency Acquisition, and Logic
Circuit.
2-1. Phase Locked Loop (PLL)
The Phase Locked Loop locks the internal PLL clock to the
incoming data rate. A simplified block diagram of the PLL is
shown below. The main components are the VCO, the
phase detector, the charge pump, and the loop filter.
Fig. 10 Simplified Block Diagram of the PLL
2-2. VCO
The VCO is a differential low phase noise, factory trimmed
oscillator that provides increased immunity to PCB noise
and precise control of the VCO centre frequency. The VCO
has a pull range of 15% about the centre frequency. A
single low impedance external resistor, R
VCO
, sets the VCO
centre frequency. The low impedance R
VCO
minimizes
thermal noise and reduces the PLL's sensitivity to PCB
noise.
The recommended R
VCO
value for SMPTE 259M-C
applications is 365
.
When the input data stream is removed for an excessive
period of time
(see AC electrical characteristics table), the
VCO frequency can drift from the 270Mb/s centre frequency
to the limits shown in Table1.
2-3. Phase Detector
The phase detector compares the phase of the PLL clock
with the phase of the incoming data signal and generates
error correcting timing pulses. The phase detector design
provides a linear transfer function which maximizes the
input jitter tolerance of the PLL.
2-4. Charge Pump
The charge pump takes the phase detector output timing
pulses and creates a charge packet that is proportional to
the system phase error. A unique differential charge pump
design insures that the output phase does not drift when
data transitions are sparse. This makes the GS7025 ideal
for SMPTE 259M-C applications where pathological signals
have data transition densities of 0.05.
2-5. Loop Filter
The loop filter integrates the charge pump packets and
produces a VCO control voltage. The loop filter is
comprised of three external components which are
connected to pins LF+, LFS, and LF-. The loop filter design
is fully differential giving the GS7025 increased immunity to
PCB board noise.
The loop filter components are critical in determining the
loop bandwidth and damping of the PLL. Choosing these
component values is discussed in detail in the PLL DESIGN
GUIDELINES section. Recommended values for SMPTE
259M-C applications are shown in the Typical Application
Circuit. No further changes from the recommended GS7025
loop filter components are necessary.
SDO
SCO
50%
DDI/DDI
LF+
LFS LF-
R
VCO
VCO
R
LF
C
LF1
C
LF2
2
PHASE
DETECTOR
INTERNAL
PLL CLOCK
CHARGE
PUMP
LOOP
FILTER
TABLE 1: Frequency Drift Range
FREQUENCY
MIN (%)
MAX(%)
270Mb/s lock
-13
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3. FREQUENCY ACQUISITION
The core PLL is able to lock if the incoming data rate and
the PLL clock frequency are within the PLL capture range
(which is slightly larger than the loop bandwidth). To assist
the PLL to lock, the GS7025 uses a frequency acquisition
circuit.
The frequency acquisition circuit sweeps the VCO control
voltage so that the VCO frequency changes from -10% to
+10% of the centre frequency. Figure 11 shows a typical
sweep waveform.
Fig. 11 Typical Sweep Waveform
The VCO frequency starts at point A and sweeps up
attempting to lock. If lock is not established during the up
sweep, the VCO is then swept down. The system is
designed such that the probability of locking within one
cycle period is greater than 0.999. If the system does not
lock within one cycle period, it will attempt to lock in the
subsequent cycle.
The average sweep time, t
swp
, is determined by the loop
filter component, C
LF1
, and the charge pump current,
CP
:
The nominal sweep time is approximately 121s when
C
LF1
= 15nF and
CP
= 165A (R
VCO
= 365
).
An internal system clock determines t
sys
(see section 3-1,
Logic Circuit).
3-1. Logic Circuit
The GS7025 is controlled by a finite state logic circuit which
is clocked by an asynchronous system clock. That is, the
system clock is completely independent of the incoming
data rate. The system clock runs at low frequencies, relative
to the incoming data rate, and thus reduces interference to
the PLL.The period of the system clock is set by the C
OSC
capacitor and is:
The recommended value for t
sys
is 450s (C
OSC
= 4.7nF)
4. LOCKING
The GS7025 indicates valid lock when the following three
conditions are satisfied:
1. Input data is detected.
2. The incoming data signal and the PLL clock are phase
locked.
3. The system is not locked to an integer-multiple harmonic
of a 270Mb/s SMPTE 259M-C signal.
The GS7025 defines the presence of input data when at
least one data transition occurs every 1s.
The GS7025 assumes that it is NOT locked to a harmonic if
the pattern `101' or `010' (in the reclocked data stream)
occurs at least once every t
sys
/3 seconds. Using the
recommended component values, this corresponds to
approximately 150s. In a harmonically locked system, all
bit cells are double clocked and the above patterns
become `110011' and `001100', respectively.
4-1. Lock Time
Synchronous switching refers to the case where the input
data is changed from one source to another source which is
at the same data rate (but different phase).
When input data to the GS7025 is removed, the GS7025
latches the current state. Therefore, when data is reapplied,
the GS7025 begins the lock procedure at the previous
locked data rate. As a result, in synchronous switching
applications, the GS7025 locks very quickly. The nominal
lock time depends on the switching time and is summarized
in the Table 3.
To acquire lock, the frequency acquisition circuit may have
to sweep over an entire cycle depending on initial
conditions. Maximum lock time is 2T
cycle
+ 2t
sys
.
The nominal value of T
cycle
for the GS7025 operating in a
typical SMPTE 259M-C application is approximately 1.3ms.
The GS7025 has a dedicated LOCK output (pin 39)
indicating when the device is locked. It should be noted
that in synchronous switching applications where the
switching time is less than 0.5s, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.
V
LF
t
swp
T
cycle
T
cycle
= t
swp
+ t
sys
t
sys
A
t
SWP
4C
LF1
3I
CP
----------------
=
t
sys
9.6
10
4
C
OSC
onds
sec
[
]
=
TABLE 3.
SWITCHING TIME
LOCK TIME
<0.5s
10s
0.5s - 10ms
2t
sys
>10ms
2T
cycle
+ 2t
sys
GENNUM CORPORATION
522 - 80 - 00
11
G
S
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025
5. OUTPUT DATA MUTING
The GS7025 internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data.
The output data muting timing is shown in Figure 12.
Fig. 12 Output Data Muting Timing
6. CLOCK ENABLE
When CLK_EN is high, the GS7025 SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO/SCO outputs are
placed in a high Z state and float to V
CC
. Disabling the
clock outputs results in a power savings of 10%. It is
recommended that the CLK_EN input be hard wired to the
desired state. For applications which do not require the
clock output, connect CLK_EN to Ground and connect the
SCO/SCO outputs to V
CC
.
7. STRESSFULL DATA PATTERNS
All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of 0's or
1's (low data transition densities for a long period of time).
The GS7025 is designed to operate with low data transition
densities such as the SMPTE 259M-C pathological signal
(data transition density = 0.05).
8. I/O DESCRIPTION
8-1. High Speed Analog Inputs (SDI/SDI)
SDI/SDI are high impedance inputs which accept
differential or single-ended input drive.
Figure 13 shows the recommended interface when a single-
ended serial digital signal is used.
Fig. 13
8-2. High Speed Digital Inputs (DDI/DDI)
DDI/DDI are high impedance inputs which accept
differential or single-ended input drive. Two conditions must
be observed when interfacing to these inputs:
1. Input signal amplitudes are between 200 and 2000mV.
2. The common mode input voltage range is as specified
in the DC Characteristics table.
Commonly used interface examples are shown in Figures
14 to 16.
Figure 14 illustrates the simplest interface to the GS7025
digital inputs. In this example, the driving device generates
the PECL level signals (800mV amplitudes) having a
common mode input range between 0.4 and 4.6V. This
scheme is recommended when the trace lengths are less
than 1in. The value of the resistors depends on the output
driver circuitry.
Fig. 14
When trace lengths become greater than 1in, controlled
impedance traces should be used. The recommended
interface is shown in Figure 15. In this case, a parallel
resistor (R
LOAD
) is placed near the GS7025 inputs to
terminate the controlled impedance trace. The value of
R
LOAD
should be twice the value of the characteristic
impedance of the trace. In addition, place series resistors
(R
SOURCE
) near the driving chip to serve as source
terminations. They should be equal to the value of the trace
impedance. Assuming 800mV output swings at the driver,
R
LOAD
= 100
, R
SOURCE
= 50
and Z
O
= 50
.
Fig. 15
Figure 16 shows the recommended interface when the
GS7025 digital inputs are driven single-endedly. In this
case, the input must be AC-coupled and a matching
resistor (Zo) must be used.
Fig. 16
When the DDI and the DDI inputs are not used, saturate
one input of the differential amplifier for improved noise
immunity. To saturate, connect either pins 44 and 1 or pins
2 and 3 to V
CC
. Leave the other pair floating.
LOCK
DDI
SDO
VALID
DATA
NO DATA TRANSITIONS
VALID
DATA
OUTPUTS MUTED
SDI
GS7025
SDI
75
10nF
10nF
75
113
DDI
DDI
GS7025
DDI
DDI
R
SOURCE
R
LOAD
R
SOURCE
Z
O
Z
O
GS7025
DDI
DDI
Z
O
GS7025
GENNUM CORPORATION
522 - 80 - 00
12
G
S
7
025
8-3. High Speed Outputs (SDO/SDO and SCO/SCO)
SDO/SDO and SCO/SCO are current mode outputs that
require external pullups (
see Figure 17). The output signal
swings are 800mV when 75
resistors are used. To shift the
signal levels down by approximately 0.7 volts, place a
diode between V
CC
and the pullups. When the output traces
are longer than 1in, use controlled impedance traces. Place
the pullup resistors at the end of the output traces as they
terminate the trace in its characteristic impedance (75
).
Fig. 17
TYPICAL APPLICATION CIRCUIT
V
CC
SDO
SDO
SCO
SCO
75
75
V
CC
75
75
GS7025
SDO
SDO
V
EE
SCO
SCO
V
EE
nc
nc
270
nc
GS7025
TOP VIEW
AGC+
V
CC
V
EE
LF+
LFS
LF-
V
EE
R
VCO
_RTN
R
VCO
CBG
V
CC
DDI
DDI
V
CC_75
V
CC
V
EE
SDI
SDI
V
CC
V
EE
CD_ADJ
AGC-
V
CC_75
OEM_TEST
MOD
A/D
SSI/CD
LOCK
C
OSC
V
EE
CLK_EN
V
CC
V
EE
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
4 x 75
see Note 2
To
GS9020
1.8k 15n
0.1 0.1
3.3p
365
(1%)
10k
75
37.5
75
10n
10n
75
100k
Pot
(Optional)
0.1
Power supply decoupling
capacitors are not shown.
V
EE
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12
13
14 15 16 17 18 19 20
21 22
44
43
42 41 40 39 38 37 36
35 34
All resistors in ohms,
all capacitors in microfarads,
unless otherwise stated.
NOTES
1. It is recommended that the DDI/DDI inpute are not driven when the SDI/SDI inputs are being used.
This minimizes crosstalk between the DDI/DDI and SDI/SDI inputs and maximizes performance.
2. These resistors are not needed if the internal pull-up resistors on the GS9020 are used.
V
CC
4n7
V
CC
15nH
0.1
V
CC
V
CC
V
CC
from GS9024
see Note 1
522 - 80 - 00
13
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
Copyright November 2000 Gennum Corporation. All rights reserved. Printed in Canada.
G
S
7
025
PACKAGE DIMENSIONS
10.00 0.10
13.20 0.25
PIN 1
10.00
0.10
0.80 BSC
0.45 MAX
0.30 MIN
13.20
0.25
2.20 MAX
1.85 MIN
0.35 MAX
0.15 MIN
2.55 MAX
0.23
MAX.
1.60
REF
0.3 MAX.
RADIUS
0.13 MIN.
RADIUS
0.88
NOM.
0.20 MIN
5 to 16
5 to 16
7 MAX
0 MIN
0 MIN
44 pin MQFP
All dimensions in millimetres
REVISION NOTES:
New document.
For latest product information, visit www.gennum.com
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET
The product is in a preproduction phase and specifications
are subject to change.
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