GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: June 2004
Document No. 18784 - 3
DATA SHEET
GS9
000
D
FEATURES
fully compatible with SMPTE 259M-ABC
decodes 8 and 10 bit serial digital signals for data rates to
270Mb/s
recommended alternative to GS9000C for use when
interfacing directly to GS7025, GS9025A or GS9035A
incorporates automatic standards selection
325mW power dissipation at 270MHz clock rate
Pb-free and Green
operates from single +5 or -5 volt supply
28 pin PLCC packaging
APPLICATIONS
4
SC
and 4:2:2 serial digital interfaces
Automatic standards select controller for serial routing
and distribution applications
DEVICE DESCRIPTION
The GS9000D is a CMOS integrated circuit specifically
designed to deserialize SMPTE 259M serial digital signals
at data rates up to 270Mb/s. The GS9000D is a pin and
functional equivalent to the GS9000C, with the exception of
SDI input levels which are compatible for direct interfacing
to the GS7025, GS9025A and GS9035A.
The device incorporates a descrambler, serial to parallel
convertor, sync processing unit, sync warning unit and
automatic standards select circuitry.
Differential pseudo-ECL inputs for both serial clock and
data are internally level shifted to CMOS levels. Digital
outputs such as parallel data, parallel clock, HSYNC, Sync
Warning and Standard Select are all TTL compatible.
The GS9000D is packaged in a 28 pin PLCC and operates
from a single 5 volt, 5% power supply.
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
Pb-FREE AND GREEN
GS9000DCPJ
28 Pin PLCC
0C to 70C
No
GS9000DCTJ
28 Pin PLCC Tape
0C to 70C
No
GS9000DCPJE3
28 Pin PLCC
0C to 70C
Yes
GS9000DCTJE3
28 Pin PLCC Tape
0C to 70C
Yes
GS9000D
SERIAL DATA IN
SERIAL DATA IN
SERIAL CLOCK IN
SERIAL CLOCK IN
LEVEL
SHIFT
SP
SYNC CORRECTION
ENABLE
STANDARDS SELECT
CONTROL
SYNC WARNING
CONTROL
DESCRAMBLER
LEVEL
SHIFT
OSC
2 BIT
COUNTER
PARALLEL
TIMING
GENERATOR
PARALLEL CLOCK
OUT
PARALLEL DATA
OUT (10 BITS)
Sync
Word
Boundary
Sync Error
Hsync Reset
SCLK
HSYNC OUTPUT
SS0
SS1
SYNC WARNING
FLAG
30 - BIT
SHIFT REG
SYNC DETECT
(3FF 000 000 HEX)
SYNC CORRECTION
SYNC WARNING
(Schmitt Trigger
Comparator)
AUTO STANDARD SELECT
GENLINX II
TM
GS9000D
Serial Digital Decoder
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GS9
000
D
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage (V
S
= V
DD
- V
SS
)
7V
Input Voltage Range (any input)
-0.3 to (V
DD
+ 0.3)
DC Input Current (any one input)
10A
Operating Temperature Range
0C to 70C
Storage Temperature Range
-65C to +150C
Lead Temperature (Soldering, 10 seconds)
260C
DC ELECTRICAL CHARACTERISTICS
V
DD
= 5V, T
A
= 0C to 70C unless otherwise shown
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
TEST
LEVEL
Supply Voltage
V
S
Operating range
4.75
5.00
5.25
V
3
Power Consumption (outputs
unloaded)
P
C
= 143MHz
-
235
-
mW
7
= 270MHz
-
325
-
mW
7
CMOS Input Voltage
VIH
MIN
T
A
= 25C
3.4
-
-
V
1
VIL
MAX
-
-
1.5
V
1
Output Voltage
VOH
MIN
I
OH
= 4mA, 25C
2.4
4.5
-
V
1
VOL
MAX
I
OL
= 4mA, 25C
-
0.2
0.5
V
1
Input Leakage Current
IN
V
IN
= V
DD
or V
SS
-
-
10
A
3
Serial Clock and Data Inputs
Common Mode Voltage
V
CM
T
A
= 25C,
V
IN
= 700 to 1200mVpp
3.0
-
4.05
V
Centre of
Swing
1
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
9. Indirect test.
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GS9
000
D
AC ELECTRICAL CHARACTERISTICS
V
DD
= 5V, T
A
= 0C to 70C unless otherwise shown
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
TEST
LEVEL
Serial Input Clock Frequency
SCI
100
-
270
MHz
1
Serial Input Data Rate
DR
SDI
100
-
270
Mb/s
1
Serial Data and Clock Inputs:
T
A
= 25C
Setup
t
SU
1.0
-
-
ns
7
Hold
t
HOLD
1.0
-
-
ns
7
Signal Swing
V
IN
700
800
1200
mVpp
1
Parallel Clock: Jitter
t
JCLK
T
A
= 25
-
1.0
-
ns p-p
7
Parallel Data: Risetime and Falltime
t
R-PDn
T
A
= 25C,
C
L
= 10pF
-
3
-
ns
20% to
80%
7
PDn to PCLK Delay Tolerance
t
D
-
-
3
ns
Rising
edge of
PCLK to bit
period
centre
7
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
9. Indirect test.
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000
D
Fig. 1 GS9000D Pin Outs, 28 Pin PLCC Package
PIN DESCRIPTIONS
PIN NO.
SYMBOL
TYPE
DESCRIPTION
1 HSYNC
Output
Horizontal Sync Output.
CMOS (TTL compatible) output that toggles for each TRS detected.
2
V
SS
Power Supply
. Most negative power supply connection.
3
SWF
Output
Sync Error Warning Flag. CMOS (TTL compatible) active high output that indicates the
preselected HSYNC Error Rate (HER). The HER is set with an RC time constant on the SWC
input.
4 V
SS
Power Supply
. Most negative power supply connection.
5, 6
SDI/SDI
Inputs
Differential, pseudo-ECL serial data inputs
. ECL voltage levels with offset of 3.0V to 4.05V for
operation up to 270MHz. See AC Electrical Characteristics Table for details.
7, 8
SCI/SCI
Inputs
Differential, pseudo-ECL serial clock inputs.
ECL voltage levels with offset of 3.0V to 4.05V for
operation up to 270MHz. See AC Electrical Characteristics Table for details.
9,10
SS1/SS0
Output
Standard Select Outputs
. CMOS (TTL compatible) outputs is generated by a 2-bit internal
binary counter which stops cycling when a valid TRS is detected by the GS9000D.
11 SSC
Input
Standards Select Control
. Analog input used to set a time constant for the standards select
hunt period. An external RC sets the time constant.
12
V
DD
Power Supply
. Most positive power supply connection.
13
V
DD
Power Supply
. Most positive power supply connection.
14 SCE
Input
Sync Correction Enable
. Active high CMOS input which enables sync correction by not
resetting the GS9000D's internal parallel timing on the first sync error. If the next incoming
sync is in error, internal parallel timing will be reset. This is to guard against spurious HSYNC
errors. When SCE is low, a valid sync will always reset the GS9000D's parallel timing generator
PD7
PD6
PD5
PD4
PD3
PD2
PD1
SDI
SDI
SCI
SCI
SS1
SS0
SSC
V
S S
S W F V
S S
H S Y N C P D 9 P D 8 V
S S
GS9000D
TOP VIEW
V
D D
V
D D
S C E S W C P C L K P D 0 V
D D
( L S B )
2 5
2 4
2 3
2 2
2 1
2 0
1 9
5
6
7
8
9
1 0
1 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8
4 3 2 2 8 2 7 2 6
( M S B )
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000
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INPUT/OUTPUT CIRCUITS
Fig. 2 Pin 11 SSC
Fig. 3 Pin 14 SCE
Fig. 4 Pins 5 - 8 SDI - SCI
15 SWC
Input
Sync Warning Control
. Analog input used to set the HSYNC Error Rate (HER). This is
accomplished by an external RC time constant connected to this pin.
16 PCLK
Output
Parallel Clock Output.
CMOS (TTL compatible) clock output where the rising edge of the
clock is located at the centre of the parallel data window within a given tolerance. See Fig. 7.
17 PD0
Output
Parallel Data Output - Bit 0 (LSB)
. CMOS (TTL compatible) descrambled parallel data output
from the serial to parallel convertor representing the least significant bit (LSB).
18
V
DD
Power Supply.
Most positive power supply connection.
19-25
PD1 - PD7
Outputs
Parallel Data Outputs - Bit 1 to Bit 7.
CMOS (TTL compatible) descrambled parallel data
outputs from the serial to parallel convertor representing data bit 1 through data bit 7.
26
V
SS
Power Supply
. Most negative power supply connection.
27
PD8
Output
Parallel Data Output.
CMOS (TTL compatible) descrambled parallel data output from the
serial to parallel convertor representing data bit 8.
28
PD9 Output
Parallel Data Output - Bit 9 (MSB)
. CMOS (TTL compatible) descrambled data output from
the serial to parallel convertor representing the most significant bit (MSB).
PIN DESCRIPTIONS
PIN NO.
SYMBOL
TYPE
DESCRIPTION
R
EXT
EXTERNAL
COMPONENTS
SSC
V
DD
V
DD
SCE
V
DD
V
DD
SDI
SCI
BIAS
SDI
SCI
V
DD
V
DD
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