GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: May 2005
Document No. 521 - 96 - 09
DATA SHEET
GS90
32
FEATURES
SMPTE 259M and 540Mb/s compliant
serializes 8-bit or 10-bit data
autostandard, adjustment free operation
minimal external components (no loop filter
components required)
isolated, quad output, adjustable cable driver
power saving secondary cable driver disable
3.3V and 5.0V CMOS/TTL compatible inputs
lock detect indication
SMPTE scramble and NRZI coding bypass option
EDH support with GS9001, GS9021
Pb-free and RoHS Comliant
APPLICATION
SMPTE 259M and 540Mb/s parallel to serial interfaces for
video cameras, VTRs, and signal generators; generic
parallel to serial conversion.
DESCRIPTION
The GS9032 encodes and serializes SMPTE 125M and
244M bit parallel digital video signals, and other 8-bit or
10-bit parallel formats. This device performs sync
detection, parallel to serial conversion, data scrambling
(using the X
9
+ X
4
+ 1 algorithm), 10x parallel clock
multiplication and conversion of NRZ to NRZI serial data.
The GS9032 features auto standard and adjustment free
operation for data rates to 540Mb/s with a single VCO
resistor. Other features include a lock detect output, NRZI
encoding, SMPTE scrambler bypass, a sync detect disable,
and an isolated quad output cable driver suitable for driving
75
loads. The complementary cable driving output swings
can be adjusted independently or the secondary differential
cable driver can be powered down.
The GS9032 requires a single +5 volt or -5 volt supply and
typically consumes 675mW of power while driving four 75
loads.
BLOCK DIAGRAM
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
Pb-FREE AND RoHS COMPLIANT
GS9032 - CVM
44 pin TQFP
0C to 70C
No
GS9032 - CTM
44 pin TQFP Tape
0C to 70C
No
GS9032 - CVME3
44 pin TQFP
0C to 70C
Yes
GS9032 - CTME3
44 pin TQFP Tape
0C to 70C
Yes
AUTO/MANUAL SELECT
(AUTO/MAN)
LOCK
DETECT
(LOCK DET)
SDO1
ENABLE
SERIAL
DIGITAL
OUTPUTS
PARALLEL CLOCK
INPUT (PCLKIN)
P
LOAD
S
CLK
S
CLK
/10
LOOP BANDWIDTH
CONTROL (LBWC)
R
VCO+
R
VCO-
DATA RATE SELECT
SS[2:0]
MUTE
RESET
RESET
SYNC DETECT DISABLE (SYNC DIS)
BYPASS
BYPASS
PARALLEL
to SERIAL
CONVERTER
&
NRZ to NRZI
DATA
IN
(PD0-PD9)
10
3
10
8
INPUT
LATCH
2
10
SYNC
DETECT
SMPTE
SCRAMBLER
PLL
SDO0
SDO0
SDO1
SDO1
GENLINX
TM
II
GS9032
Digital Video Serializer
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003
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ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage (V
S
= V
CC
-V
EE
)
5.5V
Input Voltage Range (any input)
V
EE
<V
IN
<V
CC
DC Input Current (any one input)
5mA
Power Dissipation (V
CC
= 5.25V)
1200mW
j-a
42.5C/W
j-c
6.4C/W
Maximum Die Temperature
125C
Operating Temperature Range
0C
T
A
70C
Storage Temperature Range
-65C
T
S
150C
Lead Temperature (soldering, 10 sec)
260C
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5V, V
EE
= 0V, T
A
= 0 70C unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
TEST
LEVEL
Positive Supply Voltage
V
CC
Operating Range
4.75
5.00
5.25
V
3
Power (System Power)
P
V
CC
= 5.0V, T = 25C (4 outputs)
-
675
-
mW
5
Supply Current
CC
V
CC
= 5.25V (4 outputs)
-
-
180
mA
1
V
CC
= 5.0V, T = 25C (4 outputs)
-
135
-
3
V
CC
= 5.25V (2 outputs)
-
-
160
1
V
CC
= 5.0V, T = 25C (2 outputs)
-
110
-
7
Data & Clock Inputs
(PD[9:0] PCLKIN)
SYNC DIS
V
IH
Logic Input High (wrt V
EE
)
2.4
-
-
V
3
V
IL
Logic Input Low (wrt V
EE
)
-
-
0.8
V
L
Input Current
-
-
8.0
A
Logic Input Levels
(Auto/Man, SS[2:0]
Bypass, RESET)
V
IH
Logic Input High (wrt to V
EE
)
2.4
-
-
V
3
V
IL
Logic Input Low (wrt to V
EE
)
-
-
0.8
V
L
Input Current
-
-
5.0
A
Lock Detect Output
V
OL
Sinking 500A
-
-
0.4
V
1
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
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AC ELECTRICAL CHARACTERISTICS
V
CC
= 5V, V
EE
= 0V, T
A
= 0 70C unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
TEST
LEVEL
Serial Data Bit Rate
BR
SDO
R
VCO
= 374
143
-
540
Mb/s
SMPTE
259M
3
Serial Data Outputs Signal
Swing
V
SDO
R
LOAD
= 37.5
, R
SET
= 54.9
740
800
860
mVp-p
1
Min. Swing (adjusted)
V
SDOMIN
R
LOAD
= 37.5
, R
SET
= 73.2
-
600
-
mVp-p
7
Max. Swing (adjusted)
V
SDOMAX
R
LOAD
= 37.5
, R
SET
= 43.2
-
1000
-
mVp-p
1
SD Rise/Fall Times
t
r
, t
f
20% - 80%
400
-
700
ps
7
SD Overshoot/Undershoot
-
-
7
%
1
7
Output Return Loss
O
RL
at 540MHz
15
-
-
dB
1
7
Lock Time
t
LOCK
Worst case
-
-
5
ms
6
Min. Loop Bandwidth
BW
MIN
270Mb/s
LBWC = Grounded : BW
MIN
-
220
-
kHz
7
Typical Loop Bandwidth
BW
TYP
270Mb/s
LBWC = Floating :
BW
MIN
-
500
-
kHz
7
Max. Loop Bandwidth
BW
MAX
270Mb/s
LBWC = V
CC
: 10 BW
MIN
-
1.7
-
MHz
7
Intrinsic Jitter (6
)
143Mb/s
LBWC = floating
-
0.07
-
UI
3
177Mb/s
LBWC = V
CC
-
0.07
-
270Mb/s
-
0.08
-
360Mb/s
-
0.09
-
540Mb/s
-
0.11
-
Data & Clock Inputs
(PD[9:0] PCLKIN)
t
SU
Setup Time at 25C
2.5
-
-
ns
3
t
H
Hold Time at 25C
2.0
-
-
ns
3
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for
supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for
supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
NOTES
1. Depends on PCB layout.
10
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PIN CONNECTIONS
GS9032
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
R
VCO+
LF+
V
EE
R
VCO-
LF-
V
CC1
LBWC
NC
SYNC DIS
V
EE
V
EE1
33
32
31
30
29
28
27
26
25
24
23
AUTO/MAN
BYPASS
R
SET1
V
EE
SDO1
SDO1
V
EE
SDO0
SDO0
V
EE
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLKIN
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
V
CC2
V
EE
2
C
OSC
R
SET0
SS1
SS2
SDO1 ENABLE
LOCK DET
V
EE3
SSO
V
CC3
RESET
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
1-10
PD9 - PD0
I
CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is the MSB.
11
PCLKIN
I
CMOS or TTL compatible parallel clock input.
12
V
EE3
-
Most negative power supply connection for parallel data and clock inputs.
13
V
CC3
-
Most positive power supply connection for parallel data and clock inputs.
14
C
OSC
I
Master Timer Capacitor. A capacitor should be added to decrease the system clock
frequency when an external capacitor is used across LF+ and LF- (NC if not used).
15, 16, 21
SS2, SS1, SS0
I
Data rate selection when in manual mode. These pins are not used in auto mode.
17
V
CC2
-
Most positive power supply connection for internal logic and digital circuits.
18
V
EE2
-
Most negative power supply connection for internal logic and digital circuits.
19
SDO1 ENABLE
I
Enable pin for the secondary cable driver (SDO1 and SDO1). Connect to most negative
power supply to enable. Leave open to disable (do NOT connect to V
CC
).
20
LOCK DET
O
TTL level which is high when the internal PLL is locked.
22
R
SET0
I
External resistor used to set the data output amplitude for SDO0 and SDO0.
23, 26, 29
V
EE
-
Most negative power supply connection for shielding (not connected).
24, 25
SDO0, SDO0
O
Primary, current mode, 75
cable driving output (inverse and true)
27, 28
SDO1, SDO1
O
Secondary, current mode, 75
cable driving output (inverse and true)
30
R
SET1
I
External resistor used to set the data output amplitude for SDO1 and SDO1.
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TYPICAL PERFORMANCE CURVES (V
S
= 5V, T
A
= 25C unless otherwise shown. Guard band tested to 70C only.)
Fig. 1 Rise/Fall Times vs. Temperature
Fig. 2 Supply Current vs. Temperature (SDO0 & SDO1 ON)
31
BYPASS
I
When high, the SMPTE Scrambler and NRZ encoder are bypassed.
32
AUTO/MAN
I
Autostandard or manual mode selectable operation.
33
RESET
I
Resets the scrambler when asserted.
34
V
CC1
-
Most positive power supply connection for analog circuits.
35
V
EE1
-
Most negative power supply connection for analog circuits.
36, 38
R
VCO
+, R
VCO
-
I
Differential VCO current setting resistor that sets the VCO frequency.
37
NC
I
No Connect.
39, 43
V
EE
-
Most negative power supply connection (substrate).
40
LBWC
I
TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest
jitter. If the pin is set to ground the loop bandwidth is BW
MIN
. If the pin is left floating, the
loop bandwidth is approximately 3 BW
MIN
, if the pin is tied to V
CC
the loop bandwidth is
approximately10 BW
MIN
41, 42
LF+, LF-
I
Differential loop filter pins to optimize loop transfer performance at low loop bandwidths
(NC if not used).
44
SYNC DIS
I
Sync detect disable. Logic high disables sync detection. Logic low allows 8 bit operation
by mapping 000-003 to 000 and 3FC-3FF to 3FF.
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
5.25 FALL
4.75 RISE
5.0 RISE
5.0 FALL
5.25 RISE
4.75 FALL
0
20
40
60
80
500
490
480
470
460
450
440
430
420
RISE / FALL TIME (ps)
TEMPERATURE (C)
4.75
5.0
5.25
0
20
40
60
80
155
150
145
140
135
130
125
CURRENT (mA)
TEMPERATURE (C)
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