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GS9090A GenLINX III
270Mb/s Deserializer for SDI
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
1 of 69
Key Features
SMPTE 259M-C compliant descrambling and NRZI
to NRZ decoding (with bypass)
DVB-ASI sync word detection and 8b/10b decoding
Integrated line-based FIFO for data
alignment/delay, clock phase interchange, DVB-ASI
data packet extraction and clock rate interchange,
and ancillary data packet extraction
Integrated VCO and reclocker
Automatic or manual selection between SMPTE
video and DVB-ASI data
Single serial digital input buffer with wide input
sensitivity and common mode point
User selectable additional processing features
including:
TRS, ANC data checksum, and EDH CRC error
detection and correction
programmable ANC data detection
illegal code remapping
Internal flywheel for noise immune H, V, F
extraction
Automatic standards detection and indication
Enhanced Gennum Serial Peripheral Interface
(GSPI)
JTAG test interface
Polarity insensitive for DVB-ASI and SMPTE
signals
+1.8V core power supply with optional +1.8V or
+3.3V I/O power supply
Small footprint (8mm x 8mm)
Low power operation (typically 145mW)
Pb-free and RoHS compliant
Applications
SMPTE 259M-C Serial Digital Interfaces
DVB-ASI Serial Digital Interfaces
Description
The GS9090A is a 270Mb/s reclocking deserializer with
an internal FIFO. When used in conjunction with one of
Gennum's SDI Cable Equalizers, a receive solution for
SD-SDI and DVB-ASI applications can be realized.
In addition to reclocking and deserializing the input data
stream, the GS9090A performs NRZI-to-NRZ decoding,
descrambling as per SMPTE 259M-C, and word
alignment when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will word align
the data to K28.5 sync characters and 8b/10b decode
the received stream.
The integrated reclocker features a very wide Input
Jitter Tolerance, and is fully compatible with both
SMPTE and DVB-ASI input streams.
The GS9090A includes a range of data processing
functions such as error detection and correction,
automatic standards detection, and EDH support. The
device can also detect and extract SMPTE 352M
payload identifier packets and independently identify
the received video standard. This information is read
from internal registers via the host interface port.
TRS errors, EDH CRC errors, and ancillary data
checksum errors can all be detected and corrected. A
single DATA_ERROR pin is provided which is an
inverted logical 'OR'ing of all detectable errors.
Individual error status is stored in internal
`ERROR_STATUS' registers.
The GS9090A also incorporates a video line-based
FIFO. This FIFO may be used in four user-selectable
modes to carry out tasks such as data alignment / delay,
clock phase interchange, MPEG packet extraction and
clock rate interchange, and ancillary data packet
extraction.
Parallel data outputs are provided in 10-bit multiplexed
format, with the associated parallel clock output signal
operating at 27MHz.
The GS9090A is Pb-free, and the encapsulation
compound does not contain halogenated flame
retardant (RoHS compliant).
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
3 of 69
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out .....................................................................................................................5
1.1 Pin Assignment ...............................................................................................5
1.2 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics........................................................................................12
2.1 Absolute Maximum Ratings ..........................................................................12
2.2 DC Electrical Characteristics ........................................................................12
2.3 AC Electrical Characteristics.........................................................................13
2.4 Solder Reflow Profiles...................................................................................15
2.5 Host Interface Map........................................................................................16
2.5.1 Host Interface Map (R/W registers) ....................................................17
2.5.2 Host Interface Map (Read only registers) ...........................................18
3. Detailed Description ...............................................................................................19
3.1 Functional Overview .....................................................................................19
3.2 Serial Digital Input.........................................................................................20
3.3 Clock and Data Recovery .............................................................................20
3.3.1 Internal VCO and Phase Detector ......................................................20
3.4 Serial-To-Parallel Conversion .......................................................................20
3.5 Modes Of Operation......................................................................................20
3.5.1 Lock Detect.........................................................................................21
3.5.2 Auto Mode ..........................................................................................23
3.5.3 Manual Mode ......................................................................................24
3.6 SMPTE Functionality ....................................................................................24
3.6.1 SMPTE Descrambling and Word Alignment.......................................24
3.6.2 Internal Flywheel.................................................................................25
3.6.3 Switch Line Lock Handling..................................................................25
3.6.4 HVF Timing Signal Generation ...........................................................26
3.7 DVB-ASI Functionality ..................................................................................27
3.7.1 DVB-ASI 8b/10b Decoding .................................................................28
3.7.2 Status Signal Outputs .........................................................................28
3.8 Data-Through functionality............................................................................28
3.9 Additional Processing Features ....................................................................28
3.9.1 FIFO Load Pulse.................................................................................28
3.9.2 Ancillary Data Detection and Indication ..............................................29
3.9.3 EDH Packet Detection ........................................................................31
3.9.4 EDH Flag Detection ............................................................................32
3.9.5 SMPTE 352M Payload Identifier.........................................................35
3.9.6 Automatic Video Standard and Data Format Detection......................36
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
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3.9.7 Error Detection and Indication ............................................................37
3.9.8 Error Correction and Insertion ............................................................42
3.10 Internal FIFO Operation ..............................................................................45
3.10.1 Video Mode.......................................................................................45
3.10.2 DVB-ASI Mode .................................................................................47
3.10.3 Ancillary Data Extraction Mode.........................................................49
3.10.4 Bypass Mode ....................................................................................53
3.11 Parallel Data Outputs..................................................................................54
3.11.1 Parallel Data Bus ..............................................................................54
3.11.2 Parallel Output in SMPTE Mode.......................................................55
3.11.3 Parallel Output in DVB-ASI Mode.....................................................55
3.11.4 Parallel Output in Data-Through Mode .............................................55
3.12 Programmable Multi-Function Outputs .......................................................55
3.13 Low-latency Mode.......................................................................................57
3.14 GSPI Host Interface ....................................................................................58
3.14.1 Command Word Description.............................................................59
3.14.2 Data Read and Write Timing ............................................................59
3.14.3 Configuration and Status Registers ..................................................61
3.15 Reset Operation..........................................................................................62
3.16 JTAG Operation ..........................................................................................62
3.17 Device Power Up ........................................................................................63
4. References & Relevant Standards.........................................................................64
5. Application Information...........................................................................................65
5.1 Typical Application Circuit (Part A) ...............................................................65
5.2 Typical Application Circuit (Part B) ...............................................................66
6. Package & Ordering Information............................................................................67
6.1 Package Dimensions ....................................................................................67
6.2 Recommended PCB Footprint ......................................................................68
6.3 Packaging Data.............................................................................................68
6.4 Ordering Information .....................................................................................68
7. Revision History .....................................................................................................69
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