GLT5160L16

ADVANCED

16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM

EATURES

u Single 3.3 V ±0.3 V power supply

u Clock frequency 100 MHz / 125 MHz / 143 MHz/

166 MHz

u Fully synchronous operation referenced to clock rising edge

u Dual bank operation controlled by BA (Bank Address)

u CAS latency- 2 / 3 (programmable)

u Burst length- 1 / 2 / 4 / 8 & Full Page (programmable)

u Burst type- sequential / interleave (programmable)

u Industrial grade available

u Byte control by DQMU and DQML

u Column access - random

u Auto precharge / All bank precharge controlled by A[10]

u Auto refresh and Self refresh

u 4096 refresh cycles / 64 ms

u LVTTL Interface

u 400-mil, 50-Pin Thin Small Outline Package (TSOP II) with

0.8 mm lead pitch

u 60-Ball, 6.4mmx10.1mm VFBGA package with 0.65mm Ball

pitch & 0.35mm Ball diameter.

ENERAL

ESCRIPTION

The GLT5160L16 is a 2-bank x 524288-word x 16-bit Syn-
chronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The

GLT5160L16 achieves very high speed data rate up to 166
MHz, and is suitable for main memory or graphic memory in
computer systems.

May. 2003 (Rev.2.4)

G-LINK Technology

May. 2003 (Rev. 2.4)

UNCTIONAL

LOCK

IAGRAM

A[10:0]

DQ[15:0]

Figure 1. 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM

t
r
o

l

C

i
r
c
u

i
t
r
y

Address Buffer

CLK

CKE

RAS

Clock Buffer

Control

Signal Buffer

CAS

DQML

DQMU

Mode

Memory Array

Bank #0

Memory Array

Bank #1

I/O Buffer

Signal Description

Signal

Type

Description

CLK

Input

Master Clock: All other inputs are referenced to the rising edge of CLK.

CKE

Input

Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased.
CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.

Input

Chip Select: When CS is high, any command means No Operation.

RAS, CAS, WE

Input

Combination of RAS, CAS, WE defines basic commands.

A[10:0]

Input

A[10:0] specify the Row / Column Address in conjunction with BA. The Row Address is specified by A[10:0].
The Column Address is specified by A[7:0]. A[10] is also used to indicate precharge option. When A[10] is
high at a read / write command, an auto precharge is performed. When A[10] is high at a precharge command,
both banks are precharged.

Input

Bank Address: BA is not simply A[11]. BA specifies the bank to which a command is applied. BA must be set
with ACT, PRE, READ, WRITE commands.

DQ[15:0]

Input / Output

Data In and Data out are referenced to the rising edge of CLK.

DQML

Input

Lower Din[7:0] Mask / Lower Output[7:0] Disable: When DQML is high in burst write, lower Din[7:0] for the
current cycle is masked. When DQML is high in burst read, lower Dout[7:0] is disabled at the next but one
cycle.

DQMU

Input

Upper Din[15:8] Mask / Upper Output[15:8] Disable: When DQMU is high in burst write, upper Din(8-15) for
the current cycle is masked. When DQMU is high in burst read, upper Dout[15:8] is disabled at the next but
one cycle.

, V

Power Supply

Power Supply for the memory array and peripheral circuitry.

DDQ

, V

SSQ

Power Supply

DDQ

and V

SSQ

are supplied to the Output Buffers only.

G-LINK Technology

May. 2003 (Rev.2.4)

UNCTIONAL

ESCRIPTION

The GLT5160L16 provides basic functions, bank (row) activate,

burst read / write, bank (row) precharge, and auto / self refresh.

Each command is defined by control signals of RAS, CAS and WE

at CLK rising edge. In addition to 3 signals, CS, CKE and A[10] are

used as chip select, refresh option, and precharge option,

respectively.

To know the detailed definition of commands, please see the com-

mand truth table.

Activate (ACT) [RAS = L, CAS = WE = H]

ACT command activates a row in an idle bank indicated by BA.

Read (READ) [RAS = H, CAS = L, WE = H]

READ command starts burst read from the active bank indicated by

BA. First output data appears after CAS latency. When A[10] = H at

this command, the bank is deactivated after the burst read (auto-pre-

charge, READA).

Write (WRITE) [RAS = H, CAS =WE = L]

WRITE command starts burst write to the active bank indicated by

BA. Total data length to be written is set by burst length. When

A[10] = H at this command, the bank is deactivated after the burst

write (auto-precharge, WRITEA).

Precharge (PRE)
[RAS = L, CAS = H, WE = L]

PRE command deactivates the active bank indicated by BA. This

command also terminates burst read / write operation. When A[10]

= H at this command, both banks are deactivated (precharge all,

PREA).

Auto-Refresh (REFA)
[RAS = CAS = L, WE = CKE = H]

REFA command starts auto-refresh cycle. Refresh address includ-

ing bank address are generated internally. After this command, the

banks are precharged automatically. Any other command should

not be asserted until t

is met.

CLK

RAS

CAS

CKE

A[10]

Chip Select: L=select, h=deselect

Com-

Define Basic Com-

Refresh option @refresh command

Precharge Option @ precharge or read/write
command

Command Truth Table

[1]

Command

Mnemonic

CKE n-

CKE n

RAS

CAS

A[10

]

A[9:

Deselect

DESEL

No Operation

NOP

Row Address Entry & Bank Activate

ACT

Single Bank Precharge

PRE

Precharge All Banks

PREA

Column Address Entry & Write

WRITE

Column Address Entry & Write with Auto-Precharge

WRITEA

Column Address Entry & Read

READ

Column Address Entry & Read with Auto-Precharge

READA

Auto-Refresh

REFA

Self-Refresh Entry

REFS

Self-Refresh Exit

REFSX

Burst Terminate

TBST

Mode Register Set

MRS

1. H = High Level, L = Low Level, V = Valid, X = Don't Care, n = CLK cycle number

G-LINK Technology

May. 2003 (Rev. 2.4)

Function Truth Table

[1] [2]

Current State

RAS

CAS

Address

[3]

Command

Action

[4]

IDLE

DESEL

NOP

TBST

ILLEGAL

[5]

BA, CA, A[10]

READ / WRITE

ILLEGAL

[5]

BA, RA

ACT

Bank Active, Latch RA

BA, A[10]

PRE / PREA

NOP

[6]

REFA

Auto-Refresh

[7]

Op-Code, Mode-Add

MRS

Mode Register Set

[7]

ROW ACTIVE

DESEL

NOP

TBST

NOP

BA, CA, A[10]

READ / READA

Begin Read, Latch CA, Determine Auto-
Precharge

BA, CA, A[10]

WRITE / WRITEA

Begin Write, Latch CA, Determine Auto-
Precharge

BA, RA

ACT

Bank Active / ILLEGAL

[5]

BA, A[10]

PRE / PREA

Precharge / Precharge All

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

READ

DESEL

NOP (Continue Burst to END)

NOP

NOP (Continue Burst to END)

TBST

Terminate Burst

BA, CA, A[10]

READ / READA

Terminate Burst, Latch CA, Begin New
Read, Determine Auto-Precharge

[8]

BA, CA, A[10]

WRITE / WRITEA

Terminate Burst, Latch CA, Begin Write,
Determine Auto-Precharge

[8]

BA, RA

ACT

Bank Active / ILLEGAL

[5]

BA, A[10]

PRE / PREA

Terminate Burst, Precharge

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

WRITE

DESEL

NOP (Continue Burst to END)

NOP

NOP (Continue Burst to END)

TBST

Terminate Burst

BA, CA, A[10]

READ / READA

Terminate Burst, Latch CA, Begin Read,
Determine Auto-Precharge

[8]

BA, CA, A[10]

WRITE / WRITEA

Terminate Burst, Latch CA, Begin Write,
Determine Auto-Precharge

[8]

BA, RA

ACT

Bank Active / ILLEGAL

[5]

BA, A[10]

PRE / PREA

Terminate Burst, Precharge

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

G-LINK Technology

May. 2003 (Rev.2.4)

READ with AUTO
PRECHARGE

DESEL

NOP (Continue Burst to END)

NOP

NOP (Continue Burst to END)

TBST

ILLEGAL

BA, CA, A[10]

READ / READA

ILLEGAL

BA, CA, A[10]

WRITE / WRITEA

ILLEGAL

BA, RA

ACT

Bank Active / ILLEGAL

[5]

BA, A[10]

PRE / PREA

ILLEGAL

[5]

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

WRITE with AUTO
PRECHARGE

DESEL

NOP (Continue Burst to END)

NOP

NOP (Continue Burst to END)

TBST

ILLEGAL

BA, CA, A[10]

READ / READA

ILLEGAL

BA, CA, A[10]

WRITE / WRITEA

ILLEGAL

BA, RA

ACT

Bank Active / ILLEGAL

[5]

BA, A[10]

PRE / PREA

ILLEGAL

[5]

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

PRE -CHARGING

DESEL

NOP (Idle after t

)

NOP

NOP (Idle after t

)

TBST

ILLEGAL

[5]

BA, CA, A[10]

READ / WRITE

ILLEGAL

[5]

BA, RA

ACT

ILLEGAL

[5]

BA, A[10]

PRE / PREA

NOP

[6]

(Idle after t

)

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

ROW ACTIVATING

DESEL

NOP (Row Active after t

RCD

)

NOP

NOP (Row Active after t

RCD

)

TBST

ILLEGAL

[5]

BA, CA, A[10]

READ / WRITE

ILLEGAL

[5]

BA, RA

ACT

ILLEGAL

[5]

BA, A[10]

PRE / PREA

ILLEGAL

[5]

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

WRITE RECOVERING

DESEL

NOP

TBST

ILLEGAL

[5]

BA, CA, A[10]

READ / WRITE

ILLEGAL

[5]

BA, RA

ACT

ILLEGAL

[5]

BA, A[10]

PRE / PREA

ILLEGAL

[5]

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

Function Truth Table

[1] [2]

(Continued)

Current State

RAS

CAS

Address

[3]

Command

Action

[4]

G-LINK Technology

May. 2003 (Rev. 2.4)

REFRESHING

DESEL

NOP (Idle after t

)

NOP

NOP (Idle after t

)

TBST

ILLEGAL

BA, CA, A[10]

READ / WRITE

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A[10]

PRE / PREA

ILLEGAL

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

MODE REGISTER
SETTING

DESEL

NOP (Idle after t

RSC

)

NOP

NOP (Idle after t

RSC

)

TBST

ILLEGAL

BA, CA, A[10]

READ / WRITE

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, A[10]

PRE / PREA

ILLEGAL

REFA

ILLEGAL

Op-Code, Mode-Add

MRS

ILLEGAL

1. H = High Level, L= Low Level, X = Don't Care.

2. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

3. BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No OPeration.

4. ILLEGAL = Device operation and/or data-integrity are not guaranteed.

5. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.

6. NOP to bank precharging or in idle state. May precharge bank indicated by BA.

7. ILLEGAL if any bank is not idle.

8. Must satisfy bus contention, bus turn around, write recovery requirements.

Function Truth Table

[1] [2]

(Continued)

Current State

RAS

CAS

Address

[3]

Command

Action

[4]

G-LINK Technology

May. 2003 (Rev.2.4)

Function Truth Table for CKE

[1]

Current State

CKE n-

CKE n

RAS

CAS

Add

Action

SELF-REFRESH

[2]

INVALID

Exit Self-Refresh (Idle after t

)

Exit Self-Refresh (Idle after t

)

ILLEGAL

NOP (Maintain Self-Refresh)

POWER DOWN

INVALID

Exit Power Down to Idle

NOP (Maintain Self-Refresh)

ALL BANKS IDLE

[3]

Refer to Function Truth Table

Enter Self-Refresh

Enter Power Down

ILLEGAL

Refer to Current State = Power Down

ANY STATE other than
listed above

Refer to Function Truth Table

Begin CLK Suspend at Next Cycle

[4]

Exit CLK Suspend at Next Cycle

[4]

Maintain CLK Suspend

1. H = High Level, L= Low Level, X = Don't Care.

2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

3. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.

4. Must be legal command.

G-LINK Technology

May. 2003 (Rev. 2.4)

Power On Sequence

Before starting normal operation, the following power on sequence

is necessary to prevent damage or malfunction.

1. Apply power and start clock. Attempt to maintain CKE high,

DQMU / DQML high and NOP condition at the inputs.

2. Maintain stable power, stable clock, and NOP input condi-

tions for a minimum of 200 µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after t

), issue 2 or more

auto-refresh commands.

5. Issue a mode register set command to initialize the mode

After this sequence, the SDRAM is idle state and ready for normal

operation.

MODE

SET

PRECHARGE

POWER ON

POWER

APPLIED

PRE

SELF

REFRESH

IDLE

AUTO

REFRESH

CLK

SUSPEND

ROW

WRITE

SUSPEND

WRITE

READ

SUSPEND

WRITE A

SUSPEND

WRITE A

READ A

SUSPEND

PRE

CKE

WRITE

READE

WRITE

READE

WRITE

READ

WRITE

READE

WRIT

REA

POWER

DOWN

CKE

ACT

CKE

MRS

REF

REFS

Automatic Sequence

Command Sequence

Figure 2. Simplified State Diagram

TBST

G-LINK Technology

May. 2003 (Rev.2.4)

Mode Register

Burst Length, Burst Type and CAS Latency can be programmed by

setting the mode register (MRS). The mode register stores these

data until the next MRS command, which may be issued when both

banks are in idle state. After t

RSC

from a MRS command, the

SDRAM is ready for new command.

CLK

RAS

CAS

BA, A[10:0]

A10

WBL

LTMODE

CAS

BT = 0

BT = 1

Full Page

SEQUENTIAL

INTERLEAVED

BURST

TYPE

BURST
LENGT

LATENC
Y MODE

Write Burst Length (WBL)

Length

= BL specified

Single bit (BL =

CLK

Command

READ

Address

WRITE

CAS

Burst Length

Burst Type

Initial

Address

B
L

Column Addressing

Sequential

Interleaved

G-LINK Technology

May. 2003 (Rev. 2.4)

PERATIONAL

ESCRIPTION

Bank Activate

The SDRAM has two independent banks. Each bank is activated by

the ACT command with the bank address (BA). A row is indicated

by the row address A[10:0] The minimum activation interval

between one bank and the other bank is t

RRD

Precharge

The PRE command deactivates the bank indicated by BA. When

both banks are active, the precharge all command (PREA, PRE +

A[10] = H) is available to deactivate them at the same time. After

from the precharge, an ACT command can be issued.

CLK

Figure 3. Bank Activation and Precharge All (BL=4, CL=3)

Command

A[9:0]

A[10]

ACT

REA

PRE

ACT

Qa2

Qa1

Qa0

Qa3

Precharge All

RRD

RAS

G-LINK Technology

May. 2003 (Rev.2.4)

Read

After t

RCD

from the bank activation, a READ command can be

issued. 1st output data is available after the CAS Latency from the

READ, followed by (BL-1) consecutive data when the Burst Length

is BL. The start address is specified by A[7:0], and the address

sequence of burst data is defined by the Burst Type. A READ com-

mand may be applied to any active bank, so the row precharge time

) can be hidden behind continuous output data (in case of BL =

4) by interleaving the dual banks. When A[10] is high at a READ

command, the auto-precharge (READA) is performed. Any com-

mand (READ, WRITE, PRE, ACT) to the same bank is inhibited till

the internal precharge is complete. The internal precharge start tim-

ing depends on CAS Latency. The next ACT command can be

issued after t

from the internal precharge timing.

CLK

Figure 4. Dual Bank Interleaving READ (BL=4, CL=3)

Command

A[9:0]

A[10]

ACT

REA

ACT

PRE

Qa2

Qa1

Qa0

Qa3

REA

Qb0

Qb1

Qb2

RCD

CAS Latency

Burst Length

CLK

Figure 5. READ with Auto-Precharge (BL=4, CL=3)

Command

A[9:0]

A[10]

ACT

READ A

ACT

Qa2

Qa1

Qa0

Qa3

RCD

Internal Precharge begins

CLK

Figure 6. READ Auto-Precharge Timing (BL=4)

Command

CL=3 DQ

CL=2 DQ

ACT

READ A

Internal Precharge Start Timing

Qa2

Qa1

Qa0

Qa3

Qa2

Qa1

Qa0

Qa3

G-LINK Technology

May. 2003 (Rev. 2.4)

Write

After t

RCD

from the bank activation, a WRITE command can be

issued. 1st input data is set at the same cycle as the WRITE. Follow-

ing (BL-1) data are written into the RAM, when the Burst Length is

BL. The start address is specified by A[7:0], and the address

sequence of burst data is defined by the Burst Type. A WRITE com-

mand may be applied to any active bank, so the row precharge time

) can be hidden behind continuous input data (in case of BL = 4)

by interleaving the dual banks. From the last input data to the PRE

command, the write recovery time (t

RDL

) is required. When A[10]

is high at a WRITE command, the auto-precharge (WRITEA) is

performed. Any command (READ, WRITE, PRE, ACT) to the

same bank is inhibited till the internal precharge is complete. The

internal precharge begins at t

after the last input data cycle. The

next ACT command can be issued after t

from the internal pre-

charge timing.

CLK

Figure 7. Dual Bank Interleaving WRITE (BL=4)

Command

A[9:0]

A[10]

RCD

Burst Length

RDL

Da2

Da1

Da0

Da3

ACT

WRITE

ACT

PRE

WRITE

Db1

Db0

Db3

Db2

CLK

Figure 8. WRITE with Auto-Precharge (BL=4)

Command

A[9:0]

A[10]

Internal Precharge Begins

RCD

RDL

Da2

Da1

Da0

Da3

ACT

WRITE

ACT

G-LINK Technology

May. 2003 (Rev.2.4)

Burst Interruption

[Read Interrupted by Read]

The burst read operation can be interrupted by a new read of the

same or the other bank. GLT5160L16 allows random column

access. READ to READ interval is 1 CLK minimum.

[Read Interrupted by Write]

Burst read operation can be interrupted by write of the same or the

other bank. Random column access is allowed. In this case, the DQ

should be controlled adequately by using the DQMU / DQML to

prevent the bus contention. The output is disabled automatically 2

cycles after WRITE assertion.

CLK

Figure 9. READ Interrupted by READ (BL=4, CL=3)

Command

A[9:0]

A[10]

Internal Precharge Start Timing

Qj1

Qj0

Qi0

Qk0

REA

READ

Qk2

Qk1

Ql1

Ql0

REA

Ql2

Ql3

CLK

Command

A[9:0]

A[10]

DQMU,

Figure 10. READ Interrupted by WRITE (BL=4, CL=3)

Dj0

Qi0

Dj1

REA

Dj3

Dj2

WRITE

DQM U/ DQML control

Write control

G-LINK Technology

May. 2003 (Rev. 2.4)

[Read Interrupted by Precharge]

Burst read operation can be interrupted by precharge of the same

bank. READ to PRE interval is minimum 1 CLK. A PRE command

disables the data output, depending on the CAS Latency. The figure

below shows examples, when the data-out is terminated.

Figure 11. READ Interrupted by Precharge (BL=4)

CLK

Command

CL=2

CL=3

Q 0

REA

PRE

REA

PRE

REA

PRE

REA

PRE

REA

PRE

REA

PRE

Q 0

Q 1

Q 2

Q 3

Q 0

Q 1

Q 2

Q 0

Q 1

Q 2

Q 3

Q 0

Q 1

Q 2

G-LINK Technology

May. 2003 (Rev.2.4)

[Read Interrupted by Burst Terminate]

Similarly to the precharge, burst terminate command can interrupt

burst read operation and disable the data output. READ to TBST

interval is minimum 1 CLK. The figure below shows examples,

when the data-out is terminated.

CLK

Command

Figure 12. READ Interrupted by Burst Terminate (BL=4)

Command

CL=2

CL=3

Q 0

REA

TBST

Q 1

Q 2

Q 3

REA

TBST

Q 0

Q 1

Q 2

REA

Q 0

TBST

Q 0

Q 1

Q 2

Q 3

Q 0

Q 1

Q 2

Q 0

REA

TBST

REA

TBST

REA

TBST

G-LINK Technology

May. 2003 (Rev. 2.4)

[Write Interrupted by Write]

Burst write operation can be interrupted by new write of the same or

the other bank. Random column access is allowed. WRITE to

WRITE interval is minimum 1 CLK.

[Write Interrupted by Read]

Burst write operation can be interrupted by read of the same or the

other bank. Random column access is allowed. WRITE to READ

interval is minimum 1 CLK. The input data on DQ at the interrupt-

ing READ cycle is "don't care". Using the DQMU / DQML to

prevent the bus contention is optional.

CLK

Command

A[9:0]

A[10]

Figure 13. WRITE Interrupted by WRITE (BL=4)

Dj1

Dj0

Di0

Dk0

WRIT

Dk2

Dk1

Dl1

Dl0

Dl2

Dl3

WRIT

WRITE

CLK

Command

Figure 14. WRITE interrupted by READ (BL=4, CL=3)

A[9:0]

A[10]

DQMU,

WRITE

READ

Di0

Qj1

Qj0

Dk0

Dk1

WRITE

READ

Ql0

G-LINK Technology

May. 2003 (Rev.2.4)

[Write Interrupted by Precharge]

Burst write operation can be interrupted by precharge of the same

bank. Random column access is allowed. Because the write recov-

ery time (t

RDL

) is required between the last input data and the next

PRE, 3rd data should be masked with DQMU / DQML shown as

below.

[Write Interrupted by Burst Terminate]

Burst terminate command can terminate burst write operation. In

this case, the write recovery time is not required and the bank

remains active. The figure below shows the case 3 words of data are

written. Random column access is allowed. WRITE to TBST inter-

val is minimum 1 CLK.

CLK

Command

Figure 15. WRITE Interrupted by Precharge (BL=4)

A[9:0]

A[10]

DQMU,

This data should be masked to satisfy t

RDL

requirement.

Di0

WRITE

PRE

ACT

Di1

CLK

Command

Figure 16. WRITE Interrupted by Burst Terminate (BL=4)

A[9:0]

A[10]

DQMU,

Da0

WRITE

TBST

Da1

Da2

G-LINK Technology

May. 2003 (Rev. 2.4)

Auto Refresh

Single cycle of auto-refresh is initiated with a REFA (CS = RAS =

CAS = L, WE = CKE = H) command. The refresh address is gener-

ated internally. 4096 REFA cycles within 64 ms refresh 16 Mbit

memory cells. The auto-refresh is performed on each bank alter-

nately (ping-pong refresh). Before performing an auto-refresh, both

banks must be in the idle state. Additional commands must not be

supplied to the device before t

from the REFA command.

Self Refresh

Self-refresh mode is entered by issuing a REFS command (CS =

RAS = CAS = L, WE = H, CKE = L). Once the self-refresh is initi-

ated, it is maintained as long as CKE is kept low. During the self-

refresh mode, CKE is asynchronous and the only enabled input (but

asynchronous), all other inputs including CLK are disabled and

ignored, and power consumption due to synchronous inputs is

saved. To exit the self-refresh, supplying stable CLK inputs, assert-

ing DESEL or NOP command and then asserting CKE (REFSX).

After t

from REFSX both banks are in the idle state and a new

command can be issued after t

, but DESEL or NOP commands

must be asserted till then.

CLK

A[10:0]

Figure 17. Auto Refresh

RAS

CAS

CKE

NOP or Deselect

Minimum t

Auto Refresh on Bank 0

Auto Refresh on Bank 1

minimum t

for recovery

CLK

A[10:0]

Figure 18. Self-Refresh

RAS

CAS

CKE

Stable CLK

Self Refresh Entry

Self Refresh Exit

NOP

new command

G-LINK Technology

May. 2003 (Rev.2.4)

CLK Suspend

CKE controls the internal CLK at the following cycle. Figure 19

and Figure 20 show how CKE works. By negating CKE, the next

internal CLK is suspended. The purpose of CLK suspend is power

down, output suspend or input suspend. CKE is a synchronous input

except during the self-refresh mode. CLK suspend can be per-

formed either when the banks are active or idle, but a command at

the following cycle is ignored.

ext. CLK

CKE

int. CLK

CLK

CKE

Figure 19. Power Down by CKE

Command

CKE

Command

Standby Power Down

Active Power Down

NOP

PRE

NOP

ACT

NOP

CLK

CKE

Figure 20. DQ Suspend by CKE

Command

WRITE

REA

G-LINK Technology

May. 2003 (Rev. 2.4)

DQMU / DQML Control

DQMU / DQML is a dual function signal defined as the data mask

for writes and the output disable for reads. During writes, DQMU /

DQML masks upper / lower input data word by word. DQMU /

DQML to write mask latency is 0. During reads, DQMU / DQML

forces upper / lower output to Hi-Z word by word. DQMU / DQML

to output Hi-Z latency is 2.

CLK

Command

Figure 21. DQMU / DQML Function

DQ[7:0]

DQMU

DQ[15:8]

DQML

Masked by DQML =

Masked by DQMU =

Disabled by DQMU

Disabled by DQML =

WRITE

REA

G-LINK Technology

May. 2003 (Rev.2.4)

LECTRICAL

PECIFICATIONS

Absolute Maximum Ratings

[1]

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

Symbol

Parameter

Conditions

Ratings

Unit

Supply Voltage

with respect to V

-1.0 to 4.6

DDQ

Supply Voltage for Output

with respect to V

SSQ

-1.0 to 4.6

Input Voltage

with respect to V

-1.0 to 4.6

Output Voltage

with respect to V

SSQ

-1.0 to 4.6

Output Current

Power Dissipation

= 25 °C

1000

OPR

Operating Temperature

comsumer

0 to 70

°C

Industrial

-40 to 85

°C

STG

Storage Temperature

-65 to 150

°C

Recommended Operating Conditions (T

= 0 to +70°C, unless otherwise noted)

Symbol

Parameter

Min

Typ

Max

Unit

Supply Voltage

3.0

3.3

3.6

DDQ

Supply Voltage for Output

3.0

3.3

3.6

[1]

High-Level Input Voltage all inputs

2.0

DDQ

+ 0.3

[2]

Low-Level Input Voltage all inputs

-0.3

0.8

1. V

(max) = 5.6 V for pulse width less than 3 ns.

2. V

(min) = -2.0 V for pulse width less than 3 ns.

DC Characteristics (T

= 0 to +70°C, V

= V

DDQ

= 3.3 ±0.3V, V

= V

SSQ

= 0 V, unless otherwise noted)

Symbol

Parameter

Test Conditions

Min

Max

Unit

High-Level Output Voltage

= -2 mA

2.4

Low-Level Output Voltage

= 2 mA

0.4

Off-state Output Current

Q floating V

= 0 to V

DDQ

-10

µA

Input Current

= 0 to V

DDQ

+ 0.3 V

-10

µA

Capacitance (T

= 0 to +70°C, V

= V

DDQ

= 3.3 ±0.3 V, V

= V

SSQ

= 0 V, unless otherwise noted)

Symbol

Parameter

Test Condition

Min

Max

Unit

I(A)

Input Capacitance, address pin

= V

f = 1 MHz

= 25 mVrms

2.5

I(C)

Input Capacitance, control pin

2.5

I(K)

Input Capacitance, CLK pin

2.5

I/O

Input Capacitance, I/O pin

G-LINK Technology

May. 2003 (Rev. 2.4)

Average Supply Current from V

= 0 to +70°C, V

= V

DDQ

= 3.3 ±0.3 V, V

= V

SSQ

= 0 V, unless otherwise noted)

Symbol

Parameter

Test Conditions

Rating (Max)

Unit

-6

-7

-8

-10

CC1S

Operating Current, Single Bank

= min, t

CLK

= min, BL = 1, CL = 3

120

110

100

CC1D

Operating Current, Dual Bank

= min, t

CLK

= min, BL = 1, CL = 3

170

150

140

120

CC2H

Standby Current, CKE = H

both banks idle, t

CLK

= min, CKE = H

CC2L

Standby Current, CKE = L

both banks idle, t

CLK

= min, CKE = L

CC3H

Active Standby Current, CKE = H

both banks active, t

CLK

= min, CKE = H

CC3L

Active Standby Current, CKE = L

both banks active, t

CLK

= min, CKE = L

CC4

Burst Current

CLK

= min, BL = 4, CL = 3, both banks

active

180

170

160

140

CC5

Auto-Refresh Current

= min, t

CLK

= min

110

100

CC6

Self-Refresh Current

CKE < 0.2 V

Low Power

500

µA

AC Characteristics (T

= 0 to +70°C, V

= V

DDQ

= 3.3 ±0.3 V, V

= V

SSQ

= 0 V, unless otherwise noted)

[1]

Symbol

Parameter

-6

-7

-8

-10

Unit

Min

Max

Min

Max

Min

Max

Min

Max

CLK

CLK Cycle Time

CL=2

CL=3

CLK High Pulse Width

2.5

3.5

CLK Low Pulse Width

2.5

3.5

Transition Time of CLK

Input Setup Time (all inputs)

2.5

Input Hold Time (all inputs)

Row Cycle Time

RCD

Row to Column Delay

RAS

Row Active Time

100k

Row Precharge Time

CCD

Column Address to Column Adress Delay

CLK

RRD

Act to Act Delay Time

CLK

RSC

Mode Register Set Cycle Time

CLK

RDL

Last Data-In to Row Precharge Delay

CLK

REF

Refresh Interval Time

65.6

1. Input Pulse Levels: 0.4 V to 2.4 V with t

= +1/+1 ns. Input Timing Measurement Level: 1.4 V.

1.4

CLK

Signal

1.4

Any AC timing is
referenced to the
input signal crossing

G-LINK Technology

May. 2003 (Rev.2.4)

Switching Characteristics (T

= 0 to +70°C, V

= V

DDQ

= 3.3 ±0.3 V, V

= V

SSQ

= 0 V unless otherwise

noted)

Symbol

Parameter

-6

-7

-8

-10

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Access Time from

CL=2

CL=3

5.5

Output Hold Time from CLK

2.5

OLZ

Delay Time, Output Low Impedance from
CLK

OHZ

Delay Time, Output High Imped-
ance from CLK

CL=2

CL=3

5.5

1.4

CLK

1.4

Output Timing Measurement Reference Point

1.4

CLK

1.4

REF

= 1.4V

OUT

50 pF

(1)

Figure 22. Output Load Condition

1. For GLT5160L16-6/7, the Output Load is 30

OHZ

OLZ

G-LINK Technology

May. 2003 (Rev.2.4)

ACKAGING

NFORMATION

Figure 38. 50-Pin 400 mil TSOP II Pin Assignment

DQ0

SSQ

DQ2

DQ3

DDQ

DQ4

DQ5

SSQ

DQ6

DQML

CAS

RAS

A10

DDQ

DQ11

DQ10

SSQ

DQ9

DQ8

DDQ

DQMU

CLK

Top View

DQ7

DDQ

CKE

DQ12

DQ13

SSQ

DQ14

DQ15

DQ1

VSS

DQ14

DQ13

DQ12

DQ10

DQ9

DQ8

CKE

A11

VSS

VSSQ

DQ15

VSSQ

VDDQ

DQ11

VSSQ

VDDQ

UDQM

CLK

DQ0

VDDQ

VSSQ

DQ4

VDDQ

LDQM

RAS#

VDD

DQ1

DQ2

DQ3

DQ5

DQ6

DQ7

WE#

CAS#

CS#

A10

VDD

Figure 38-1. 60-Ball VFBGA Ball

G-LINK Technology

May. 2003 (Rev. 2.4)

RDERING

NFO

GLT5160L16

Part Number

Mode

Cycle Time

Max Frequency

Interface

Package

GLT5160L16-10TC

Synchronous

100 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16-8TC

Synchronous

125 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16-7TC

Synchronous

143 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16-6TC

Synchronous

166 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16-10FJ

Synchronous

100 MHz

LVTTL

60-Ball VFBGA

GLT5160L16-8FJ

Synchronous

125 MHz

LVTTL

60-Ball VFBGA

GLT5160L16-7FJ

Synchronous

143 MHz

LVTTL

60-Ball VFBGA

GLT5160L16-6FJ

Synchronous

166 MHz

LVTTL

60-Ball VFBGA

GLT5160L16I-10TC

Synchronous

100 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16I-8TC

Synchronous

125 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16I-7TC

Synchronous

143 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16I-6TC

Synchronous

166 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16I-10FJ

Synchronous

100 MHz

LVTTL

60-Ball VFBGA

GLT5160L16I-8FJ

Synchronous

125 MHz

LVTTL

60-Ball VFBGA

GLT5160L16I-7FJ

Synchronous

143 MHz

LVTTL

60-Ball VFBGA

GLT5160L16I-6FJ

Synchronous

166 MHz

LVTTL

60-Ball VFBGA

GLT5160L16P-10TC

Synchronous

100 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16P-8TC

Synchronous

125 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16P-7TC

Synchronous

143 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16P-6TC

Synchronous

166 MHz

LVTTL

50-Pin 400 mil Plastic TSOP II

GLT5160L16P-10FJ

Synchronous

100 MHz

LVTTL

60-Ball VFBGA

GLT5160L16P-8FJ

Synchronous

125 MHz

LVTTL

60-Ball VFBGA

GLT5160L16P-7FJ

Synchronous

143 MHz

LVTTL

60-Ball VFBGA

GLT5160L16P-6FJ

Synchronous

166 MHz

LVTTL

60-Ball VFBGA

G-LINK Technology

May. 2003 (Rev.2.4)

Parts Numbers (Top Mark) Definition for SDRAM and SGRAM :

GLT 5 160 L 16 - 7 TC

5 : Synchronous
DRAM
9 : SGRAM

DENSITY

40 : 4M
160 : 16M
320 : 32M,4Bank
640 : 64M
1280 : 128M

VOLTAGE

Blank : 5V
L : 3.3V
M : 2.5V
N : 2.0V

CONFIG.

04 : x04
08 : x08
16 : x16
32 : x32

SPEED

SDRAM :
5 : 5ns/200 MHZ
5.5 : 5.5ns/183 MHZ
6 : 6ns/166 MHZ
7 : 7ns/143 MHZ
8 : 8ns/125 MHZ
10 : 10ns/100 MHZ

PACKAGE

TS : TSOP(Type I)
ST : sTSOP(Type I)
TC : TSOPll
TQ : TQFP
FJ : 60Ball VFBGA

Temperature Range

E : Extended Temperature
I : Industrial Temperature
Blank : Commercial Temperature

Environmental Option

P : Pbfree part

POWER

Blank : Standard
L : Low Power
LL : Low Low Power

Circuit diagrams utilizing G-LINK products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for design purposes is not necessarily given.

G-LINK Technology reserves the right to change products or specifications without notice.

The information contained in this document does not convey any license under copyrights, patent rights or trademarks claimed and owned by G-LINK or its subsidiaries. G-LINK assumes no liability for
G-LINK applications assistance, customer's product design, or infringement of patents arising from use of semiconductor devices in such systems' designs. Nor does G-LINK warrant or represent that any
patent right, copyright, or other intellectual property right of G-LINK covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used.

G-LINK Technology's products are not authorized for use in life support devices or systems. Life support devices or systems are device or systems which are: a) intended for surgical implant into the human
body and b) designed to support or sustain life; and when properly used according to label instructions, can reasonably be expected to cause significant injury to the user in the event of failure.

The information contained in this document is believed to be entirely accurate. However, G-LINK Technology assumes no responsibility for inaccuracies.

G-LINK Technology Corporation, Taiwan

www.glink.com.tw

sales@glink.com.tw

TEL: 886-2-2659-9658

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