G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features :
Description :
Low-power consumption.
-Active: 30mA Icc at 120ns.
-Stand by :
20
A (CMOS input / output , LL)
5
A (CMOS input / output, SL)
Single +2.3V to 2.7V Power Supply.
Equal access and cycle time.
85/120 ns access time.
Tri-state output.
Automatic power-down when
deselected.
Multiple center power and ground pins
for improved noise immunity.
Individual byte controls for both Read
and Write cycles.
Industrial grade (-40
C ~ 85
C)
available.
Available in 48-fpBGA/44L TSOPII.
CE2 pin available for fpBGA only.
The GLT6400M16 is a low power CMOS Static
RAM organized as 262,144 words by 16 bits. Easy
memory expansion is provided by an active LOW
CE1
and
OE
pin and active HIGH CE2.
This device has an automatic power down
mode feature when deselected. Separate Byte
Enable controls (
BLE
and
BHE
) allow individual
bytes to be accessed.
BLE
controls the lower bits
I/O0 I/O7.
BHE
controls the upper bits I/O8
I/O15.
Writing to these devices is performed by taking
Chip Enable
CE1
with Write Enable
WE
and byte
Enable (
BLE
/
BHE )
Low while CE2 remains
HIGH.
Reading from the device is performed by taking
Chip Enable
CE1
with Output enable
OE
and byte
Enable (
BLE
/
BHE
) Low while Write Enable
WE
and CE2 are held HIGH.
Function Block Diagram :
Row Select
Memory Array
2048 x 2048
Pre-Charge Circuit
I/O Circuit
Column Select
Data
Circuit
Data
Circuit
Vcc
Vss
WE
OE
BLE
BHE
CE1
I/O
8
- I/O
15
I/O
0
- I/O
7
Control
Logic
CE2
Column Address
Row Address
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
BHE
Pin Configurations :
GLT6400M16
A
4
1
2
3
4
5
6
7
9
10
12
13
14
Vcc
8
15
16
17
18
19
20
21
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
CE1
I/O
0
OE
BLE
22
23
34
11
Vcc
WE
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
Vss
I/O
4
I/O
5
I/O
6
I/O
7
A
17
A
16
A
15
A
14
A
11
A
10
A
9
A
8
NC
I/O
8
I/O
9
I/O
10
I/O
11
Vss
I/O
12
I/O
13
I/O
14
I/O
15
BHE
A
7
A6
A
5
A
13
A
12
48 Ball fpBGA :
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
1
BLE
I/O9
I/O10
Vss
Vcc
I/O15
I/O16
NC
2
OE
I/O11
I/O12
I/O13
I/O14
NC
A8
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1 I/O2
I/O4
I/O5
I/O6
WE
A11
6
CE2
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
NC
(Bottom View)
(Bottom View)
Note
:
NC means no Ball.
Pin Descriptions:
Name
Function
A
0
A
17
Address Inputs
CE
1
and CE
2
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O
0
I/O
15
Data Input and Data Output
V
CC
2.5V Power Supply
BLE
Lower Byte Enable Input ( I/O
0
to I/O
7
)
BHE
Higher Byte Enable Input ( I/O
8
to I/O
15
)
GND
Ground
NC
No Connection
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Truth Table:
CE1 CE2
OE WE BLE BHE
I/O0-I/O7
I/O8-I/O15
Power
Mode
H
X
X
X
X
X
High-Z
High-Z
Standby
Deselected
X
L
X
X
X
X
High-Z
High-Z
Standby
Deselected
X
X
X
X
H
H
High-Z
High-Z
Standby
Deselected
L
H
H
H
L
X
High-Z
High-Z
Active
Output Disabled
L
H
H
H
X
L
High-Z
High-Z
Active
Output Disabled
L
H
L
H
L
H
Data Out
High-Z
Active
Lower Byte Read
L
H
L
H
H
L
High-Z
Data Out
Active
Upper Byte Read
L
H
L
H
L
L
Data Out
Data Out
Active
Word Read
L
H
X
L
L
H
Data In
High-Z
Active
Lower Byte Write
L
H
X
L
H
L
High-Z
Data In
Active
Upper Byte Write
L
H
X
L
L
L
Data In
Data In
Active
Word Write
Note ; X means don care. (Must be low or high state).
Absolute Maximum Ratings*
Parameter
Symbol
Minimum
Maximum
Unit
Voltage on Any Pin Relative to Gnd
Vt
-0.5
Vcc + 0.5
V
Power Dissipation
P
T
-
1.0
W
Storage Temperature (Plastic)
Tstg
-55
+150
C
Temperature Under Bias
Tbias
-25
+85
C
*Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any conditions outside those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions ( TA = -25
C to 85
C )
Parameter
Symbol
Min
Typ
Max
Unit
V
CC
2.3
2.5
2.7
V
Supply Voltage
Gnd
0.0
0.0
0.0
V
V
IH
2.0
-
V
CC
+0.2
V
Input Voltage
V
IL
-0.2*
-
0.6
V
* V
IL
min = -2.0V for pulse width less than t
RC
/2.
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
DC Operating Characteristics
( Vcc=2.3 to 2.7V, T
A
= -25
C to 85
C )
85
120
Unit
Parameter
Sym.
Test Conditions
Min
Max
Min
Max
Input Leakage Current
I
LI
V
CC
= Max,
Vin = Gnd to V
CC
-
1
-
1
A
Output Leakage
Current
I
LO
CE
1
=V
IH
or CE2 = V
IH
V
CC
= Max, V
OUT
= Gnd to V
CC
-
1
-
1
A
Operating Power
Supply Current
I
CC
CE
1
=V
IL
,CE2 = V
IH
V
IN
=V
IH
or V
IL
, I
OUT
=0mA
-
5
-
5
mA
I
CC1
CE
1
=V
IL
,CE2 = V
IH
I
OUT
= 0mA,
Min Cycle, 100% Duty
-
45
-
30
mA
Average Operating
Current
I
CC2
CE
1
=0.2V
CE2 = V
CC
0.2V
I
OUT
= 0mA,
Cycle Time=1
s, 100% Duty
-
5
-
5
mA
Standby Power Supply
Current(TTL Level)
I
SB
CE
1
=V
IH
or CE2 = V
IL
-
0.3
-
0.3
mA
GLT6400M16LL
-
20
-
20
A
Standby Power Supply
Current (CMOS Level)
I
SB1
CE
1
V
CC
-
0.2V or
CE2
0.2V, f=0
V
IN
0.2V or
V
IN
V
CC
-0.2V
GLT6400M16SL
-
5
-
5
A
Output Low Voltage
V
OL
I
OL
= 0.5 mA
-
0.4
-
0.4
V
Output High Voltage
V
OH
I
OH
= -0.5 mA
2.0
-
2.0
-
V
Data Retention
Parameter
Sym.
Test Conditions
Min.
Max.
Unit
V
CC
for Data retention
V
DR
1.0
-
V
Data Retention Current
I
CCDR
-
4
A
Chip Deselect to Data Retention Time
t
CDR
0
-
ns
Operating Recovery Time
(2)
t
R
CE1
V
CC
-0.2V
CE2
+0.2V
V
IN
V
CC
-0.2V or
V
IN
0.2V
t
RC
-
ns
Data Retention Waveform
(TA = -25
C to +85
C)
Data Retention Mode
Vcc
CE1
V
DR
V
DR >= 1.0V
t
R
t
CDR
Vcc-typ
Vcc-typ
V
IH
V
IH
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
AC Test Conditions
AC Test Loads and Waveforms
C
L
*
TTL
Output Load Condition
*Including Scope and Jig Capacitance
C
L
= 30pf + 1TTL Load
Read Cycle
(9)
( Vcc=2.3V to 2.7V, T
A
= -25
C to 85
C )
85
120
Unit
Note
Parameter
Symbol
Min
Max
Min
Max
Read Cycle Time
t
RC
85
120
ns
Address Access Time
t
AA
85
120
ns
Chip Enable Access Time
t
ACE
85
120
ns
Output Enable Access Time
t
OE
40
60
ns
Output Hold from address Change
t
OH
10
15
ns
Chip Enable to Output in Low-Z
t
LZ
10
20
ns
4,5
Chip Disable to Output in High-Z
t
HZ
35
0
35
ns
3,4,5
Output Enable to Output in Low-Z
t
OLZ
5
20
ns
Output Disable to Output in High-Z
t
OHZ
30
0
35
ns
BLE , BHE Enable to Output in Low-Z
t
BLZ
5
20
ns
4,5
BLE , BHE Disable to Output in High-Z
t
BHZ
30
0
35
ns
3,4,5
BLE , BHE Access Time
t
BA
40
60
ns
Timing Waveform of Read Cycle 1 (Address Controlled)
D
OUT
t
RC
Address
t
OH
t
AA
Previous Data Valid
Data Valid
Input Pulse Levels
0.4V to 2.2V
Input Rise and Fall Time
Input and Output Timing
Reference Level
5 ns
1.1V
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 6 -
Timing Waveform of Read Cycle 2
(3~5)
D
OUT
t
RC
Address
t
ACE
t
AA
t
LZ
t
OE
t
BA
t
OLZ
t
BLZ
t
HZ
t
BHZ
t
OHZ
t
OH
Data Valid
High - Z
CE1
UB / LB
OE
Timing Waveform of Read Cycle 3
(3~5)
D
OUT
t
RC
Address
t
ACE
t
AA
t
LZ
t
OE
t
BA
t
OLZ
t
BLZ
t
HZ
t
BHZ
t
OHZ
t
OH
Data Valid
High - Z
CE2
UB / LB
OE
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
Write Cycle
(11)
( Vcc=2.3 to 2.7V, T
A
= -25
C to 85
C )
85
120
Parameter
Symbol
Min
Max
Min
Max
Unit Note
Write Cycle Time
t
WC
85
120
ns
Chip Enable to Write End
t
CW
70
100
ns
Address Setup to Write End
t
AW
70
100
ns
Address Setup Time
t
AS
0
0
ns
Write Pulse Width
t
WP
60
80
ns
Write Recovery Time
t
WR
0
0
ns
Data Valid to Write End
t
DW
35
50
ns
Data Hold Time
t
DH
0
0
ns
Write Enable to Output in High-Z
t
WHZ
35
35
ns
Output Active from Write End
t
OW
5
5
ns
BLE , BHE Setup to Write End
t
BW
70
100
ns
Timing Waveform of Write Cycle 1 (Address Controlled)
(2~6,8)
D
OUT
t
WC
Address
t
AW
t
WR
CE1
UB / LB
WE
t
CW
t
BW
t
AS
t
WP
t
DW
t
DH
t
OW
High-Z
High-Z
D
IN
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 8 -
Timing Waveform of Write Cycle 2 ( CE1 Controlled)
(2~6,8)
D
OUT
t
WC
Address
t
AW
t
WR
CE1
UB / LB
WE
t
CW
t
AS
t
BW
t
WP
t
DW
t
DH
t
WHZ
t
LZ
High - Z
High - Z
High - Z
D
IN
Timing Waveform of Write Cycle 3 (CE2 Controlled)
(2~6,8)
D
OUT
t
WC
Address
t
AW
t
WR
CE1
UB / LB
WE
t
CW
t
AS
t
BW
t
WP
t
DW
t
DH
t
WHZ
t
LZ
High - Z
High - Z
High - Z
D
IN
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 9 -
Timing Waveform of Write Cycle 4 ( UB / LB Controlled)
(2~6,8)
D
OUT
t
WC
Address
t
AW
t
WR
CE1
UB / LB
WE
t
CW
t
AS
t
BW
t
WP
t
DW
t
DH
t
WHZ
t
BLZ
High - Z
High - Z
High - Z
D
IN
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 10 -
Notes :
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition.
4. This parameter is tested with CL = 5pF. Transition is measured
500mV from steady state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transition address.
10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
Ordering Information
Part Number
SPEED
POWER
PACKAGE
GLT6400M16LL-85TC
85ns
Normal
TSOPII 44L
GLT6400M16SL-85TC
85ns
Normal
TSOPII 44L
GLT6400M16LLI-85TC
85ns
Normal
TSOPII 44L
GLT6400M16SLI-85TC
85ns
Normal
TSOPII 44L
GLT6400M16LL-120TC
120ns
Normal
TSOPII 44L
GLT6400M16SL-120TC
120ns
Normal
TSOPII 44L
GLT6400M16LLI-120TC
120ns
Normal
TSOPII 44L
GLT6400M16SLI-120TC
120ns
Normal
TSOPII 44L
Parts Numbers (Top Mark) Definition :
GLT 6 400 M 16 LL I - 120 TC
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 64K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
VOLTAGE
Blank : 5V
L : 3.3V
M : 2.5V
N : 2.1V
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
10 : 10ns
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
ST : sTSOP (Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
FG : 48-fpBGA
LL : Low Low power
L : Low power
SL : Super Low power
I : Industrial Temperature
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
Package Information
44 pin Small Outline J-form Package (TSOPII)
G -LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 2.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 13 -
GLT6400M16 fpBGA
A B C D E F G H
1
2
3
4
5
6
O O O O O O O O
O O O O O O O O
O O O O O O O O
O O O O O O O O
O O O O O O O O
O O O O O O O O
PACKAGE OUTLINE DWG.
SYMBOL
UNIT : MM
A
1.10
0.1
A1
0.22
0.05
b
0.35
C
0.32TYP
D
10.00
0.10
D1
5.25
E
8.00
0.10
E1
3.75
e
0.75TYP
aaa
0.10
E1
E
D1
D
e
aaa
A1
C
A
b
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