Rev: 2.10 3/2002
1/25
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
5.5 ns
8.5 ns
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
Flow Through mode operation; Pin 14 = No Connect
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS8160F18/32/36T is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
option on Pin 14. Board sites for flow through Burst RAMS
should be designed with V
SS
connected to the FT pin location
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI's pipeline/flow through-configurable Burst RAMs or any
vendor's flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160F18/32/36T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
-5.5
-6
-6.5
-7
-7.5 -8.5 Unit
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
Rev: 2.10 3/2002
2/25
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5
GS8160F18 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
V
DD
NC
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
V
SS
V
DDQ
V
DDQ
V
SS
V
SS
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
N
C
N
C
V
S
S
V
D
D
A
1
8
A
1
7
A
1
0
A
1
1
A
1
2
A
1
3
A
1
4
A
1
6
A
6
A
7
E
1
E
2
N
C
N
C
B
B
B
A
E
3
C
K
G
W
B
W
V
D
D
V
S
S
G
A
D
S
C
A
D
S
P
A
D
V
A
8
A
9
A
1
5
1M x 18
Top View
DQ
A9
A
19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 2.10 3/2002
3/25
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5
GS8160F32 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
N
C
N
C
V
S
S
V
D
D
A
1
8
A
1
7
A
1
0
A
1
1
A
1
2
A
1
3
A
1
4
A
1
6
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
C
K
G
W
B
W
V
D
D
V
S
S
G
A
D
S
C
A
D
S
P
A
D
V
A
8
A
9
A
1
5
512K x 32
Top View
DQ
B5
NC
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
NC
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
NC
DQ
C5
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 2.10 3/2002
4/25
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5
GS8160F36 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
N
C
N
C
V
S
S
V
D
D
A
1
8
A
1
7
A
1
0
A
1
1
A
1
2
A
1
3
A
1
4
A
1
6
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
C
K
G
W
B
W
V
D
D
V
S
S
G
A
D
S
C
A
D
S
P
A
D
V
A
8
A
9
A
1
5
512K x 36
Top View
DQ
B5
DQ
B9
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
DQ
A9
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
DQ
D9
DQ
C5
DQ
C9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 2.10 3/2002
5/25
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A
0
, A
1
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43, 42
A
2
A
18
I
Address Inputs
80
A
19
I
Address Inputs (x18 versions)
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
DQ
A1
DQ
A8
DQ
B1
DQ
B8
DQ
C1
DQ
C8
DQ
D1
DQ
D8
I/O
Data Input and Output pins (x32, x36 Version)
51, 80, 1, 30
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
I/O
Data Input and Output pins (x36 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQ
A1
DQ
A9
DQ
B1
DQ
B9
I/O
Data Input and Output pins (x18 Version)
51, 52, 53, 56, 57
75, 78, 79, 95, 96
1, 2, 3, 6, 7,
25, 28, 29, 30
NC
--
No Connect (x18 Version)
87
BW
I
Byte Write--Writes all enabled bytes; active low
93, 94
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
95, 96
B
C
, B
D
I
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
(x32, x36 Version)
89
CK
I
Clock Input Signal; active high
88
GW
I
Global Write Enable--Writes all bytes; active low
98, 92
E
1
, E
3
I
Chip Enable; active low
97
E
2
I
Chip Enable; active high
86
G
I
Output Enable; active low
83
ADV
I
Burst address counter advance enable; active low
84, 85
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
64
ZZ
I
Sleep Mode control; active high
31
LBO
I
Linear Burst Order mode; active low
15, 41, 65, 91
V
DD
I
Core power supply
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
V
SS
I
I/O and Core Ground
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
I
Output driver power supply
14, 16, 38, 39, 66
NC
--
No Connect
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