Rev: 2.11 3/2002
1/37
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8161Z18/36T-250/225/200/166/150/133
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
Fully pin-compatible with both pipelined and flow through
NtRAMTM, NoBLTM and ZBTTM SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip write parity checking; even or odd selectable
2.5 V or 3.3 V +10%/10% core power supply
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ pin for automatic power-down
JEDEC-standard 100-lead TQFP package
Functional Description
The GS8161Z18/36T is an 18Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising-edge-triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS8161Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
mA
2.5 V
Curr (x18)
Curr (x36)
275
320
250
295
230
265
195
225
180
210
165
185
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
2.5 V
Curr (x18)
Curr (x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Rev: 2.11 3/2002
4/37
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18/36T-250/225/200/166/150/133
100-Pin TQFP Pin Descriptions
Pin Location
Symbol
Type
Description
37, 36
A
0
, A
1
In
Burst Address Inputs; Preload the burst counter
35, 34, 33, 32, 100, 99, 82, 81,
44, 45, 46,47, 48, 49, 50, 83, 84
A
2
A
18
In
Address Inputs
80
A
19
In
Address Input (x18 Version Only)
89
CK
In
Clock Input Signal
93
B
A
In
Byte Write signal for data inputs DQ
A1
DQ
A9
; active low
94
B
B
In
Byte Write signal for data inputs DQ
B1
DQ
B9
; active low
95
B
C
In
Byte Write signal for data inputs DQ
C1
DQ
C9
; active low (x36 Version Only)
96
B
D
In
Byte Write signal for data inputs DQ
D1
DQ
D9
; active low (x36 Version Only)
88
W
In
Write Enable; active low
98
E
1
In
Chip Enable; active low
97
E
2
In
Chip Enable--Active High. For self decoded depth expansion
92
E
3
In
Chip Enable--Active Low. For self decoded depth expansion
86
G
In
Output Enable; active low
85
ADV
In
Advance/Load; Burst address counter control pin
87
CKE
In
Clock Input Buffer Enable; active low
58, 59, 62,63, 68, 69, 72, 73, 74 DQ
A1
DQ
A9
I/O
Byte A Data Input and Output pins (x18 Version Only)
8, 9, 12, 13, 18, 19, 22, 23, 24
DQ
B1
DQ
B9
I/O
Byte B Data Input and Output pins (x18 Version Only)
16, 66
NC
--
No Connect
51, 52, 53, 56, 57, 75, 78, 79,
95, 96, 1, 2, 3, 6, 7, 25, 28, 29,
30
NC
--
No Connect (x18 Version Only)
63, 62, 59, 58, 57, 56, 53, 52, 51 DQ
A1
DQ
A9
I/O
Byte A Data Input and Output pins (x36 Version Only)
68, 69, 72, 73, 74, 75,
78, 79, 80
DQ
B1
DQ
B9
I/O
Byte B Data Input and Output pins (x36 Version Only)
13, 12, 9, 8, 7, 6, 3, 2, 1
DQ
C1
DQ
C9
I/O
Byte C Data Input and Output pins (x36 Version Only)
18, 19, 22, 23, 24, 25, 28, 29, 30 DQ
D1
DQ
D9
I/O
Byte D Data Input and Output pins (x36 Version Only)
64
ZZ
In
Power down control; active high
14
FT
In
Pipeline/Flow Through Mode Control; active low
31
LBO
In
Linear Burst Order; active low.
15, 41, 65, 91
V
DD
In
Core power supply
5, 10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
V
SS
In
Ground
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
In
Output driver power supply
PDF 
ZIP
