Rev: 1.00 10/2001
1/39
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS8162F18/36B-5/5.5/6/6.5/7.5/8.5/10/11
1M x 18, 512K x 36
18Mb S/DCD Sync Burst SRAMs
5 ns
11 ns
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119-Bump BGA
Commercial Temp
Industrial Temp
Features
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip read parity checking; even or odd selectable
ZQ mode pin for user-selectable high/low output drive
On-chip parity encoding and error detection
2.5 V or 3.3 V +10%/5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119-bump BGA package
Functional Description
Applications
The GS8162F18/36B is a 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDriveTM
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS8162F18/36B operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
-5
-5.5
-6
-6.5 -7.5 -8.5 -10 -11 Unit
Flow
Through
2-1-1-1
t
KQ
tCycle
5.0
6.0
5.5
6.5
6.0
7.0
6.5
7.5
7.5
8.5
8.5
10
10
10
11
15
ns
ns
3.3 V
Curr
(x18)
Curr
(x36)
100
110
100
110
150
175
150
175
135
150
135
150
135
150
100
110
mA
mA
2.5 V
Curr
(x18)
Curr
(x36)
95
110
95
110
150
170
150
170
135
150
135
150
135
150
95
110
mA
mA
Rev: 1.00 10/2001
4/39
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162F18/36B-5/5.5/6/6.5/7.5/8.5/10/11
GS8162F18/36 BGA Pin Description
Pin Location
Symbol
Type
Description
P4, N4
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
R2, C3, B3, C2, A2, A3, A5, A6, T3,
T5, R6, C5, B5, C6, B6, B2
An
I
Address Inputs
T4
An
Address Input (x36 Version)
T2, T6
NC
--
No Connect (x36 Version)
T2, T6
An
I
Address Input (x18 Version)
K7, L7, N7, P7, K6, L6, M6, N6
H7, G7, E7, D7, H6, G6, F6, E6
H1, G1, E1, D1, H2, G2, F2, E2
K1, L1, N1, P1, K2, L2, M2, N2
DQ
A1
DQ
A8
DQ
B1
DQ
B8
DQ
C1
DQ
C8
DQ
D1
DQ
D8
I/O
Data Input and Output pins. (x36 Version)
P6, D6, D2, P2
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
I/O
Data Input and Output pins. (x36 Version)
L5, G5, G3, L3
B
A
, B
B
, B
C
, B
D
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low (x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQ
A1
DQ
A9
DQ
B1
DQ
B9
I/O
Data Input and Output pins (x18 Version)
L5, G3
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low (x18 Version)
B1, C1, D4, R1, T1, U6, B7, C7, L4,
R5, R7, J3, J5
NC
--
No Connect
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4
NC
--
No Connect (x18 Version)
K4
CK
I
Clock Input Signal; active high
M4
BW
I
Byte Write--Writes all enabled bytes; active low
H4
GW
I
Global Write Enable--Writes all bytes; active low
E4
E
1
I
Chip Enable; active low
F4
G
I
Output Enable; active low
G4
ADV
I
Burst address counter advance enable; active low
A4, B4
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
T7
ZZ
I
Sleep mode control; active high
R3
LBO
I
Linear Burst Order mode; active low
U2
TMS
I
Scan Test Mode Select
Rev: 1.00 10/2001
5/39
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162F18/36B-5/5.5/6/6.5/7.5/8.5/10/11
U3
TDI
I
Scan Test Data In
U5
TDO
O
Scan Test Data Out
U4
TCK
I
Scan Test Clock
R7
PE
I
Parity Bit Enable; active low
J2, C4, J4, R4, J6
V
DD
I
Core power supply
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
V
SS
I
I/O and Core Ground
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
V
DDQ
I
Output driver power supply
GS8162F18/36 BGA Pin Description
Pin Location
Symbol
Type
Description
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