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Электронный компонент: 8320Z36

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Rev: 1.01 10/2001
1/25
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8320Z18/36T-250/225/200/166/150/133
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Product Preview
Features
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAMTM, NoBLTM and
ZBTTM SRAMs
2.5 V or 3.3 V +10%/
5% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
LBO pin for Linear or Interleave Burst mode
Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
Functional Description
The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8320Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8320Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.3
4.0
2.5
4.4
3.0
5.0
3.5
6.0
3.8
6.6
4.0
7.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
365
430
335
390
300
350
265
305
240
280
220
245
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
360
420
330
380
295
340
260
295
235
270
215
235
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
6.0
7.0
6.5
7.5
7.5
8.5
8.5
10
10
10
11
15
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
200
230
200
230
180
195
180
195
180
195
135
145
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
200
225
200
225
180
195
180
195
180
195
130
145
mA
mA
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Rev: 1.01 10/2001
2/25
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8320Z18/36T-250/225/200/166/150/133
Product Preview
GS8320Z18T Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
FT
V
DD
V
DD
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
N
C
N
C
V
S
S
V
D
D
N
C
A
1
9

A
1
0

A
1
1

A
1
2

A
1
3

A
1
4

A
1
6
A
6
A
7
E
1
E
2
N
C
N
C
B
B
B
A
E
3
C
K
W
C
K
E
V
D
D
V
S
S
G
A
D
V
A
1
8
A
1
7
A
8
A
9

A
1
5
2M x 18
Top View
DQ
A9
A
20
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.01 10/2001
3/25
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8320Z18/36T-250/225/200/166/150/133
Product Preview
GS8320Z36T Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
V
DD
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
N
C
N
C
V
S
S
V
D
D
N
C
A
1
9

A
1
0

A
1
1

A
1
2

A
1
3

A
1
4

A
1
6
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
C
K
W
C
K
E
V
D
D
V
S
S
G
A
D
V
A
1
8
A
1
7
A
8
A
9

A
1
5
1M x 36
Top View
DQ
B5
DQ
B9
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
DQ
A9
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
DQ
D9
DQ
C5
DQ
C9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.01 10/2001
4/25
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8320Z18/36T-250/225/200/166/150/133
Product Preview
100-Pin TQFP Pin Descriptions
Pin Location
Symbol
Type
Description
37, 36
A
0
, A
1
In
Burst Address Inputs; Preload the burst counter
35, 34, 33, 32, 100, 99, 82, 81,
44, 45, 46,47, 48, 49, 50, 83, 84,
43
A
2
A
19
In
Address Inputs
80
A
20
In
Address Input (x18 Version Only)
89
CK
In
Clock Input Signal
93
B
A
In
Byte Write signal for data inputs DQ
A1
-DQ
A9
; active low
94
B
B
In
Byte Write signal for data inputs DQ
B1
-DQ
B9
; active low
95
B
C
In
Byte Write signal for data inputs DQ
C1
-DQ
C9
; active low (x36 Version Only)
96
B
D
In
Byte Write signal for data inputs DQ
D1
-DQ
D9
; active low (x36 Version Only)
88
W
In
Write Enable; active low
98
E
1
In
Chip Enable; active low
97
E
2
In
Chip Enable; Active High. For self decoded depth expansion
92
E
3
In
Chip Enable; Active Low. For self decoded depth expansion
86
G
In
Output Enable; active low
85
ADV
In
Advance/Load; Burst address counter control pin
87
CKE
In
Clock Input Buffer Enable; active low
58, 59, 62,63, 68, 69, 72, 73, 74 DQ
A1
DQ
A9
I/O
Byte A Data Input and Output pins (x18 Version Only)
8, 9, 12, 13, 18, 19, 22, 23, 24
DQ
B1
DQ
B9
I/O
Byte B Data Input and Output pins (x18 Version Only)
51, 52, 53, 56, 57, 75, 78, 79,
1, 2, 3, 6, 7, 25, 28, 29, 30
NC
--
No Connect (x18 Version Only)
63, 62, 59, 58, 57, 56, 53, 52, 51 DQ
A1
DQ
A9
I/O
Byte A Data Input and Output pins (x36 Version Only)
68, 69, 72, 73, 74, 75,
78, 79, 80
DQ
B1
DQ
B9
I/O
Byte B Data Input and Output pins (x36 Version Only)
13, 12, 9, 8, 7, 6, 3, 2, 1
DQ
C1
DQ
C9
I/O
Byte C Data Input and Output pins (x36 Version Only)
18, 19, 22, 23, 24, 25, 28, 29, 30 DQ
D1
DQ
D9
I/O
Byte D Data Input and Output pins (x36 Version Only)
64
ZZ
In
Power down control; active high
14
FT
In
Pipeline/Flow Through Mode Control; active low
31
LBO
In
Linear Burst Order; active low
15, 16, 41, 65, 91
V
DD
In
Core power supply
5,10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
V
SS
In
Ground
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
In
Output driver power supply
38, 39, 42, 66
NC
--
No Connect
Rev: 1.01 10/2001
5/25
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8320Z18/36T-250/225/200/166/150/133
Product Preview
GS8320Z18/36 NBT SRAM Functional Block Diagram
K
S
A
1
S
A
0
B
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s
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C
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3
E
2
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W
B
D
B
C
B
B
B
A
C
K
C
K
E
D






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