Rev: 1.00 10/2001
1/42
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8322Z18(B/C)/GS8322Z36(B/C)/GS8322Z72(C)
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119 and 209 BGA
Commercial Temp
Industrial Temp
Product Preview
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAMTM, NoBLTM and
ZBTTM SRAMs
2.5 V or 3.3 V +10%/5% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip write parity checking; even or odd selectable
On-chip parity encoding and error detection
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 119- or 209-Bump BGA package
Functional Description
The GS8322Z18/36/72 is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8322Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8322Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump or 209-bump BGA package.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.3
4.0
2.5
4.4
3.0
5.0
3.5
6.0
3.8
6.6
4.0
7.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
365
560
660
335
510
600
305
460
540
265
400
460
245
370
430
215
330
380
mA
mA
mA
2.5 V
Curr (x18)
Curr (x36)
Curr (x72)
360
550
640
330
500
590
305
460
530
260
390
450
240
360
420
215
330
370
mA
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
6.0
7.0
6.5
7.5
7.5
8.5
8.5
10
10
10
11
15
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
235
300
350
230
300
350
210
270
300
200
270
300
195
270
300
150
200
220
mA
mA
mA
2.5 V
Curr (x18)
Curr (x36)
Curr (x72)
235
300
340
230
300
340
210
270
300
200
270
300
195
270
300
145
190
220
mA
mA
mA
Rev: 1.00 10/2001
5/42
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18(B/C)/GS8322Z36(B/C)/GS8322Z72(C)
Product Preview
GS8322Z18/36/72 209-Bump BGA Pin Description
Pin Location
Symbol
Type
Description
W6, V6
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs.
W7, W5, V9, V8, V7, V5, V4, V3, U8, U6, U4,
A3, A5, A7, B7, A9, U7
An
I
Address Inputs
B5
A
19
I
Address Inputs (x36/x18 Versions)
C7
A
20
I
Address Inputs (x18 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2
DQ
A1
DQ
A9
DQ
B1
DQ
B9
DQ
C1
DQ
C9
DQ
D1
DQ
D9
DQ
E1
DQ
E9
DQ
F1
DQ
F9
DQ
G1
DQ
G9
DQ
H1
DQ
H9
I/O
Data Input and Output pins (x72 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
DQ
A1
DQ
A9
DQ
B1
DQ
B9
DQ
C1
DQ
C9
DQ
D1
DQ
D9
I/O
Data Input and Output pins (x36 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10
J1, H1, G1, F1, J2, H2, G2, F2, E2
DQ
A1
DQ
A9
DQ
B1
DQ
B9
I/O
Data Input and Output pins (x18 Version)
C9, B8
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low
B3, C4
B
C
,B
D
I
Byte Write Enable for DQ
C
, DQ
D
I/Os; active low
(x72/x36 Versions)
C8, B9, B4, C3
B
E
, B
F
, B
G
,B
H
I
Byte Write Enable for DQ
E
, DQ
F
, DQ
G
, DQ
H
I/Os; active low
(x72 Version)
B5
NC
--
No Connect (x72 Version)
C7
NC
--
No Connect (x72/x36 Versions)
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,
B4, C3
NC
--
No Connect (x36/x18 Versions)
B3, C4
NC
--
No Connect (x18 Version)
C5, D4, D5, D7, D8, K1, K2, K4, K8, K9, K10,
K11, T4, T5, T7, T8, U3, U5, U9
NC
--
No Connect
K3
CK
I
Clock Input Signal; active high
C6
E
1
I
Chip Enable; active low
A8
E
3
I
Chip Enable; active low
A4
E
2
I
Chip Enable; active high
D6
G
I
Output Enable; active low
A6
ADV
I
Burst address counter advance enable
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