Rev: 1.00 10/2001
1/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
2M x 18, 1M x 36, 512K x 72
36Mb Sync NBT SRAMs
250 MHz
133MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119- and 209-Pin BGA
Commercial Temp
Industrial Temp
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAMTM, NoBLTM and
ZBTTM SRAMs
FT pin for user-configurable flow through or pipeline operation
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
2.5 V or 3.3 V +10%/5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119- and 209-bump BGA package
Functional Description
Applications
The GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die
synchronous SRAM module with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device now
finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDriveTM
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS8324Z18/36/72 operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.3
4.0
2.5
4.4
3.0
5.0
3.5
6.0
3.8
6.6
4.0
7.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
365
560
660
335
510
600
305
460
540
265
400
460
245
370
430
215
330
380
mA
mA
mA
2.5 V
Curr (x18)
Curr (x36)
Curr (x72)
360
550
640
330
500
590
305
460
530
260
390
450
240
360
420
215
330
370
mA
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
6.0
7.0
6.5
7.5
7.5
8.5
8.5
10
10
10
11
15
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
235
300
350
230
300
350
210
270
300
200
270
300
195
270
300
150
200
220
mA
mA
mA
2.5 V
Curr (x18)
Curr (x36)
Curr (x72)
235
300
340
230
300
340
210
270
300
200
270
300
195
270
300
145
190
220
mA
mA
mA
Rev: 1.00 10/2001
5/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 209-Bump BGA Pin Description
Pin Location
Symbol
Type
Description
W6, V6
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs.
W7, W5, V9, V8, V7, V5, V4, V3, U8, U6, U4,
A3, A5, A7, B7, A9, U7
An
I
Address Inputs
B5
A
19
I
Address Inputs (x36/x18 Versions)
C7
A
20
I
Address Inputs (x18 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2
DQ
A1
DQ
A9
DQ
B1
DQ
B9
DQ
C1
DQ
C9
DQ
D1
DQ
D9
DQ
E1
DQ
E9
DQ
F1
DQ
F9
DQ
G1
DQ
G9
DQ
H1
DQ
H9
I/O
Data Input and Output pins (x72 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
DQ
A1
DQ
A9
DQ
B1
DQ
B9
DQ
C1
DQ
C9
DQ
D1
DQ
D9
I/O
Data Input and Output pins (x36 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10
J1, H1, G1, F1, J2, H2, G2, F2, E2
DQ
A1
DQ
A9
DQ
B1
DQ
B9
I/O
Data Input and Output pins (x18 Version)
C9, B8
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low
B3, C4
B
C
,B
D
I
Byte Write Enable for DQ
C
, DQ
D
I/Os; active low
(x72/x36 Versions)
C8, B9, B4, C3
B
E
, B
F
, B
G
,B
H
I
Byte Write Enable for DQ
E
, DQ
F
, DQ
G
, DQ
H
I/Os; active low
(x72 Version)
B5
NC
--
No Connect (x72 Version)
C7
NC
--
No Connect (x72/x36 Versions)
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,
B4, C3
NC
--
No Connect (x36/x18 Versions)
B3, C4
NC
--
No Connect (x18 Version)
C5, D4, D5, D7, D8, K1, K2, K4, K8, K9, K10,
K11, T4, T5, T7, T8, U3, U5, U9
NC
--
No Connect
K3
CK
I
Clock Input Signal; active high
C6
E
1
I
Chip Enable; active low
A8
E
3
I
Chip Enable; active low (x72/x36 Versions)
A4
E
2
I
Chip Enable; active high (x72/x36 Versions)
D6
G
I
Output Enable; active low
A6
ADV
I
Burst address counter advance enable
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