Rev: 1.01 3/2002
1/41
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS882Z18/36AB/D-250/225/200/166/150/133
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119 and 165 BGA
Commercial Temp
Industrial Temp
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAMTM, NoBLTM and
ZBTTM SRAMs
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip parity encoding and error detection
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 119-bump BGA and 165-bump FPBGA
packages
Functional Description
The GS882Z18/36A is a 9Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS882Z18/36A may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising edge triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS882Z18/36A is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 119-bump BGA and 165-bump FPBGA packages.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
275
320
250
295
230
265
195
225
180
210
165
185
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Rev: 1.01 3/2002
4/41
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS882Z18/36AB/D-250/225/200/166/150/133
GS882Z18/36A Pin Description
Pin Location
Symbol
Type
Description
P4, N4
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
A2, A3, G4, A5, A6, B3, B5, C2, C3,
C5, C6, R2, R6, T3, T5
An
I
Address Inputs
T4
An
I
Address Inputs (x36 Version)
A4, T2, T6
NC
--
No Connect (x36 Version)
T2, T6
An
I
Address Inputs (x18 Version)
K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2
K1, L1, N1, P1, K2, L2, M2, N2, P2
DQ
A1
DQ
A9
DQ
B
1
DQ
B
9
DQ
C1
DQ
C
9
DQ
D
1
DQ
D
9
I/O
Data Input and Output pins (x36 Version)
L5, G5, G3, L3
B
A
, B
B
, B
C
, B
D
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
A
I/Os; active low ( x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQ
A1
DQ
A9
DQ
B
1
DQ
B
9
I/O
Data Input and Output pin. (x18 Version)
L5, G3
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low ( x18 Version)
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4, A4
NC
--
No Connect (x18 Version)
K4
CK
I
Clock Input Signal; active high
M4
CKE
I
Clock Input Buffer Enable; active low
H4
W
I
Write Enable. Writes all enabled bytes; active low
E4, B6
E
1
, E
3
I
Chip Enable; active low
B2
E
2
I
Chip Enable; active high
F4
G
I
Output Enable; active low
B4
ADV
I
Burst address counter advance enable; active high
T7
ZZ
I
Sleep Mode control; active high
R5
FT
I
Flow Through or Pipeline mode; active low
R3
LBO
I
Linear Burst Order mode; active low
R7
PE
I
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
D4
ZQ
I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
B1, C1, R1, T1, L4, B7, C7, U6, J3,
J5
NC
--
No Connect
U2
TMS
I
Scan Test Mode Select
Rev: 1.01 3/2002
5/41
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS882Z18/36AB/D-250/225/200/166/150/133
BPR1999.05.18
U3
TDI
I
Scan Test Data In
U5
TDO
O
Scan Test Data Out
U4
TCK
I
Scan Test Clock
J2, C4, J4, R4, J6
V
DD
I
Core power supply
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
V
SS
I
I/O and Core Ground
A1, F1, J1, M1, U1, A7, F7,
J7, M7, U7
V
DDQ
I
Output driver power supply
K4
CK
I
Clock Input Signal; active high
GS882Z18/36A Pin Description
Pin Location
Symbol
Type
Description
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