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Электронный компонент: GS78116AB-8

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Rev: 1.00 2/2003
1/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
512K x 16
8Mb Asynchronous SRAM
8, 10, 12 ns
3.3 V V
DD
BGA
Commercial Temp
Industrial Temp
Features
Fast access time: 8, 10, 12 ns
CMOS low power operation: 240/190/170 mA at minimum
cycle time
Single 3.3 V 0.3 V power supply
All inputs and outputs are TTL-compatible
Fully static operation
Industrial Temperature Option: 40 to 85C
14 mm x 22 mm, 119-bump, 1.27 mm Pitch Ball Grid Array
package
Description
The GS78116A is a high speed CMOS Static RAM organized
as 524,288-words by 16-bits. Static design eliminates the need
for external clocks or timing strobes. The GS78116A operates
on a single 3.3 V power supply, and all inputs and outputs are
TTL-compatible. The GS78116 is available in a
14 mm x 22 mm BGA package.
Pin Descriptions
Symbol
Description
A
0
to A
18
Address input
DQ
1
to DQ
16
Data input/output
CE
Chip enable input
WE
Write enable input
OE
Output enable input
V
DD
+3.3 V power supply
V
SS
Ground
NC
No connect
Memory Array
Row
Decoder
Column
Decoder
Address
Input
Buffer
Control
I/O Buffer
A
0
CE
WE
OE
DQ
1
A
18
Block Diagram
DQ
16
Rev: 1.00 2/2003
2/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
512K x 16 Async SRAM in 119-bump, 14 mm x 22 mm
Note: Bumps 1B, 7T, 3C, and 5C are actually NC's but should be wired 3C = V
DD
and 1B, 7T and 5C = V
SS
to assure compatibility
with future versions.
Top View
1
2
3
4
5
6
7
A
NC
A
15
A
14
A
16
A
13
A
12
NC
B
NC,
V
SS
A
11
A
10
CE
A
9
A
8
NC
C
NC
NC
V
DD
,
NC
A
17
V
SS
,
NC
NC
NC
D
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
E
DQ
1
NC
V
DD
V
SS
V
DD
NC
DQ
16
F
DQ
2
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
15
G
DQ
3
NC
V
DD
V
SS
V
DD
NC
DQ
14
H
DQ
4
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
13
J
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
K
DQ
5
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
12
L
DQ
6
NC
V
DD
V
SS
V
DD
NC
DQ
11
M
DQ
7
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
10
N
DQ
8
NC
V
DD
V
SS
V
DD
NC
DQ
9
P
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
R
NC
NC
NC
A
18
NC
NC
NC
T
NC
A
7
A
6
WE
A
5
A
4
NC,
V
SS
U
NC
A
3
A
2
OE
A
1
A
0
NC
Rev: 1.00 2/2003
3/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
Note: X: "H" or "L"
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to
Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect
device reliability.
Notes:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than 2 V and not exceed 20 ns.
Truth Table
CE
OE
WE
DQ
1
to DQ
8
V
DD
Current
H
X
X
Not Selected
ISB1, ISB2
L
L
H
Read
--
L
X
L
Write
I
DD
L
H
H
High Z
--
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
V
DD
0.5 to +4.6
V
Input Voltage
V
IN
0.5 to V
DD
+0.5
(
4.6 V max.)
V
Output Voltage
V
OUT
0.5 to V
DD
+0.5
(
4.6 V max.)
V
Allowable power dissipation
PD
1.5
W
Storage temperature
T
STG
55 to 150
o
C
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage for -8/10/12
V
DD
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0
--
V
DD
+0.3
V
Input Low Voltage
V
IL
0.3
--
0.8
V
Ambient Temperature,
Commercial Range
T
Ac
0
--
70
o
C
Ambient Temperature,
Industrial Range
T
Ai
40
--
85
o
C
Rev: 1.00 2/2003
4/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
Notes:
1. Tested at T
A
= 25C, f = 1 MHz
2. These parameters are sampled and are not 100% tested
Capacitance
Parameter
Symbol
Test Condition
Max
Unit
Input Capacitance
C
IN
V
IN
= 0 V
10
pF
Output Capacitance
C
OUT
V
OUT
= 0 V
7
pF
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
I
IL
V
IN
= 0 to V
DD
2 uA
2 uA
Output Leakage Current
I
OL
Output High Z,
V
OUT
= 0 to V
DD
1 uA
1 uA
Output High Voltage
V
OH
I
OH
= 4 mA
2.4
Output Low Voltage
V
OL
I
OL
= +4 mA
0.4 V
Power Supply Currents
Parameter
Symbol
Test Conditions
0 to 70C
40 to 85C
8 ns
10 ns
12 ns
8 ns
10 ns
12 ns
Operating
Supply
Current
I
DD
E
V
IL
All other inputs
V
IH
or
V
IL
Min. cycle time
I
OUT
= 0 mA
160 mA
130 mA
115 mA
180 mA
150 mA
135 mA
Standby
Current
I
SB1
E
V
IH
All other inputs
V
IH
or
V
IL
Min. cycle time
60 mA
50 mA
50 mA
80 mA
70 mA
70 mA
Standby
Current
I
SB2
E
V
DD
- 0.2V
All other inputs
V
DD
- 0.2V or
0.2V
20 mA
40 mA
Rev: 1.00 2/2003
5/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
AC Test Conditions
AC Characteristics
Read Cycle
Parameter
Symbol
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
8
--
10
--
12
--
ns
Address access time
t
AA
--
8
--
10
--
12
ns
Chip enable access time (CE)
t
AC
--
8
--
10
--
12
ns
Output enable to output valid (OE)
t
OE
--
3.5
--
4
--
5
ns
Output hold from address change
t
OH
3
--
3
--
3
--
ns
Chip enable to output in low Z (CE)
t
LZ
*
3
--
3
--
3
--
ns
Output enable to output in low Z (OE)
t
OLZ
*
0
--
0
--
0
--
ns
Chip disable to output in High Z (CE)
t
HZ
*
--
4
--
5
--
6
ns
Output disable to output in High Z (OE)
t
OHZ
*
--
3.5
--
4
--
5
ns
DQ
VT = 1.4 V
50
30pF
1
DQ
3.3 V
Output Load 1
Output Load 2
589
434
5pF
1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in
Fig. 1 unless otherwise noted
3. Output load 2 for t
LZ
, t
HZ
, t
OLZ
and t
OHZ
.
Parameter
Conditions
Input high level
V
IH
= 2.4 V
Input low level
V
IL
= 0.4 V
Input rise time
tr = 1 V/ns
Input fall time
tf = 1 V/ns
Input reference level
1.4 V
Output reference level
1.4 V
Output load
Fig. 1& 2
Rev: 1.00 2/2003
6/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
Read Cycle 1:CE = OE = V
IL
* These parameters are sampled and are not 100% tested
Write Cycle
Parameter
Symbol
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Write cycle time
tWC
8
--
10
--
12
--
ns
Address valid to end of write
tAW
5.5
--
7
--
8
--
ns
Chip enable to end of write
tCW
5.5
--
7
--
8
--
ns
Data set up time
tDW
4
--
5
--
6
--
ns
Data hold time
tDH
0
--
0
--
0
--
ns
Write pulse width
tWP
5.5
--
7
--
8
--
ns
Address set up time
tAS
0
--
0
--
0
--
ns
Write recovery time (WE)
tWR
0
--
0
--
0
--
ns
Write recovery time (CE)
tWR1
0
--
0
--
0
--
ns
Output Low Z from end of write
tWLZ
*
3
--
3
--
3
--
ns
Write to output in High Z
tWHZ
*
--
3.5
--
4
--
5
ns
t
AA
t
OH
t
RC
Address
Data Out
Previous Data
Data valid
Rev: 1.00 2/2003
7/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
Write Cycle 1: WE Controlled
Write Cycle 2: CE Controlled
t
WC
Address
CE
WE
Data In
OE
Data Out
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
WLZ
t
WHZ
Data valid
High impedance
t
WC
Address
CE
WE
Data In
OE
Data Out
t
AW
t
WP
t
AS
t
CW
t
WR1
t
DW
t
DH
Data valid
High impedance
Rev: 1.00 2/2003
8/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
Package Dimensions - 119-bump PBGA
BPR 1999.05.18
N
P
A
B
Pin 1
Corner
K
E
F
CT
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
G
S
D
1
2
3
4
5
6
7
Package Dimensions - 119 Pin PBGA
Unit: mm
Symbol
Description
Min.
Nom.
Max
A
Width
13.8
14.0
14.2
B
Length
21.8
22.0
22.2
C
Package Height (including ball)
-
2.40
D
Ball Size
0.60
0.75
0.90
E
Ball Height
0.50
0.60
0.70
F
Package Height (excluding balls)
1.46
1.70
G
Width between Balls
1.27
K
Package Height above board
0.80
0.90
1.00
N
Cut-out Package Width
12.00
P
Foot Length
19.50
R
Width of package between balls
7.62
S
Length of package between balls
20.32
T
Variance of Ball Height
0.15
Bottom View
R
Top View
Side View
Rev: 1.00 2/2003
9/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
* Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. For example:
GS78116AB-12T
Ordering Information
Part Number
*
Package
Access Time
Temp. Range
Status
GS78116AB-8
BGA
8 ns
Commercial
GS78116AB-10
BGA
10 ns
Commercial
GS78116AB-12
BGA
12 ns
Commercial
GS78116AB-8I
BGA
8 ns
Industrial
GS78116AB-10I
BGA
10 ns
Industrial
GS78116AB-12I
BGA
12 ns
Industrial
Rev: 1.00 2/2003
10/10
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78116AB
Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page #/Revisions/Reason
GS78116AB_r1
Creation of new datasheet