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Электронный компонент: GS78132AB-8

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Rev: 1.00 2/2003
1/11
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78132AB
256K x 32
8Mb Asynchronous SRAM
8, 10, 12 ns
3.3 V V
DD
BGA
Commercial Temp
Industrial Temp
Features
Fast access time: 8, 10, 12 ns
CMOS low power operation: 260/210/180 mA at minimum
cycle time
Single 3.3 V 0.3 V power supply
All inputs and outputs are TTL-compatible
Byte control
Fully static operation
Industrial Temperature Option: 40 to 85C
14 mm x 22 mm, 119-bump, 1.27 mm Pitch Ball Grid Array
package
Description
The GS78132A is a high speed CMOS Static RAM organized
as 262,144-words by 32-bits. Static design eliminates the need
for external clocks or timing strobes. The GS78132A operates
on a single 3.3 V power supply, and all inputs and outputs are
TTL-compatible. The GS78132A is available in a
14 mm x 22 mm BGA package.
Pin Descriptions
Symbol
Description
A
0
to A
17
Address input
CE
Chip enable input
DQ
A1
TO DQ
A8
Byte A Data input/output
DQ
B1
TO DQ
B8
Byte B Data input/output
DQ
C1
TO DQ
C8
Byte C Data input/output
DQ
D1
TO DQ
D8
Byte D Data input/output
B
A
Byte A Byte enable input
B
B
Byte B Byte enable input
B
C
Byte C Byte enable input
B
D
Byte D Byte enable input
WE
Write enable input
OE
Output enable input
V
DD
+3.3 V power supply
V
SS
Ground
NC
No connect
Memory Array
Row
Decoder
Column
Decoder
Address
Input
Buffer
Control
I/O Buffer
A
0
CE
WE
OE
DQ
1
A
17
Block Diagram
DQ
32
Bx
____
Rev: 1.00 2/2003
2/11
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78132AB
256K x 32 Async SRAM in 119-bump, 14 mm x 22 mm BGA
Note: Bumps 3C and 5C are actually NC's but should be wired 3C = V
DD
and 5C = V
ss
to assure compatibility with future versions.
Top View
1
2
3
4
5
6
7
A
NC
A
15
A
14
A
16
A
13
A
12
NC
B
B
C
A
11
A
10
CE
A
9
A
8
B
B
C
DQ
C6
NC
V
DD
,
NC
A
17
V
SS
,
NC
NC
DQ
B6
D
DQ
C5
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
B5
E
DQ
C4
DQ
C8
V
DD
V
SS
V
DD
DQ
B8
DQ
B4
F
DQ
C3
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
B3
G
DQ
C2
DQ
C7
V
DD
V
SS
V
DD
DQ
B7
DQ
B2
H
DQ
C1
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
B1
J
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
K
DQ
D1
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
A1
L
DQ
D2
DQ
D7
V
DD
V
SS
V
DD
DQ
A7
DQ
A2
M
DQ
D3
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
A3
N
DQ
D4
DQ
D8
V
DD
V
SS
V
DD
DQ
A8
DQ
A4
P
DQ
D5
V
DD
V
SS
V
SS
V
SS
V
DD
DQ
A5
R
DQ
D6
NC
NC
NC
NC
NC
DQ
A6
T
B
D
A
7
A
6
WE
A
5
A
4
B
A
U
NC
A
3
A
2
OE
A
1
A
0
NC
Rev: 1.00 2/2003
3/11
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78132AB
Note: X: "H" or "L"
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to
Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect
device reliability.
Truth Table
CE OE WE B
A
B
B
B
C
B
D
DQ
A1A8
DQ
B1B8
DQ
C1C8
DQ
D1D8
Supply
Current
H
X
X
X
X
X
X
Not Selected
Not Selected
Not Selected
Not Selected
ISB1, ISB2
L
L
H
L
L
L
L
Read
Read
Read
Read
I
DD
H
L
L
L
High Z
Read
Read
Read
L
H
L
L
Read
High Z
Read
Read
L
L
H
L
Read
Read
High Z
Read
L
L
L
H
Read
Read
Read
High Z
L
X
L
L
L
L
L
Write
Write
Write
Write
H
L
L
L
High Z
Write
Write
Write
L
H
L
L
Write
High Z
Write
Write
L
L
H
L
Write
Write
High Z
Write
L
L
L
H
Write
Write
Write
High
L
H
H
X
X
X
X
High Z
High Z
High Z
High Z
L
X
X
H
H
H
H
High Z
High Z
High Z
High Z
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
V
DD
0.5 to +4.6
V
Input Voltage
V
IN
0.5 to V
DD
+0.5
(
4.6 V max.)
V
Output Voltage
V
OUT
0.5 to V
DD
+0.5
(
4.6 V max.)
V
Allowable power dissipation
PD
1.5
W
Storage temperature
T
STG
55 to 150
o
C
Rev: 1.00 2/2003
4/11
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78132AB
Notes:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than 2 V and not exceed 20 ns.
Notes:
1. Tested at T
A
= 25C, f = 1 MHz
2. These parameters are sampled and are not 100% tested
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage for -8/10/12
V
DD
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0
--
V
DD
+0.3
V
Input Low Voltage
V
IL
0.3
--
0.8
V
Ambient Temperature,
Commercial Range
T
Ac
0
--
70
o
C
Ambient Temperature,
Industrial Range
T
Ai
40
--
85
o
C
Capacitance
Parameter
Symbol
Test Condition
Max
Unit
Input Capacitance
C
IN
V
IN
= 0 V
10
pF
Output Capacitance
C
OUT
V
OUT
= 0 V
7
pF
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
I
IL
V
IN
= 0 to V
DD
2 uA
2 uA
Output Leakage Current
I
OL
Output High Z,
V
OUT
= 0 to V
DD
1 uA
1 uA
Output High Voltage
V
OH
I
OH
= 4 mA
2.4
Output Low Voltage
V
OL
I
OL
= +4 mA
0.4 V
Rev: 1.00 2/2003
5/11
2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS78132AB
AC Test Conditions
AC Characteristics
Power Supply Currents
Parameter
Symbol
Test Conditions
0 to 70C
40 to 85C
8 ns
10 ns
12 ns
8 ns
10 ns
12 ns
Operating
Supply
Current
I
DD
E
V
IL
All other inputs
V
IH
or
V
IL
Min. cycle time
I
OUT
= 0 mA
260 mA
210 mA
180 mA
280 mA
230 mA
200 mA
Standby
Current
I
SB1
E
V
IH
All other inputs
V
IH
or
V
IL
Min. cycle time
60 mA
50 mA
50 mA
80 mA
70 mA
70 mA
Standby
Current
I
SB2
E
V
DD
- 0.2V
All other inputs
V
DD
- 0.2V or
0.2V
20 mA
40 mA
DQ
VT = 1.4 V
50
30pF
1
DQ
3.3 V
Output Load 1
Output Load 2
589
434
5pF
1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in
Fig. 1 unless otherwise noted
3. Output load 2 for t
LZ
, t
HZ
, t
OLZ
and t
OHZ
.
Parameter
Conditions
Input high level
V
IH
= 2.4 V
Input low level
V
IL
= 0.4 V
Input rise time
tr = 1 V/ns
Input fall time
tf = 1 V/ns
Input reference level
1.4 V
Output reference level
1.4 V
Output load
Fig. 1& 2