Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

300 MHz150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

100-Pin TQFP
Commercial Temp
Industrial Temp

Preliminary

Features

· FT pin for user-configurable flow through or pipeline

operation

· Single Cycle Deselect (SCD) operation
· 2.5 V or 3.3 V +10%/10% core power supply
· 2.5 V or 3.3 V I/O supply
· LBO pin for Linear or Interleaved Burst mode
· Internal input resistors on mode pins allow floating mode pins
· Default to Interleaved Pipeline mode
· Byte Write (BW) and/or Global Write (GW) operation
· Internal self-timed write cycle
· Automatic power-down for portable applications
· JEDEC-standard 100-lead TQFP package

Functional Description

Applications

The GS816018/32/36AT is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS816018/32/36AT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V

DDQ

) pins are used to decouple output noise

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-300

-250

-200

-150

Unit

Pipeline

3-1-1-1

(x18/x36)

tCycle

2.5
3.3

2.5
4.0

3.0
5.0

3.8
6.7

ns
ns

Curr

(x18)

Curr

(x32/x36)

335
390

280
330

230
270

185
210

mA
mA

Flow Through

2-1-1-1

tCycle

5.0
5.0

5.5
5.5

6.5
6.5

7.5
7.5

ns
ns

Curr

(x18)

Curr

(x32/x36)

230
270

210
240

185
205

170
190

mA
mA

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

GS816018A 100-Pin TQFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

DQP

DDQ

NC
V

ZZ
DQ

DDQ

LBO

ADSC

ADSP

ADV

1M x 18

Top View

DQP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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GS816018/32/36AT-300/250/200/150

Preliminary

GS816032A 100-Pin TQFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

NC
V

ZZ
DQ

DDQ

LBO

ADSC

ADSP

ADV

512K x 32

Top View

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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GS816018/32/36AT-300/250/200/150

Preliminary

GS816036A 100-Pin TQFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

NC
V

ZZ
DQ

DDQ

LBO

ADSC

ADSP

ADV

512K x 36

Top View

DQP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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GS816018/32/36AT-300/250/200/150

Preliminary

TQFP Pin Description

Symbol

Type

Description

, A

Address field LSBs and Address Counter preset Inputs

Address Inputs

I/O

Data Input and Output pins

No Connect

Byte Write--Writes all enabled bytes; active low

, B

Byte Write Enable for DQ

, DQ

Data I/Os; active low

Clock Input Signal; active high

Global Write Enable--Writes all bytes; active low

, E

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

ADV

Burst address counter advance enable; active low

ADSP, ADSC

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

LBO

Linear Burst Order mode; active low

Core power supply

I/O and Core Ground

DDQ

Output driver power supply

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GS816018/32/36AT-300/250/200/150

Preliminary

Note:
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name

Pin

Name

State

Function

Burst Order Control

LBO

Linear Burst

Interleaved Burst

Output Register Control

Flow Through

H or NC

Pipeline

Power Down Control

L or NC

Active

Standby, I

= I

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

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GS816018/32/36AT-300/250/200/150

Preliminary

Byte Write Truth Table

Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B

, B

and/or B

may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes "

" and "

" are only available on the x32 and x36 versions.

Function

Notes

Read

Write byte a

2, 3

Write byte b

2, 3

Write byte c

2, 3, 4

Write byte d

2, 3, 4

Write all bytes

2, 3, 4

Write all bytes

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GS816018/32/36AT-300/250/200/150

Preliminary

Synchronous Truth Table

Operation

Address

Used

State

Diagram

Key

ADSP ADSC

ADV

Deselect Cycle, Power Down

None

High-Z

Deselect Cycle, Power Down

None

High-Z

Deselect Cycle, Power Down

None

High-Z

Read Cycle, Begin Burst

External

Read Cycle, Begin Burst

External

Write Cycle, Begin Burst

External

Read Cycle, Continue Burst

Next

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Next

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Current

Read Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst

Current

Notes:
1. X = Don't Care, H = High, L = Low
2. E = T (True) if E

= 1 and E

= 0; E = F (False) if E

= 0 or E

= 1

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as "Q" in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

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GS816018/32/36AT-300/250/200/150

Preliminary

First Write

First Read

Burst Write

Burst Read

Deselect

Simple Synchronous Operation

Simple Burst Synchronou

s Operation

Simplified State Diagram

Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (B

, B

, BW, and GW)

control inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

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GS816018/32/36AT-300/250/200/150

Preliminary

First Write

First Read

Burst Write

Burst Read

Deselect

Simplified State Diagram with G

Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.03a 5/2003

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GS816018/32/36AT-300/250/200/150

Preliminary

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Condi-
tions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.

Absolute Maximum Ratings

(All voltages reference to V

)

Symbol

Description

Value

Unit

Voltage on V

Pins

0.5 to 4.6

DDQ

Voltage in V

DDQ

Pins

0.5 to 4.6

I/O

Voltage on I/O Pins

0.5 to V

DDQ

+0.5 (

4.6 V max.)

Voltage on Other Input Pins

0.5 to V

+0.5 (

4.6 V max.)

Input Current on Any Pin

+/20

OUT

Output Current on Any I/O Pin

+/20

Package Power Dissipation

1.5

STG

Storage Temperature

55 to 125

BIAS

Temperature Under Bias

55 to 125

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

Power Supply Voltage Ranges

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

3.3 V Supply Voltage

DD3

3.0

3.3

3.6

2.5 V Supply Voltage

DD2

2.3

2.5

2.7

3.3 V V

DDQ

I/O Supply Voltage

DDQ3

3.0

3.3

3.6

2.5 V V

DDQ

I/O Supply Voltage

DDQ2

2.3

2.5

2.7

Notes:
1.

The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDQ3

Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Input High Voltage

2.0

+ 0.3

Input Low Voltage

0.3

0.8

DDQ

I/O Input High Voltage

IHQ

2.0

DDQ

+ 0.3

1,3

DDQ

I/O Input Low Voltage

ILQ

0.3

0.8

1,3

Notes:
1.

Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

DDQ2

Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Input High Voltage

0.6*V

+ 0.3

Input Low Voltage

0.3

0.3*V

DDQ

I/O Input High Voltage

IHQ

0.6*V

DDQ

+ 0.3

1,3

DDQ

I/O Input Low Voltage

ILQ

0.3

0.3*V

1,3

Notes:
1.

Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

Note: These parameters are sample tested.

Recommended Operating Temperatures

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Note:
1.

Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Capacitance

= 25

C, f = 1 MH

, V

= 2.5 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Input Capacitance

= 0 V

Input/Output Capacitance

I/O

OUT

= 0 V

20% tKC

2.0 V

50%

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

+ 2.0 V

50%

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

AC Test Conditions

Parameter

Conditions

Input high level

0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

Output reference level

DDQ

Output load

Fig. 1

Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

= 0 to V

1 uA

ZZ Input Current

IN1

0 V

1 uA

100 uA

FT Input Current

IN2

0 V

100 uA

1 uA

Output Leakage Current

Output Disable, V

OUT

= 0 to V

1 uA

Output High Voltage

OH2

= 8 mA, V

DDQ

= 2.375 V

1.7 V

Output High Voltage

OH3

= 8 mA, V

DDQ

= 3.135 V

2.4 V

Output Low Voltage

= 8 mA

0.4 V

DDQ/2

30pF

Output Load 1

* Distributed Test Jig Capacitance

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

Operating Cu

rrents

Notes:

and I

DDQ

apply to any combination of V

DD3

, V

DD2

, V

DDQ3

, and

operation.

All parameters listed are worst case scenario.

Parameter

T
est

Condi

t
i
ons

Mode

Sym

bol

-300

-250

-200

-
1
50

Unit

to 70°C

to 85°C

to 70°C

85°C

to 70°C

to 85°C

to 70°C

to 85°C

Operat

Current

Dev

i
ce Sel

e
ct

ed;

All oth

e
r inputs

o
r

Outpu

t

open

32/

x36)

Pipeline

DDQ

345

300

240

250

Flow Through

DDQ

240

230

190

200

18)

Pipeline

DDQ

310

270

215

225

Flow Through

DDQ

215

210

175

185

and

Current

0.2 V

Pipeline

4
0

Flow Through

4
0

selec

Current

Devi

c
e
D

e
sel

e
c
t
e
d
;

All oth

e
r inputs

Pipeline

7
5

Flow Through

5
0

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

AC Electrical Characteristics

Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times

as specified above.

Parameter

Symbol

-300

-250

-200

-150

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Pipeline

Clock Cycle Time

tKC

3.3

4.0

5.0

6.7

Clock to Output Valid

tKQ

2.5

3.0

3.8

Clock to Output Invalid

tKQX

1.5

Clock to Output in Low-Z

tLZ

1.5

Setup time

1.0

1.2

1.4

1.5

Hold time

0.1

0.2

0.4

0.5

Flow Through

Clock Cycle Time

tKC

5.0

5.5

6.5

7.5

Clock to Output Valid

tKQ

5.0

5.5

6.5

7.5

Clock to Output Invalid

tKQX

3.0

Clock to Output in Low-Z

tLZ

3.0

Setup time

1.4

1.5

Hold time

0.4

0.5

Clock HIGH Time

tKH

1.3

1.5

Clock LOW Time

tKL

1.5

1.7

Clock to Output in

High-Z

tHZ

1.5 2.5

1.5 3.0

G to Output Valid

tOE

2.5

3.0

3.8

G to output in Low-Z

tOLZ

G to output in High-Z

tOHZ

2.5

3.0

3.8

ZZ setup time

tZZS

ZZ hold time

tZZH

ZZ recovery

tZZR

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

Pipeline Mode Timing

Begi

d A

ont

Cont

e
s
e
lec

Writ

e B

e
a
d C

e
a
d C+1

e
a
d C+2

d C+3

ont

Desele

Burst Rea

S
i
ngle W

r
it

S
i
ngle W

r
it

ngle Re

Q(A)

)

Q(C+1

)

(
C+

Q(C+3)

wit

h

E1

E1 m

a
sk

s A

and

3

only

samp

l
e
d

wit

h

ADSP

and

ADSC i

n
i
tia

ADS

ADV

DQaDQ

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

Flow Through Mode Timing

Begin

ead A

ont

rit

e
B

ead C

e
a
d C+1

d C+

ead C+3

e
a
d C

ont2

e
s
e
l
ec

Q(A)

)

Q(C)

C+

Q(C+2

)

Q(C+3

)

Q(C)

E2 an

d E

3

o
n
l
y
sa

mple

d

with

ADSC

ADSC i

n
it

d r

e
a
d

l
ect

wit

h

E1

Fix

e
d H

i
gh

A0An

aDQd

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of "dummy read cycles" (read cycles that are launched normally but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.

ADSP

ADSC

tKH tKL

tKC

tZZR

tZZH

tZZS

~ ~

Snooze

Sleep Mode Timing Diagram

~ ~
~ ~

~ ~

Rev: 1.03a 5/2003

21/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

TQFP Package Drawing

Pin 1

Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.

Symbol

Description

Min. Nom. Max

Standoff

0.05

0.10

0.15

Body Thickness

1.35

1.40

1.45

Lead Width

0.20

0.30

0.40

Lead Thickness

0.09

0.20

Terminal Dimension

21.9

22.0

22.1

Package Body

19.9

20.0

20.1

Terminal Dimension

15.9

16.0

16.1

Package Body

13.9

14.0

14.1

Lead Pitch

0.65

Foot Length

0.45

0.60

0.75

Lead Length

1.00

Coplanarity

0.10

Lead Angle

Rev: 1.03a 5/2003

22/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

Ordering Information for GSI Synchronous Burst RAMs

Org

Part Number

Type

Package

Speed

(MHz/ns)

Status

1M x 18

GS816018AT-300

Pipeline/Flow Through

TQFP

300/5

1M x 18

GS816018AT-250

Pipeline/Flow Through

TQFP

250/5.5

1M x 18

GS816018AT-200

Pipeline/Flow Through

TQFP

200/6.5

1M x 18

GS816018AT-150

Pipeline/Flow Through

TQFP

150/7.5

512K x 32

GS816032AT-300

Pipeline/Flow Through

TQFP

300/5

512K x 32

GS816032AT-250

Pipeline/Flow Through

TQFP

250/5.5

512K x 32

GS816032AT-200

Pipeline/Flow Through

TQFP

200/6.5

512K x 32

GS816032AT-150

Pipeline/Flow Through

TQFP

150/7.5

512K x 36

GS816036AT-300

Pipeline/Flow Through

TQFP

300/5

512K x 36

GS816036AT-250

Pipeline/Flow Through

TQFP

250/5.5

512K x 36

GS816036AT-200

Pipeline/Flow Through

TQFP

200/6.5

512K x 36

GS816036AT-150

Pipeline/Flow Through

TQFP

150/7.5

1M x 18

GS816018AT-300I

Pipeline/Flow Through

TQFP

300/5

1M x 18

GS816018AT-250I

Pipeline/Flow Through

TQFP

250/5.5

1M x 18

GS816018AT-200I

Pipeline/Flow Through

TQFP

200/6.5

1M x 18

GS816018AT-150I

Pipeline/Flow Through

TQFP

150/7.5

512K x 32

GS816032AT-300I

Pipeline/Flow Through

TQFP

300/5

512K x 32

GS816032AT-250I

Pipeline/Flow Through

TQFP

250/5.5

512K x 32

GS816032AT-200I

Pipeline/Flow Through

TQFP

200/6.5

512K x 32

GS816032AT-150I

Pipeline/Flow Through

TQFP

150/7.5

512K x 36

GS816036AT-300I

Pipeline/Flow Through

TQFP

300/5

512K x 36

GS816036AT-250I

Pipeline/Flow Through

TQFP

250/5.5

512K x 36

GS816036AT-200I

Pipeline/Flow Through

TQFP

200/6.5

512K x 36

GS816036AT-150I

Pipeline/Flow Through

TQFP

150/7.5

Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816018AT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. T

= I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.03a 5/2003

23/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018/32/36AT-300/250/200/150

Preliminary

18Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Page;Revisions;Reason

816018A_r1

· Creation of new datasheet

816018A_r1;

816018A_r1_01

Content

· Updated FT power numbers
· Updated AC Characteristics table
· Updated ZZ recovery time diagram
· Updated AC Test Conditions table and removed Output Load

2 diagram

816018A_r1_01;

816018A_r1_02

Content

· Removed extraneous V

DDQ1

table on page 13 and changed

DDQ2

table to V

DDQ

· Removed pin locations from pin description table

8160xxA_r1_02;

8160xxA_r1_03

Content

· Entire datasheet was rewritten due to design changes

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS816018AT-250I

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS816018AT-250I