1/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS816019/33/37T
Datasheet Errata
Base datasheet:
GS816019/33/37T, Rev.1.00, 3/2002
Product(s) covered in this supplement:
GS816019/33/37T-250/225/200/166/150/133
Product specification(s) addressed by this supplement:
Pin 14
Note: The specifications cited in the base datasheet for the products addressed by this errata remain in force except where
superseded by the information in this errata.
2/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS816019/33/37T
Datasheet Errata
GS816019 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
V
DD
NC
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
V
SS
V
DDQ
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
A
18
A
17
A
10
A
11
A
12
A
13
A
14
A
16
A
6
A
7
E
1
E
2
NC
NC
B
B
B
A
E
3
CK
GW
BW
V
DD
V
SS
G
ADSC
ADSP
ADV
A
8
A
9
A
15
1M x 18
Top View
DQ
A9
A
19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
V
DDQ
/DNU
3/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS816019/33/37T
Datasheet Errata
GS816033 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
A
18
A
17
A
10
A
11
A
12
A
13
A
14
A
16
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
GW
BW
V
DD
V
SS
G
ADSC
ADSP
ADV
A
8
A
9
A
15
512K x 32
Top View
DQ
B5
NC
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
NC
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
NC
DQ
C5
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
V
DDQ
/DNU
4/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS816019/33/37T
Datasheet Errata
GS816037 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
A
18
A
17
A
10
A
11
A
12
A
13
A
14
A
16
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
GW
BW
V
DD
V
SS
G
ADSC
ADSP
ADV
A
8
A
9
A
15
512K x 36
Top View
DQ
B5
DQ
B9
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
DQ
A9
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
DQ
D9
DQ
C5
DQ
C9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
V
DDQ
/DNU
5/5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 5/17/02
GS816019/33/37T
Datasheet Errata
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A
0
, A
1
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43, 42
A
2
A
18
I
Address Inputs
80
A
19
I
Address Inputs (x18 versions)
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
DQ
A1
DQ
A8
DQ
B1
DQ
B8
DQ
C1
DQ
C8
DQ
D1
DQ
D8
I/O
Data Input and Output pins (x32, x36 Version)
51, 80, 1, 30
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
I/O
Data Input and Output pins (x36 Version)
51, 80, 1, 30
NC
No Connect (x32 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQ
A1
DQ
A9
DQ
B1
DQ
B9
I/O
Data Input and Output pins (x18 Version)
51, 52, 53, 56, 57
75, 78, 79, 95, 96,
1, 2, 3, 6, 7,
25, 28, 29, 30
NC
--
No Connect (x18 Version)
87
BW
I
Byte Write--Writes all enabled bytes; active low
93, 94
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
95, 96
B
C
, B
D
I
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
(x32, x36 Version)
89
CK
I
Clock Input Signal; active high
88
GW
I
Global Write Enable--Writes all bytes; active low
98, 92
E
1
, E
3
I
Chip Enable; active low
97
E
2
I
Chip Enable; active high
86
G
I
Output Enable; active low
83
ADV
I
Burst address counter advance enable; active low
84, 85
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
64
ZZ
I
Sleep Mode control; active high
31
LBO
I
Linear Burst Order mode; active low
15, 41, 65, 91
V
DD
I
Core power supply
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
V
SS
I
I/O and Core Ground
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
I
Output driver power supply
16, 38, 39, 66
NC
--
No Connect
14
V
DDQ
/DNU
--
V
DDQ
or V
DD
(must be tied high)
or
Do Not Use (must be left floating)
Rev: 1.00 3/2002
1/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
250 MHz
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
Single Cycle Deselect (SCD) operation
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS816019/33/37T is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS816019/33/37T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.0
4.0
2.2
4.4
2.5
5.0
2.9
6.0
3.3
6.7
3.5
7.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
275
320
250
295
230
265
195
225
180
210
165
185
mA
mA
Rev: 1.00 3/2002
2/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
GS816019 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
V
DD
NC
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
N
C
N
C
V
S
S
V
D
D
A
1
8
A
1
7
A
1
0
A
1
1
A
1
2
A
1
3
A
1
4
A
1
6
A
6
A
7
E
1
E
2
N
C
N
C
B
B
B
A
E
3
C
K
G
W
B
W
V
D
D
V
S
S
G
A
D
S
C
A
D
S
P
A
D
V
A
8
A
9
A
1
5
1M x 18
Top View
DQ
A9
A
19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 1.00 3/2002
3/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
GS816033 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
N
C
N
C
V
S
S
V
D
D
A
1
8
A
1
7
A
1
0
A
1
1
A
1
2
A
1
3
A
1
4
A
1
6
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
C
K
G
W
B
W
V
D
D
V
S
S
G
A
D
S
C
A
D
S
P
A
D
V
A
8
A
9
A
1
5
512K x 32
Top View
DQ
B5
NC
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
NC
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
NC
DQ
C5
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 1.00 3/2002
4/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
GS816037 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
N
C
N
C
V
S
S
V
D
D
A
1
8
A
1
7
A
1
0
A
1
1
A
1
2
A
1
3
A
1
4
A
1
6
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
C
K
G
W
B
W
V
D
D
V
S
S
G
A
D
S
C
A
D
S
P
A
D
V
A
8
A
9
A
1
5
512K x 36
Top View
DQ
B5
DQ
B9
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
DQ
A9
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
DQ
D9
DQ
C5
DQ
C9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
Rev: 1.00 3/2002
5/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A
0
, A
1
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43, 42
A
2
A
18
I
Address Inputs
80
A
19
I
Address Inputs (x18 versions)
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
DQ
A1
DQ
A8
DQ
B1
DQ
B8
DQ
C1
DQ
C8
DQ
D1
DQ
D8
I/O
Data Input and Output pins (x32, x36 Version)
51, 80, 1, 30
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
I/O
Data Input and Output pins (x36 Version)
51, 80, 1, 30
NC
No Connect (x32 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQ
A1
DQ
A9
DQ
B1
DQ
B9
I/O
Data Input and Output pins (x18 Version)
51, 52, 53, 56, 57
75, 78, 79, 95, 96,
1, 2, 3, 6, 7,
25, 28, 29, 30
NC
--
No Connect (x18 Version)
87
BW
I
Byte Write
--
Writes all enabled bytes; active low
93, 94
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
95, 96
B
C
, B
D
I
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
(x32, x36 Version)
89
CK
I
Clock Input Signal; active high
88
GW
I
Global Write Enable
--
Writes all bytes; active low
98, 92
E
1
, E
3
I
Chip Enable; active low
97
E
2
I
Chip Enable; active high
86
G
I
Output Enable; active low
83
ADV
I
Burst address counter advance enable; active low
84, 85
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
64
ZZ
I
Sleep Mode control; active high
31
LBO
I
Linear Burst Order mode; active low
15, 41, 65, 91
V
DD
I
Core power supply
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
V
SS
I
I/O and Core Ground
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
I
Output driver power supply
14, 16, 38, 39, 66
NC
--
No Connect
Rev: 1.00 3/2002
6/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
GS816019/33/37 Block Diagram
A1
A0
A0
A1
D0
D1
Q1
Q0
Counter
Load
D
Q
D
Q
Register
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
R
e
g
i
s
t
e
r
D
Q
R
e
g
i
s
t
e
r
A0
An
LBO
ADV
CK
ADSC
ADSP
GW
BW
E
1
G
ZZ
Power Down
Control
Memory
Array
36
36
4
A
Q
D
E
2
E
3
DQx1
DQx9
Note: Only x36 version shown for simplicity.
1
B
A
B
B
B
C
B
D
1
Rev: 1.00 3/2002
7/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
Note:
Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Burst Counter Sequences
BPR 1999.05.18
Byte Write Truth Table
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes "
C
" and "
D
" are only available on the x32 and x36 versions.
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Power Down Control
ZZ
L or NC
Active
H
Standby, I
DD
= I
SB
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Rev: 1.00 3/2002
8/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key
5
E
1
E
2
ADSP ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
None
X
H
X
X
L
X
X
High-Z
Deselect Cycle, Power Down
None
X
L
F
L
X
X
X
High-Z
Deselect Cycle, Power Down
None
X
L
F
H
L
X
X
High-Z
Read Cycle, Begin Burst
External
R
L
T
L
X
X
X
Q
Read Cycle, Begin Burst
External
R
L
T
H
L
X
F
Q
Write Cycle, Begin Burst
External
W
L
T
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
X
H
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
X
H
H
H
T
D
Write Cycle, Suspend Burst
Current
H
X
X
H
H
T
D
Notes:
1. X = Don't Care, H = High, L = Low
2. E = T (True) if E
2
= 1 and E
3
= 0; E = F (False) if E
2
= 0 or E
3
= 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as "Q" in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.00 3/2002
9/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
S
i
m
p
l
e
S
y
n
c
h
r
o
n
o
u
s
O
p
e
r
a
t
i
o
n
S
i
m
p
l
e
B
u
r
s
t
S
y
n
c
h
r
o
n
o
u
s
O
p
e
r
a
t
i
o
n
CR
R
CW
CR
CR
Simplified State Diagram
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (B
A
, B
B
, B
C
, B
D
, BW, and GW)
control inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.00 3/2002
10/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.00 3/2002
11/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Condi-
tions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Absolute Maximum Ratings
(All voltages reference to V
SS
)
Symbol
Description
Value
Unit
V
DD
Voltage on V
DD
Pins
0.5 to 4.6
V
V
DDQ
Voltage in V
DDQ
Pins
0.5 to 4.6
V
V
CK
Voltage on Clock Input Pin
0.5 to 6
V
V
I/O
Voltage on I/O Pins
0.5 to V
DDQ
+0.5 (
4.6 V max.)
V
V
IN
Voltage on Other Input Pins
0.5 to V
DD
+0.5 (
4.6 V max.)
V
I
IN
Input Current on Any Pin
+/
20
mA
I
OUT
Output Current on Any I/O Pin
+/
20
mA
P
D
Package Power Dissipation
1.5
W
T
STG
Storage Temperature
55 to 125
o
C
T
BIAS
Temperature Under Bias
55 to 125
o
C
Rev: 1.00 3/2002
12/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
3.3 V Supply Voltage
V
DD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
V
DD2
2.3
2.5
2.7
V
3.3 V V
DDQ
I/O Supply Voltage
V
DDQ3
3.0
3.3
3.6
V
2.5 V V
DDQ
I/O Supply Voltage
V
DDQ2
2.3
2.5
2.7
V
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be
2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
V
DDQ3
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
2.0
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.8
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
2.0
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.8
V
1,3
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be
2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3.
V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
V
DDQ2
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
0.6*V
DD
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.3*V
DD
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
0.6*V
DD
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.3*V
DD
V
1,3
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be
2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3.
V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
Rev: 1.00 3/2002
13/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
Note: These parameters are sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
T
A
0
25
70
C
2
Ambient Temperature (Industrial Range Versions)
T
A
40
25
85
C
2
Note:
1.
The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be
2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Capacitance
(T
A
= 25
o
C, f = 1 MH
Z
, V
DD
= 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
C
IN
V
IN
= 0 V
4
5
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0 V
6
7
pF
Package Thermal Characteristics
Rating
Layer Board
Symbol
Max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
R
JA
40
C/W
1,2
Junction to Ambient (at 200 lfm)
four
R
JA
24
C/W
1,2
Junction to Case (TOP)
--
R
JC
9
C/W
3
20% tKC
V
SS
2.0 V
50%
V
SS
V
IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
V
DD
+ 2.0 V
50%
V
DD
V
IL
Rev: 1.00 3/2002
14/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
AC Test Conditions
Parameter
Conditions
Input high level
V
DD
0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DD
/2
Output reference level
V
DDQ
/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig.
1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
1 uA
1 uA
ZZ Input Current
I
IN1
V
DD
V
IN
V
IH
0 V
V
IN
V
IH
1 uA
1 uA
1 uA
100 uA
Output Leakage Current
I
OL
Output Disable, V
OUT
= 0 to V
DD
1 uA
1 uA
Output High Voltage
V
OH2
I
OH
=
8 mA, V
DDQ
= 2.375 V
1.7 V
--
Output High Voltage
V
OH3
I
OH
=
8 mA, V
DDQ
= 3.135 V
2.4 V
--
Output Low Voltage
V
OL
I
OL
= 8 mA
--
0.4 V
DQ
V
DDQ/2
50
30pF
*
Output Load 1
* Distributed Test Jig Capacitance
Rev: 1.00 3/2002
15/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
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9
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3
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4
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6
5
3
5
2
7
5
3
5
2
4
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3
0
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5
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3
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5
2
5
2
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2
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(
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i
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0
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2
3
5
2
0
2
4
5
2
0
2
1
5
1
5
2
2
5
1
5
1
8
5
1
5
1
9
5
1
5
1
7
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1
5
1
8
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1
5
1
5
5
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A
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2
.
5
V
D
e
v
i
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e
l
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c
t
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;
A
l
l
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o
r
V
I
L
O
u
t
p
u
t
o
p
e
n
(
x
3
2
/
x
3
6
)
P
i
p
e
l
i
n
e
I
D
D
I
D
D
Q
2
9
0
3
0
3
0
0
3
0
2
6
5
3
0
2
7
5
3
0
2
4
0
2
5
2
5
0
2
5
2
0
5
2
0
2
1
5
2
0
1
9
0
2
0
2
0
0
2
0
1
7
0
1
5
1
8
0
1
5
m
A
(
x
1
8
)
P
i
p
e
l
i
n
e
I
D
D
I
D
D
Q
2
6
0
1
5
2
7
0
1
5
2
3
5
1
5
2
4
5
1
5
2
1
5
1
5
2
2
5
1
5
1
8
5
1
0
1
9
5
1
0
1
7
0
1
0
1
8
0
1
0
1
5
5
1
0
1
6
5
1
0
m
A
S
t
a
n
d
b
y
C
u
r
r
e
n
t
Z
Z
V
D
D
0
.
2
V
--
P
i
p
e
l
i
n
e
I
S
B
2
0
3
0
2
0
3
0
2
0
3
0
2
0
3
0
2
0
3
0
2
0
3
0
m
A
D
e
s
e
l
e
c
t
C
u
r
r
e
n
t
D
e
v
i
c
e
D
e
s
e
l
e
c
t
e
d
;
A
l
l
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t
h
e
r
i
n
p
u
t
s
V
I
H
o
r
V
I
L
--
P
i
p
e
l
i
n
e
I
D
D
8
5
9
0
8
0
8
5
7
5
8
0
6
4
7
0
6
0
6
5
5
0
5
5
m
A
Rev: 1.00 3/2002
16/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Parameter
Symbol
-250
-225
-200
-166
-150
-133
Unit
Min
Max
Min
Max
Min
Max
Min
Max Min Max Min Max
Pipeline
Clock Cycle Time
tKC
4.0
--
4.4
--
5.0
--
6.0
--
6.7
--
7.5
--
ns
Clock to Output Valid
tKQ
--
2.0
--
2.2
--
2.5
--
2.9
--
3.3
--
3.5
ns
Clock to Output Invalid
tKQX
1.0
--
1.0
--
1.0
--
1.0
--
1.0
--
1.0
--
ns
Clock to Output in Low-Z
tLZ
1
1.0
--
1.0
--
1.0
--
1.0
--
1.0
--
1.0
--
ns
Setup time
tS
1.2
--
1.3
--
1.4
--
1.5
--
1.5
--
1.5
--
ns
Hold time
tH
0.2
--
0.3
--
0.4
--
0.5
--
0.5
--
0.5
--
ns
G to Output Valid
tOE
--
1.8
--
2.0
--
2.5
--
2.9
--
3.3
--
3.5
ns
G to output in High-Z
tOHZ
1
--
1.8
--
2.0
--
2.5
--
2.5
--
2.5
--
2.5
ns
Clock HIGH Time
tKH
1.3
--
1.3
--
1.3
--
1.3
--
1.5
--
1.7
--
ns
Clock LOW Time
tKL
1.5
--
1.5
--
1.5
--
1.5
--
1.7
--
2
--
ns
Clock to Output in
High-Z
tHZ
1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0
1.5
3.0
1.5 3.0
ns
G to output in Low-Z
tOLZ
1
0
--
0
--
0
--
0
--
0
--
0
--
ns
ZZ setup time
tZZS
2
5
--
5
--
5
--
5
--
5
--
5
--
ns
ZZ hold time
tZZH
2
1
--
1
--
1
--
1
--
1
--
1
--
ns
ZZ recovery
tZZR
20
--
20
--
20
--
20
--
20
--
20
--
ns
Rev: 1.00 3/2002
17/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
CK
ADSP
ADSC
ADV
GW
BW
G
WR2
WR3
WR1
WR1
WR2
WR3
tKC
Single Write
Burst Write
D2
A
D2
B
D2
C
D2
D
D3
A
D1
A
t
KL
t
KH
tS tH
tS tH
tS tH
tS tH
tS tH
tS tH
tS tH
tS tH
Write specified byte for 2
A
and all bytes for 2
B
, 2
C
& 2
D
ADV must be inactive for ADSP Write
ADSC initiated write
ADSP is blocked by E inactive
A
0
An
B
A
B
D
DQ
A
DQ
D
Write
Deselected
Hi-Z
WR1
WR2
WR3
Write Cycle Timing
E
1
E
3
tS tH
tS tH
tS tH
E
2
and E
3
only sampled with ADSP or ADSC
E
1
masks ADSP
E
2
Deselected with E
2
Rev: 1.00 3/2002
18/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
Pipelined SCD Read Cycle Timing
Q1
A
Q3
A
Q2
D
Q2c
Q2
B
Q2
A
tKQ
tLZ
tOE
tOHZ
tOLZ
tKQX
tHZ
tKQX
CK
ADSP
ADSC
BW
G
GW
ADV
Burst Read
RD2
RD3
tKL
tS
tH
tH
tS tH
tS tH
ADSC initiated read
Suspend Burst
Single Read
ADSP is blocked by E inactive
A
0
An
BW
A
BW
D
tKH
tKC
tS
tH
tS
tS
tH
DQ
A
DQ
D
RD1
Hi-Z
E
2
tS
tH
tH
tH
E
1
masks ADSP
E
2
and E
3
only sampled with ADSP or ADSC
Deselected with E
2
E
3
E
1
tS
tS
Rev: 1.00 3/2002
19/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
CK
ADSP
ADV
GW
BW
G
Q1
A
D1
A
Q2
A
Q2
Bb
Q2c
Q2
D
Single Read
Burst Read
tOE
tOHZ
tS tH
tS
tH
tH
tS tH
tS tH
tKH
DQ
A
DQ
D
BW
A
BW
D
tKL
tKC
tS
Single Write
ADSP is blocked by E inactive
tKQ
tS tH
Hi-Z
Pipelined SCD Read-Write Cycle Timing
WR1
E
1
E
3
E
2
tS
tS tH
tS
E
1
masks ADSP
E
2
and E
3
only sampled with ADSP and ADSC
Deselected with E
3
tH
tH
RD1
WR1
RD2
tS tH
A
0
An
ADSC
tS tH
ADSC initiated read
Rev: 1.00 3/2002
20/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of "dummy read cycles" (read cycles that are launched normally but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
Snooze
Sleep Mode Timing Diagram
~ ~
~ ~
~ ~
~ ~
~ ~
Rev: 1.00 3/2002
21/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
TQFP Package Drawing
D
1
D
E1
E
P
i
n
1
b
e
c
L
L1
A2
A1
Y
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol
Description
Min. Nom. Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
--
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
--
0.65
--
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
--
1.00
--
Y
Coplanarity
0.10
Lead Angle
0
--
7
Rev: 1.00 3/2002
22/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number
1
Type
Package
Speed
(MHz/ns)
T
A
2
Status
1M x 18
GS816019T-250
Pipeline
TQFP
250
C
1M x 18
GS816019T-225
Pipeline
TQFP
225
C
1M x 18
GS816019T-200
Pipeline
TQFP
200
C
1M x 18
GS816019T-166
Pipeline
TQFP
166
C
1M x 18
GS816019T-150
Pipeline
TQFP
150
C
1M x 18
GS816019T-133
Pipeline
TQFP
133
C
512K x 32
GS816033T-250
Pipeline
TQFP
250
C
512K x 32
GS816033T-225
Pipeline
TQFP
225
C
512K x 32
GS816033T-200
Pipeline
TQFP
200
C
512K x 32
GS816033T-166
Pipeline
TQFP
166
C
512K x 32
GS816033T-150
Pipeline
TQFP
150
C
512K x 32
GS816033T-133
Pipeline
TQFP
133
C
512K x 36
GS816037T-250
Pipeline
TQFP
250
C
512K x 36
GS816037T-225
Pipeline
TQFP
225
C
512K x 36
GS816037T-200
Pipeline
TQFP
200
C
512K x 36
GS816037T-166
Pipeline
TQFP
166
C
512K x 36
GS816037T-150
Pipeline
TQFP
150
C
512K x 36
GS816037T-133
Pipeline
TQFP
133
C
1M x 18
GS816019T-250I
Pipeline
TQFP
250
I
1M x 18
GS816019T-225I
Pipeline
TQFP
225
I
1M x 18
GS816019T-200I
Pipeline
TQFP
200
I
1M x 18
GS816019T-166I
Pipeline
TQFP
166
I
1M x 18
GS816019T-150I
Pipeline
TQFP
150
I
1M x 18
GS816019T-133I
Pipeline
TQFP
133
I
512K x 32
GS816033T-250I
Pipeline
TQFP
250
I
512K x 32
GS816033T-225I
Pipeline
TQFP
225
I
512K x 32
GS816033T-200I
Pipeline
TQFP
200
I
512K x 32
GS816033T-166I
Pipeline
TQFP
166
I
512K x 32
GS816033T-150I
Pipeline
TQFP
150
I
512K x 32
GS816033T-133I
Pipeline
TQFP
133
I
512K x 36
GS816037T-250I
Pipeline
TQFP
250
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816019T-150IT.
2. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00 3/2002
23/24
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816019/33/37T-250/225/200/166/150/133
512K x 36
GS816037T-225I
Pipeline
TQFP
225
I
512K x 36
GS816037T-200I
Pipeline
TQFP
200
I
512K x 36
GS816037T-166I
Pipeline
TQFP
166
I
512K x 36
GS816037T-150I
Pipeline
TQFP
150
I
512K x 36
GS816037T-133I
Pipeline
TQFP
133
I
Org
Part Number
1
Type
Package
Speed
(MHz/ns)
T
A
2
Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816019T-150IT.
2. T
A
= C = Commercial Temperature Range. T
A
= I = Ind
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