Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

GS8160Z18/36AT-300/250/200/150

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

300 MHz150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

100-Pin TQFP
Commercial Temp
Industrial Temp

Preliminary

Features

· NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAMTM, NoBLTM and
ZBTTM SRAMs

· 2.5 V or 3.3 V +10%/10% core power supply
· 2.5 V or 3.3 V I/O supply
· User-configurable Pipeline and Flow Through mode
· LBO pin for Linear or Interleave Burst mode
· Pin compatible with 2M, 4M, and 8M devices
· Byte write operation (9-bit Bytes)
· 3 chip enable signals for easy depth expansion
· ZZ Pin for automatic power-down
· JEDEC-standard 100-lead TQFP package

Functional Description

The GS8160Z18/36AT is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS8160Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.

The GS8160Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.

Parameter Synopsis

-300

-250

-200

-150

Unit

Pipeline

3-1-1-1

(x18/x36)

tCycle

2.5
3.3

2.5
4.0

3.0
5.0

3.8
6.7

ns
ns

Curr

(x18)

Curr

(x32/x36)

335
390

280
330

230
270

185
210

mA
mA

Flow Through

2-1-1-1

tCycle

5.0
5.0

5.5
5.5

6.5
6.5

7.5
7.5

ns
ns

Curr

(x18)

Curr

(x32/x36)

230
270

210
240

185
205

170
190

mA
mA

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

GS8160Z18AT Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

DQP

DDQ

NC
V

ZZ
DQ

DDQ

CKE

ADV

1M x 18

Top View

DQP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

GS8160Z36AT Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

NC
V

ZZ
DQ

DDQ

CKE

ADV

512K x 36

Top View

DQP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

100-Pin TQFP Pin Descriptions

Symbol

Type

Description

, A

Burst Address Inputs; Preload the burst counter

Address Inputs

Clock Input Signal

Byte Write signal for data inputs DQ

-DQ

; active low

Byte Write signal for data inputs DQ

-DQ

; active low

Byte Write signal for data inputs DQ

-DQ

; active low

Byte Write signal for data inputs DQ

-DQ

; active low

Write Enable; active low

Chip Enable; active low

Chip Enable; Active High. For self decoded depth expansion

Chip Enable; Active Low. For self decoded depth expansion

Output Enable; active low

ADV

Advance/Load; Burst address counter control pin

CKE

Clock Input Buffer Enable; active low

No Connect

I/O

Byte A Data Input and Output pins

I/O

Byte B Data Input and Output pins

I/O

Byte C Data Input and Output pins

I/O

Byte D Data Input and Output pins

Power down control; active high

Pipeline/Flow Through Mode Control; active low

LBO

Linear Burst Order; active low

Core power supply

Ground

DDQ

Output driver power supply

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GS8160Z18/36AT-300/250/200/150

Preliminary

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E

, E

and E

). Deassertion of any one of the Enable

inputs will deactivate the device.

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E

, E

and E

) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B

, B

& B

) determine which bytes will be written. All or none may be activated. A write

cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.

Function

Read

Write Byte "a"

Write Byte "b"

Write Byte "c"

Write Byte "d"

Write all Bytes

Write Abort/NOP

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

Synchronous Truth Table

Operation

Type Address E

ZZ ADV W Bx G CKE CK

Notes

Deselect Cycle, Power Down

None

L-H High-Z

Deselect Cycle, Power Down

None

L-H High-Z

Deselect Cycle, Power Down

None

L-H High-Z

Deselect Cycle, Continue

None

L-H High-Z

Read Cycle, Begin Burst

External

L-H

Read Cycle, Continue Burst

L-H

1,10

NOP/Read, Begin Burst

External

L-H High-Z

Dummy Read, Continue Burst

L-H High-Z

1,2,10

Write Cycle, Begin Burst

External

L-H

Write Cycle, Continue Burst

L-H

1,3,10

NOP/Write Abort, Begin Burst

None

L-H High-Z

2,3

Write Abort, Continue Burst

L-H High-Z 1,2,3,10

Clock Edge Ignore, Stall

Current

L-H

Sleep Mode

None

High-Z

Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-

lect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W

pin is sampled low but no Byte Write pins are active so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during

write cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write

signals are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

Deselect

New Read

New Write

Burst Read

Burst Write

Pipeline and Flow Through Read Write Control State Diagram

Current State (n)

Next State (n+1)

Transition

Input Command Code

Key

Notes:

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B and D represent input command

codes ,as indicated in the Synchronous Truth Table.

Clock (CK)

Command

Current State

Next State

n+1

n+2

n+3

Current State and Next State Definition for

Pipeline and Flow Through Read/Write Control State Diagram

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

Intermediate

High Z

(Data In)

Data Out

(Q Valid)

High Z

B W

Pipeline Mode Data I/O State Diagram

Current State (n)

Next State (n+2)

Transition

Input Command Code

Key

Transition

Intermediate State (N+1)

Notes:

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Clock (CK)

Command

Current State

Intermediate

n+1

n+2

n+3

Current State and Next State Definition for

Pipeline Mode Data I/O State Diagram

Next State

State

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

High Z

(Data In)

Data Out

(Q Valid)

High Z

B W

Current State (n)

Next State (n+1)

Transition

Input Command Code

Key

Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B and D represent input command

codes as indicated in the Truth Tables.

Flow Through Mode Data I/O State Diagram

Clock (CK)

Command

Current State

Next State

n+1

n+2

n+3

Current State and Next State Definition for:

Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.03a 5/2003

11/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.

Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name

Pin

Name

State

Function

Burst Order Control

LBO

Linear Burst

Interleaved Burst

Output Register Control

Flow Through

H or NC

Pipeline

Power Down Control

L or NC

Active

Standby, I

= I

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V

or V

DDQ

on pipelined parts and V

on flow

through parts. GSI NBT SRAMs are fully compatible with these sockets.

tZZR

tZZH

tZZS

~ ~

Sleep

~ ~

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to
Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of
time, may affect reliability of this component.

Absolute Maximum Ratings

(All voltages reference to V

)

Symbol

Description

Value

Unit

Voltage on V

Pins

0.5 to 4.6

DDQ

Voltage in V

DDQ

Pins

0.5 to 4.6

I/O

Voltage on I/O Pins

0.5 to V

DDQ

+0.5 (

4.6 V max.)

Voltage on Other Input Pins

0.5 to V

+0.5 (

4.6 V max.)

Input Current on Any Pin

+/20

OUT

Output Current on Any I/O Pin

+/20

Package Power Dissipation

1.5

STG

Storage Temperature

55 to 125

BIAS

Temperature Under Bias

55 to 125

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

Power Supply Voltage Ranges

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

3.3 V Supply Voltage

DD3

3.0

3.3

3.6

2.5 V Supply Voltage

DD2

2.3

2.5

2.7

3.3 V V

DDQ

I/O Supply Voltage

DDQ3

3.0

3.3

3.6

2.5 V V

DDQ

I/O Supply Voltage

DDQ2

2.3

2.5

2.7

Notes:
1.

The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDQ3

Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Input High Voltage

2.0

+ 0.3

Input Low Voltage

0.3

0.8

DDQ

I/O Input High Voltage

IHQ

2.0

DDQ

+ 0.3

1,3

DDQ

I/O Input Low Voltage

ILQ

0.3

0.8

1,3

Notes:
1.

2. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

DDQ2

Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Input High Voltage

0.6*V

+ 0.3

Input Low Voltage

0.3

0.3*V

DDQ

I/O Input High Voltage

IHQ

0.6*V

DDQ

+ 0.3

1,3

DDQ

I/O Input Low Voltage

ILQ

0.3

0.3*V

1,3

Notes:
1.

2. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

Note: These parameters are sample tested.

Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-

ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Recommended Operating Temperatures

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:
1.

2. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Capacitance

= 25

C, f = 1 MH

, V

= 2.5 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Input Capacitance

= 0 V

Input/Output Capacitance

I/O

OUT

= 0 V

Package Thermal Characteristics

Rating

Layer Board

Symbol

Max

Unit

Notes

Junction to Ambient (at 200 lfm)

single

C/W

1,2

Junction to Ambient (at 200 lfm)

four

C/W

1,2

Junction to Case (TOP)

C/W

20% tKC

2.0 V

50%

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

+ 2.0 V

50%

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

AC Test Conditions

Parameter

Conditions

Input high level

0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

Output reference level

DDQ

Output load

Fig. 1

Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

= 0 to V

1 uA

ZZ Input Current

IN1

0 V

1 uA
1 uA

1 uA

100 uA

FT Input Current

IN2

0 V

100 uA

1 uA

1 uA
1 uA

Output Leakage Current

Output Disable, V

OUT

= 0 to V

1 uA

Output High Voltage

OH2

= 8 mA, V

DDQ

= 2.375 V

1.7 V

Output High Voltage

OH3

= 8 mA, V

DDQ

= 3.135 V

2.4 V

Output Low Voltage

= 8 mA

0.4 V

DDQ/2

30pF

Output Load 1

* Distributed Test Jig Capacitance

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

p
er

ing C

u
rrent

Notes:

d I

DDQ

apply to any combination of V

DD3

, V

DD2

, V

, and V

DDQ2

operation.

All p

a
rameters listed are worst case scenario.

Parameter

T
est Conditions

Mode

Symbol

-300

-25

-200

-15

Unit

to 70°C

to 85°C

to 70°

to 85°C

to 70°C

to 85°C

to 70°C

to 85°C

p
er

r
r
e
n
t

Devi

ed;

All other

input

o
r

Output

pen

(x32

P
i
pe

li
ne

DDQ

355

290

250

190

200

Flow

rou

g
h

DDQ

250

220

200

175

185

(x18

)

P
i
pe

li
ne

DDQ

320

260

225

170

180

Flow

rou

g
h

DDQ

225

200

185

160

170

andby

r
r
e
n
t

0.2 V

P
i
pe

li
ne

4
0

Flow

rou

g
h

4
0

Des

e
lect

r
r
e
n
t

ce Des

e
l
e
ct

ed;

All other

input

P
i
pe

li
ne

8
5

6
0

Flow

rou

g
h

6
0

5
0

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

AC Electrical Characteristics

Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Parameter

Symbol

-300

-250

-200

-150

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Pipeline

Clock Cycle Time

tKC

3.3

4.0

5.0

6.7

Clock to Output Valid

tKQ

2.5

3.0

3.8

Clock to Output Invalid

tKQX

1.5

Clock to Output in Low-Z

tLZ

1.5

Setup time

1.0

1.2

1.4

1.5

Hold time

0.1

0.2

0.4

0.5

Flow Through

Clock Cycle Time

tKC

5.0

5.5

6.5

7.5

Clock to Output Valid

tKQ

5.0

5.5

6.5

7.5

Clock to Output Invalid

tKQX

3.0

Clock to Output in Low-Z

tLZ

3.0

Setup time

1.4

1.5

Hold time

0.4

0.5

Clock HIGH Time

tKH

1.3

1.5

Clock LOW Time

tKL

1.5

1.7

Clock to Output in

High-Z

tHZ

1.5 2.5

1.5 3.0

G to Output Valid

tOE

2.5

3.0

3.8

G to output in Low-Z

tOLZ

G to output in High-Z

tOHZ

2.5

3.0

3.8

ZZ setup time

tZZS

ZZ hold time

tZZH

ZZ recovery

tZZR

Rev: 1.03a 5/2003

21/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

TQFP Package Drawing

BPR 1999.05.18

Pin 1

Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.

Symbol

Description

Min. Nom. Max

Standoff

0.05

0.10

0.15

Body Thickness

1.35

1.40

1.45

Lead Width

0.20

0.30

0.40

Lead Thickness

0.09

0.20

Terminal Dimension

21.9

22.0

20.1

Package Body

19.9

20.0

20.1

Terminal Dimension

15.9

16.0

16.1

Package Body

13.9

14.0

14.1

Lead Pitch

0.65

Foot Length

0.45

0.60

0.75

Lead Length

1.00

Coplanarity

0.10

Lead Angle

Rev: 1.03a 5/2003

22/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

Ordering Information--GSI NBT Synchronous SRAM

Org

Part Number

Type

Package

Speed

(MHz/ns)

Status

1M x 18

GS8160Z18AT-300

NBT Pipeline/Flow Through

TQFP

300/5

1M x 18

GS8160Z18AT-250

NBT Pipeline/Flow Through

TQFP

250/5.5

1M x 18

GS8160Z18AT-200

NBT Pipeline/Flow Through

TQFP

200/6.5

1M x 18

GS8160Z18AT-150

NBT Pipeline/Flow Through

TQFP

150/7.5

512K x 36

GS8160Z36AT-300

NBT Pipeline/Flow Through

TQFP

300/5

512K x 36

GS8160Z36AT-250

NBT Pipeline/Flow Through

TQFP

250/5.5

512K x 36

GS8160Z36AT-200

NBT Pipeline/Flow Through

TQFP

200/6.5

512K x 36

GS8160Z36AT-150

NBT Pipeline/Flow Through

TQFP

150/7.5

1M x 18

GS8160Z18AT-300I

NBT Pipeline/Flow Through

TQFP

300/5

1M x 18

GS8160Z18AT-250I

NBT Pipeline/Flow Through

TQFP

250/5.5

1M x 18

GS8160Z18AT-200I

NBT Pipeline/Flow Through

TQFP

200/6.5

1M x 18

GS8160Z18AT-150I

NBT Pipeline/Flow Through

TQFP

150/7.5

512K x 36

GS8160Z36AT-300I

NBT Pipeline/Flow Through

TQFP

300/5

512K x 36

GS8160Z36AT-250I

NBT Pipeline/Flow Through

TQFP

250/5.5

512K x 36

GS8160Z36AT-200I

NBT Pipeline/Flow Through

TQFP

200/6.5

512K x 36

GS8160Z36AT-150I

NBT Pipeline/Flow Through

TQFP

150/7.5

Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8160Z36AT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. T

= I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Rev: 1.03a 5/2003

23/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160Z18/36AT-300/250/200/150

Preliminary

18Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Page;Revisions;Reason

8160Z18A_r1

· Creation of new datasheet

8160Z18A_r1;

8160Z18A_r1_01

Content

· Updated FT power numbers
· Updated AC Characteristics table
· Updated ZZ recovery time diagram
· Updated AC Test Conditions table and removed Output Load

2 diagram

8160Z18A_r1_01;

8160Z18A_r1_02

Content

· Removed extraneous V

DDQ1

table on page 13 and changed

DDQ2

table to V

DDQ

· Removed pin locations from pin description table

GS8160ZxxA_r1_02;

GS8160ZxxA_r1_03

Content

· Entire datasheet rewritten due to design changes

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