Rev: 2.13a 9/2002
1/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8160Z18/36T-250/225/200/166/150/133
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAMTM, NoBLTM and
ZBTTM SRAMs
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
LBO pin for Linear or Interleave Burst mode
Pin compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
Functional Description
The GS8160Z18/36T is an 18Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8160Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8160Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
275
320
250
295
230
265
195
225
180
210
165
185
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Rev: 2.13a 9/2002
2/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
GS8160Z18T Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
FT
V
DD
V
DD
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
V
SS
V
DDQ
LB
O
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
16
A
6
A
7
E
1
E
2
NC
NC
B
B
B
A
E
3
CK
W
CKE
V
DD
V
SS
G
ADV
A
18
A
17
A
8
A
9
A
15
1M x 18
Top View
DQ
A9
A
19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.13a 9/2002
3/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
GS8160Z36T Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
V
DD
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
LB
O
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
16
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
W
CKE
V
DD
V
SS
G
ADV
A
18
A
17
A
8
A
9
A
15
512K x 36
Top View
DQ
B5
DQ
B9
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
DQ
A9
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
DQ
D9
DQ
C5
DQ
C9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.13a 9/2002
4/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
100-Pin TQFP Pin Descriptions
Symbol
Type
Description
A
0
, A
1
In
Burst Address Inputs; Preload the burst counter
A
2
A
18
In
Address Inputs
A
19
In
Address Input
CK
In
Clock Input Signal
B
A
In
Byte Write signal for data inputs DQ
A1
-DQ
A9
; active low
B
B
In
Byte Write signal for data inputs DQ
B1
-DQ
B9
; active low
B
C
In
Byte Write signal for data inputs DQ
C1
-DQ
C9
; active low
B
D
In
Byte Write signal for data inputs DQ
D1
-DQ
D9
; active low
W
In
Write Enable; active low
E
1
In
Chip Enable; active low
E
2
In
Chip Enable; Active High. For self decoded depth expansion
E
3
In
Chip Enable; Active Low. For self decoded depth expansion
G
In
Output Enable; active low
ADV
In
Advance/Load; Burst address counter control pin
CKE
In
Clock Input Buffer Enable; active low
NC
--
No Connect
DQ
A1
DQ
A9
I/O
Byte A Data Input and Output pins
DQ
B1
DQ
B9
I/O
Byte B Data Input and Output pins
DQ
C1
DQ
C9
I/O
Byte C Data Input and Output pins
DQ
D1
DQ
D9
I/O
Byte D Data Input and Output pins
ZZ
In
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
LBO
In
Linear Burst Order; active low
V
DD
In
Core power supply
V
SS
In
Ground
V
DDQ
In
Output driver power supply
Rev: 2.13a 9/2002
5/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
GS8160Z18/36 NBT SRAM Functional Block Diagram
K
SA
1
SA
0
Burst
Cou
n
ter
LBO
ADV
Memory
Array
E
3
E
2
E
1
G
W
B
D
B
C
B
B
B
A
CK
CKE
D
Q
FT
DQ
a
DQ
n
K
SA1'
SA0'
D
Q
Matc
h
W
r
ite
A
ddress
Regi
st
er 2
W
r
it
e A
ddre
s
s
Reg
i
s
t
er
1
Wr
i
t
e
D
a
t
a
Regist
er 2
W
r
ite Data
Regist
er
1
K
K
K
K
K
K
Se
nse Amps
Write Driver
s
Re
ad, W
r
ite an
d
Data Cohe
re
ncy
Contr
o
l Lo
gic
FT
A
0
An
Rev: 2.13a 9/2002
6/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E
1
, E
2,
and E
3
) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B
A
, B
B
, B
C,
& B
D
) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function
W
B
A
B
B
B
C
B
D
Read
H
X
X
X
X
Write Byte "a"
L
L
H
H
H
Write Byte "b"
L
H
L
H
H
Write Byte "c"
L
H
H
L
H
Write Byte "d"
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H
Rev: 2.13a 9/2002
7/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Synchronous Truth Table
Operation
Type Address E
1
E
2
E
3
ZZ ADV W Bx G CKE CK
DQ
Notes
Deselect Cycle, Power Down
D
None
H
X
X
L
L
X
X
X
L
L-H High-Z
Deselect Cycle, Power Down
D
None
X
X
H
L
L
X
X
X
L
L-H High-Z
Deselect Cycle, Power Down
D
None
X
L
X
L
L
X
X
X
L
L-H High-Z
Deselect Cycle, Continue
D
None
X
X
X
L
H
X
X
X
L
L-H High-Z
1
Read Cycle, Begin Burst
R
External
L
H
L
L
L
H
X
L
L
L-H
Q
Read Cycle, Continue Burst
B
Next
X
X
X
L
H
X
X
L
L
L-H
Q
1,10
NOP/Read, Begin Burst
R
External
L
H
L
L
L
H
X
H
L
L-H High-Z
2
Dummy Read, Continue Burst
B
Next
X
X
X
L
H
X
X
H
L
L-H High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L
H
L
L
L
L
L
X
L
L-H
D
3
Write Cycle, Continue Burst
B
Next
X
X
X
L
H
X
L
X
L
L-H
D
1,3,10
NOP/Write Abort, Begin Burst
W
None
L
H
L
L
L
L
H
X
L
L-H High-Z
2,3
Write Abort, Continue Burst
B
Next
X
X
X
L
H
X
H
X
L
L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall
Current
X
X
X
L
X
X
X
X
H
L-H
-
4
Sleep Mode
None
X
X
X
H
X
X
X
X
X
X
High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 2.13a 9/2002
8/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Deselect
New Read
New Write
Burst Read
Burst Write
W
R
B
R
B
W
D
D
B
B
W
R
D
B
W
R
D
D
Pipeline and Flow Through Read Write Control State Diagram
Current State (n)
Next State (n+1)
Transition
Input Command Code
Key
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B and D represent input command
codes ,as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State
Next State
n
n+1
n+2
n+3
Current State and Next State Definition for
Pipeline and Flow Through Read/Write Control State Diagram
W
R
Rev: 2.13a 9/2002
9/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Pipeline Mode Data I/O State Diagram
Current State (n)
Next State (n+2)
Transition
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Intermediate
n
n+1
n+2
n+3
Current State and Next State Definition for
Pipeline Mode Data I/O State Diagram
Next State
State
Rev: 2.13a 9/2002
10/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Current State (n)
Next State (n+1)
Transition
Input Command Code
Key
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B and D represent input command
codes as indicated in the Truth Tables.
Flow Through Mode Data I/O State Diagram
Clock (CK)
Command
Current State
Next State
n
n+1
n+2
n+3
Current State and Next State Definition for:
Pipeline and Flow Through Read Write Control State Diagram
Rev: 2.13a 9/2002
11/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Note:
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Power Down Control
ZZ
L or NC
Active
H
Standby, I
DD
= I
SB
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Rev: 2.13a 9/2002
12/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V
DD
or V
DDQ
on pipelined parts and V
SS
on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
CK
ZZ
tZZR
tZZH
tZZS
~ ~
~ ~
Sleep
~ ~
~ ~
~ ~
Rev: 2.13a 9/2002
13/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Absolute Maximum Ratings
(All voltages reference to V
SS
)
Symbol
Description
Value
Unit
V
DD
Voltage on V
DD
Pins
0.5 to 4.6
V
V
DDQ
Voltage in V
DDQ
Pins
0.5 to 4.6
V
V
CK
Voltage on Clock Input Pin
0.5 to 6
V
V
I/O
Voltage on I/O Pins
0.5 to V
DDQ
+0.5 (
4.6 V max.)
V
V
IN
Voltage on Other Input Pins
0.5 to V
DD
+0.5 (
4.6 V max.)
V
I
IN
Input Current on Any Pin
+/20
mA
I
OUT
Output Current on Any I/O Pin
+/20
mA
P
D
Package Power Dissipation
1.5
W
T
STG
Storage Temperature
55 to 125
o
C
T
BIAS
Temperature Under Bias
55 to 125
o
C
Rev: 2.13a 9/2002
14/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
3.3 V Supply Voltage
V
DD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
V
DD2
2.3
2.5
2.7
V
3.3 V V
DDQ
I/O Supply Voltage
V
DDQ3
3.0
3.3
3.6
V
2.5 V V
DDQ
I/O Supply Voltage
V
DDQ2
2.3
2.5
2.7
V
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
V
DDQ3
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
2.0
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.8
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
2.0
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.8
V
1,3
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3.
V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
V
DDQ2
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
0.6*V
DD
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.3*V
DD
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
0.6*V
DD
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.3*V
DD
V
1,3
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3.
V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
Rev: 2.13a 9/2002
15/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Note: These parameters are sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
T
A
0
25
70
C
2
Ambient Temperature (Industrial Range Versions)
T
A
40
25
85
C
2
Note:
1.
The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2.
Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Capacitance
(T
A
= 25
o
C, f = 1 MH
Z
, V
DD
= 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
C
IN
V
IN
= 0 V
4
5
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0 V
6
7
pF
Package Thermal Characteristics
Rating
Layer Board
Symbol
Max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
R
JA
40
C/W
1,2
Junction to Ambient (at 200 lfm)
four
R
JA
24
C/W
1,2
Junction to Case (TOP)
--
R
JC
9
C/W
3
20% tKC
V
SS
2.0 V
50%
V
SS
V
IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
V
DD
+ 2.0 V
50%
V
DD
V
IL
Rev: 2.13a 9/2002
16/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
AC Test Conditions
Parameter
Conditions
Input high level
V
DD
0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DD
/2
Output reference level
V
DDQ
/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
1 uA
1 uA
ZZ Input Current
I
IN1
V
DD
V
IN
V
IH
0 V
V
IN
V
IH
1 uA
1 uA
1 uA
100 uA
FT Input Current
I
IN2
V
DD
V
IN
V
IL
0 V
V
IN
V
IL
100 uA
1 uA
1 uA
1 uA
Output Leakage Current
I
OL
Output Disable, V
OUT
= 0 to V
DD
1 uA
1 uA
Output High Voltage
V
OH2
I
OH
= 8 mA, V
DDQ
= 2.375 V
1.7 V
--
Output High Voltage
V
OH3
I
OH
= 8 mA, V
DDQ
= 3.135 V
2.4 V
--
Output Low Voltage
V
OL
I
OL
= 8 mA
--
0.4 V
DQ
V
DDQ/2
50
30pF
*
Output Load 1
* Distributed Test Jig Capacitance
Rev: 2.13a 9/2002
17/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS18/36-250/225/200/166/150/133
O
p
er
at
ing C
u
rrent
s
Notes:
1.
I
DD
an
d I
DDQ
apply to any combination of V
DD3
, V
DD2
, V
DD
Q
3
, and V
DDQ2
operation.
2.
All p
a
rameters listed are worst case scenario.
Par
a
meter
T
est
Co
nd
itio
ns
Mo
de
Sym
b
o
l
-250
-225
-200
-166
-150
-133
Un
it
0
to
70C
40
to
85C
0
to
70C
40
to
85C
0
to
70C
40
to
85C
0
to
70
C
40
to
85C
0
to
70C
40
to
85C
0
to
70C
40
to
85C
Operating
Current
3.3 V
Devi
ce Selec
t
ed;
All o
t
her
inpu
ts
V
IH
o
r
V
IL
Output
o
pen
(x32/
x
36)
Pipeline
I
DD
I
DD
Q
29
0
40
300
40
265
35
275
35
240
30
250
30
205
25
215
25
190
25
20
0
25
170
20
180
20
mA
Flow
Through
I
DD
I
DD
Q
18
0
20
190
20
170
20
180
20
165
15
175
15
155
15
165
15
150
15
16
0
15
140
10
150
10
mA
(x18)
Pipeline
I
DD
I
DD
Q
26
0
20
270
20
235
20
245
20
215
15
225
15
185
15
195
15
170
15
18
0
15
155
10
165
10
mA
Flow
Through
I
DD
I
DD
Q
16
5
10
175
10
155
10
165
10
150
10
160
10
140
10
150
10
135
10
14
5
10
125
10
135
10
mA
Operating
Current
2.5 V
Devi
ce Selec
t
ed;
All o
t
her
inpu
ts
V
IH
o
r
V
IL
Output
o
pen
(x32/
x
36)
Pipeline
I
DD
I
DD
Q
29
0
30
300
30
265
30
275
30
240
25
250
25
205
20
215
20
190
20
20
0
20
170
15
180
15
mA
Flow
Through
I
DD
I
DD
Q
18
0
20
190
20
170
20
180
20
165
15
175
15
155
15
165
15
150
15
16
0
15
140
10
150
10
mA
(x18)
Pipeline
I
DD
I
DD
Q
26
0
15
270
15
235
15
245
15
215
15
225
15
185
10
195
10
170
10
18
0
10
155
10
165
10
mA
Flow
Through
I
DD
I
DD
Q
16
5
10
175
10
155
10
165
10
150
10
160
10
140
10
150
10
135
10
14
5
10
125
10
135
10
mA
Standby
Current
ZZ
V
DD
0.2 V
--
Pipeline
I
SB
2
0
30
20
30
20
30
20
30
20
3
0
20
30
mA
Flow
Through
I
SB
2
0
30
20
30
20
30
20
30
20
3
0
20
30
mA
Des
e
lect
Current
Dev
i
ce D
e
selected;
All o
t
her
inpu
ts
V
IH
or
V
IL
--
Pipeline
I
DD
8
5
90
80
85
75
80
64
70
60
6
5
50
55
mA
Flow
Through
I
DD
6
0
65
60
65
50
55
50
55
50
5
5
45
50
mA
Rev: 2.13a 9/2002
18/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Parameter
Symbol
-250
-225
-200
-166
-150
-133
Unit
Min
Max
Min
Max
Min
Max
Min
Max Min Max Min Max
Pipeline
Clock Cycle Time
tKC
4.0
--
4.4
--
5.0
--
6.0
--
6.7
--
7.5
--
ns
Clock to Output Valid
tKQ
--
2.5
--
2.7
--
3.0
--
3.4
--
3.8
--
4.0
ns
Clock to Output Invalid
tKQX
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Clock to Output in Low-Z
tLZ
1
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Setup time
tS
1.2
--
1.3
--
1.4
--
1.5
--
1.5
--
1.5
--
ns
Hold time
tH
0.2
--
0.3
--
0.4
--
0.5
--
0.5
--
0.5
--
ns
Flow
Through
Clock Cycle Time
tKC
5.5
--
6.0
--
6.5
--
7.0
--
7.5
--
8.5
--
ns
Clock to Output Valid
tKQ
--
5.5
--
6.0
--
6.5
--
7.0
--
7.5
--
8.5
ns
Clock to Output Invalid
tKQX
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
ns
Clock to Output in Low-Z
tLZ
1
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
ns
Setup time
tS
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Hold time
tH
0.5
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
--
ns
Clock HIGH Time
tKH
1.3
--
1.3
--
1.3
--
1.3
--
1.5
--
1.7
--
ns
Clock LOW Time
tKL
1.5
--
1.5
--
1.5
--
1.5
--
1.7
--
2
--
ns
Clock to Output in
High-Z
tHZ
1
1.5 2.3
1.5 2.5
1.5 3.0
1.5
3.0
1.5 3.0
1.5 3.0
ns
G to Output Valid
tOE
--
2.3
--
2.5
--
3.2
--
3.5
--
3.8
--
4.0
ns
G to output in Low-Z
tOLZ
1
0
--
0
--
0
--
0
--
0
--
0
--
ns
G to output in High-Z
tOHZ
1
--
2.3
--
2.5
--
3.0
--
3.0
--
3.0
--
3.0
ns
ZZ setup time
tZZS
2
5
--
5
--
5
--
5
--
5
--
5
--
ns
ZZ hold time
tZZH
2
1
--
1
--
1
--
1
--
1
--
1
--
ns
ZZ recovery
tZZR
20
--
20
--
20
--
20
--
20
--
20
--
ns
Rev: 2.13a 9/2002
19/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Pipeline Mode Read/Write Cycle Timing
*Note: E = High (False) if E
1
= 1 or E
2
= 0 or E
3
= 1
tH
tS
tH
CK
CKE
E*
ADV
tKH
W
tKL
tKC
tS
Bn
A
0
An
A1
tH
tS
A2
A3
D(A1)
D(A2)
Q(A3)
Q
Q(A6)
tH
tS
D
D(A5)
tKQLZ
tKQ
tKQHZ
tOEHZ
tOELZ
tKQX
tKHQZ
tGLQV
G
1
2
3
4
5
6
7
8
9
10
COMMAND
Write
D(A1)
Write
D(A2)
BURST
Write
D(A2+1)
Read
Q(A3)
Read
Q(A4)
BURST
Read
Q(A4+1)
Write
D(A5)
Read
Q(A6)
Write
D(A7)
DESELECT
DON'T CARE
UNDEFINED
DQ
A
DQ
D
tH
tS
tH
tS
tH
tS
A4
A5
A6
A7
Q(A4)
(A4+1)
(A2+1)
Rev: 2.13a 9/2002
20/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Pipeline Mode No-Op, Stall and Deselect Timing
*Note: E = High (False) if E
1
= 1 or E
2
= 0 or E
3
= 1
CK
CKE
E
*
ADV
W
Bn
A
0
An
A1
A5
D(A1)
Q(A2)
Q(A3)
Q(A5)
DQ
1
2
3
4
5
6
7
8
9
10
COMMAND
Write
D(A1)
Read
Q(A2)
STALL
Read
Q(A3)
Write
D(A4)
STALL
NOP
Read
Q(A5)
CONTINUE
DON'T CARE
UNDEFINED
D(A4)
tKHQZ
tKQHZ
DESELECT
DESELECT
tH
tS
A2
A3
A4
tH
tS
tH
tS
tH
tS
Rev: 2.13a 9/2002
21/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Flow Through Mode Read/Write Cycle Timing
*Note: E = High (False) if E
1
= 1 or E
2
= 0 or E
3
= 1
CK
CKE
E*
ADV
tKH
W
tKL
tKC
Bn
A
0
An
tH
tS
A7
DQ
1
2
3
4
5
6
7
8
9
10
COMMAND
Write
D(A1)
Write
D(A2)
BURST
Write
D(A2+1)
Read
Q(A3)
Read
Q(A4)
BURST
Read
Q(A4+1)
Write
D(A5)
Read
Q(A6)
Write
D(A7)
DESELECT
DON'T CARE
UNDEFINED
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
A1
A2
A3
A4
A5
A6
D(A1)
D(A2)
Q(A3)
Q
Q(A6)
tH
tS
D
D(A5)
tKQLZ
tKQ
tKQHZ
tOEHZ
tOELZ
tKQX
tKHQZ
tGLQV
Q(A4)
(A4+1)
(A2+1)
G
Rev: 2.13a 9/2002
22/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Flow Through Mode No-Op, Stall and Deselect Timing
*Note: E = High (False) if E
1
= 1 or E
2
= 0 or E
3
= 1
CK
CKE
E
*
ADV
W
Bn
A
0
An
Q(A5)
DQ
1
2
3
4
5
6
7
8
9
10
COMMAND
Write
D(A1)
Read
Q(A2)
STALL
Read
Q(A3)
Write
D(A4)
STALL
NOP
Read
Q(A5)
CONTINUE
DON'T CARE
UNDEFINED
D(A4)
tKHQZ
tKQHZ
DESELECT
DESELECT
D(A1)
Q(A2)
Q(A3)
A1
A5
A2
A3
A4
tH
tS
tH
tS
tH
tS
Rev: 2.13a 9/2002
23/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
TQFP Package Drawing
BPR 1999.05.18
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol
Description
Min. Nom. Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
--
0.20
D
Terminal Dimension
21.9
22.0
20.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
--
0.65
--
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
--
1.00
--
Y
Coplanarity
--
--
0.10
Lead Angle
0
--
7
Rev: 2.13a 9/2002
24/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Ordering Information--GSI NBT Synchronous SRAM
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
Status
1M x 18
GS8160Z18T-250
NBT Pipeline/Flow Through
TQFP
250/5.5
C
1M x 18
GS8160Z18T-225
NBT Pipeline/Flow Through
TQFP
225/6
C
1M x 18
GS8160Z18T-200
NBT Pipeline/Flow Through
TQFP
200/6.5
C
1M x 18
GS8160Z18T-166
NBT Pipeline/Flow Through
TQFP
166/7
C
1M x 18
GS8160Z18T-150
NBT Pipeline/Flow Through
TQFP
150/7.5
C
1M x 18
GS8160Z18T-133
NBT Pipeline/Flow Through
TQFP
133/8.5
C
512K x 36
GS8160Z36T-250
NBT Pipeline/Flow Through
TQFP
250/5.5
C
512K x 36
GS8160Z36T-225
NBT Pipeline/Flow Through
TQFP
225/6
C
512K x 36
GS8160Z36T-200
NBT Pipeline/Flow Through
TQFP
200/6.5
C
512K x 36
GS8160Z36T-166
NBT Pipeline/Flow Through
TQFP
166/7
C
512K x 36
GS8160Z36T-150
NBT Pipeline/Flow Through
TQFP
150/7.5
C
512K x 36
GS8160Z36T-133
NBT Pipeline/Flow Through
TQFP
133/8.5
C
1M x 18
GS8160Z18T-250I
NBT Pipeline/Flow Through
TQFP
250/5.5
I
1M x 18
GS8160Z18T-225I
NBT Pipeline/Flow Through
TQFP
225/6
I
1M x 18
GS8160Z18T-200I
NBT Pipeline/Flow Through
TQFP
200/6.5
I
1M x 18
GS8160Z18T-166I
NBT Pipeline/Flow Through
TQFP
166/7
I
1M x 18
GS8160Z18T-150I
NBT Pipeline/Flow Through
TQFP
150/7.5
I
1M x 18
GS8160Z18T-133I
NBT Pipeline/Flow Through
TQFP
133/8.5
I
512K x 36
GS8160Z36T-250I
NBT Pipeline/Flow Through
TQFP
250/5.5
I
512K x 36
GS8160Z36T-225I
NBT Pipeline/Flow Through
TQFP
225/6
I
512K x 36
GS8160Z36T-200I
NBT Pipeline/Flow Through
TQFP
200/6.5
I
512K x 36
GS8160Z36T-166I
NBT Pipeline/Flow Through
TQFP
166/7
I
512K x 36
GS8160Z36T-150I
NBT Pipeline/Flow Through
TQFP
150/7.5
I
512K x 36
GS8160Z36T-133I
NBT Pipeline/Flow Through
TQFP
133/8.5
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816Z36-166IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 2.13a 9/2002
25/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
GS18/36 1.00 9/1999A;GS18/
362.0012/1999B
Content
Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master
File Rev B
Added x72 Pinout.
GS18/362.00 12/1999BGS18/
362.01 1/2000C
Format
Added new GSI Logo
GS18/362.0 1/2000DGS18/
362.03 2/2000E
Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O
supply; Completeness
Absolute Maximum Ratings; Changed VDDQ - Value: From: -.05 to
VDD : to : -.05 to 3.6; Completeness.
Recommended Operating Conditions;Changed: I/O Supply Voltage-
Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to
3.6; Same page - took out Note 1;Completeness
Electrical Characteristics - Added second Output High Voltage line to
table; completeness.
Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
GS18/362.03 2/2000E;
8160Z18_r2_04
Content
Removed pin 14 from V
SS
in pin description table.
ADV changed to pin 85 in pin description table.
8160Z18_r2_04;
8160Z18_r2_05
Content
Changed the value of ZZ recovery in the AC Electrical Characteristics
table on page 17 from 20 ns to 100 ns
8160Z18_r2_05;
8160Z18_r2_06
Content
Added 225 MHz speed bin
Updated Pg. 1 table, AC Characteristics table, and Operating Cur-
rents table to match 815xxx
Updated format to comply with Technical Publications standards
8160Z18_r2_06;
8160Z18_r2_07
Content
Updated Capitance table--removed Input row and changed Output
row to I/O
8160Z18_r2_07;
8160Z18_r2_08
Content
Updated Features list on page 1
Completely reworked table on page 1
Updated Mode Pin Functions table on page 11
8160Z18_r2_08;
8160Z18_r2_09
Content
Added 3.3 V references to entire document
Updated Operating Conditions table
Updated Operating Currents table and added note
Update table on page 1; added power numbers
8160Z18_r2_09;
8160Z18_r2_10
Content
Updated DQ on page 19
Updated DQ on page 21
Updated Pin Description table
Updated Operating Currents table
Updated table on page 1; updated power numbers
Updated Recommended Operating Conditions table (added
V
DDQ
references)
Rev: 2.13a 9/2002
26/26
1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
8160Z18_r2_10;
8160Z18_r2_11
Content
Updated table on page 1
Created recommended operating conditions tables on pages
13 and 14
Updated AC Electrical Characteristics table
Updated Ordering Information for 225 MHz part (changed
from 7ns to 6.5 ns)
Added 250 MHz speed bin
Deleted 180 MHz speed bin
8160Z18_r2_11;
8160Z18_r2_12
Content
Updated AC Characteristics table
Updated FT power numbers
Updated ZZ recovery time diagram
Updated Mb references from 16Mb to 18Mb
Updated AC Test Conditions table and removed Output Load
2 diagram
8160Z18_r2_12;
8160Z18_r2_13
Content
Removed Preliminary banner
Removed pin locations from pin description table
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
PDF 
ZIP