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Электронный компонент: GS8161Z18BT-200

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GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Commercial Temp
Industrial Temp
Preliminary
Rev: 1.00 9/2004
1/37
2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
Fully pin-compatible with both pipelined and flow through
NtRAMTM, NoBLTM and ZBTTM SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
2.5 V or 3.3 V +10%/10% core power supply
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ pin for automatic power-down
JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
packages
Pb-Free 100-lead TQFP package available
Functional Description
The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
is implemented with GSI's high performance CMOS
technology and is available in JEDEC-standard 100-pin TQFP
and 165-bump FP-BGA packages.
Parameter Synopsis
-250
-200
-150
Unit
Pipeline
3-1-1-1
t
KQ
(x18/x36)
tCycle
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
Curr
(x18)
Curr
(x32/x36)
280
330
230
270
185
210
mA
mA
Flow Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Curr
(x18)
Curr
(x32/x36)
210
240
185
205
170
190
mA
mA
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
2/37
2004, GSI Technology
GS8161Z18BT Pinout (Package T)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
FT
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
LBO
A
A
A
A
A
1
A
0
TM
S
TDI
V
SS
V
DD
TD
O
TCK
A
A
A
A
A
A
A
A
E
1
E
2
NC
NC
B
B
B
A
E
3
CK
W
CKE
V
DD
V
SS
G
AD
V
A
A
A
A
A
1M x 18
Top View
DQP
A
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
3/37
2004, GSI Technology
GS8161Z36BT Pinout (Package T)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
FT
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
LBO
A
A
A
A
A
1
A
0
TM
S
TD
I
V
SS
V
DD
TDO
TCK
A
A
A
A
A
A
A
A
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
W
CKE
V
DD
V
SS
G
AD
V
A
A
A
A
A
512K x 36
Top View
DQ
B
DQP
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
DQ
C
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
DQP
D
DQ
C
DQP
C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
4/37
2004, GSI Technology
100-Pin TQFP Pin Descriptions
Symbol
Type
Description
A
0
, A
1
In
Burst Address Inputs; Preload the burst counter
A
In
Address Inputs
CK
In
Clock Input Signal
B
A
In
Byte Write signal for data inputs DQ
A1
DQ
A9
; active low
B
B
In
Byte Write signal for data inputs DQ
B1
DQ
B9
; active low
B
C
In
Byte Write signal for data inputs DQ
C1
DQ
C9
; active low
B
D
In
Byte Write signal for data inputs DQ
D1
DQ
D9
; active low
W
In
Write Enable; active low
E
1
In
Chip Enable; active low
E
2
In
Chip Enable--Active High. For self decoded depth expansion
E
3
In
Chip Enable--Active Low. For self decoded depth expansion
G
In
Output Enable; active low
ADV
In
Advance/Load; Burst address counter control pin
CKE
In
Clock Input Buffer Enable; active low
NC
--
No Connect
DQ
A
I/O
Byte A Data Input and Output pins
DQ
B
I/O
Byte B Data Input and Output pins
DQ
C
I/O
Byte C Data Input and Output pins
DQ
D
I/O
Byte D Data Input and Output pins
ZZ
In
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
LBO
In
Linear Burst Order; active low.
TMS
Scan Test Mode Select
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
5/37
2004, GSI Technology
TDI
Scan Test Data In
TDO
Scan Test Data Out
TCK
Scan Test Clock
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
V
DD
In
Core power supply
V
SS
In
Ground
V
DDQ
In
Output driver power supply
100-Pin TQFP Pin Descriptions
Symbol
Type
Description
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
6/37
2004, GSI Technology
165 Bump BGA--x18 Commom I/O--Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BB
NC
E3
CKE
ADV
A
A
A
A
B
NC
A
E2
NC
BA
CK
W
G
A
A
NC
B
C
NC
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPA
C
D
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
D
E
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
E
F
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
F
G
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
G
H
FT
MCH
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
ZZ
H
J
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
J
K
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
K
L
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
L
M
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
M
N
DQPB
NC
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
NC
N
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
NC
P
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
7/37
2004, GSI Technology
165 Bump BGA--x32 Common I/O--Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
CKE
ADV
A
A
NC
A
B
NC
A
E2
BD
BA
CK
W
G
A
A
NC
B
C
NC
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
NC
C
D
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
D
E
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
E
F
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
F
G
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
G
H
FT
MCH
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
ZZ
H
J
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
J
K
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
K
L
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
L
M
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
M
N
NC
NC
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
NC
N
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
NC
P
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
8/37
2004, GSI Technology
165 Bump BGA--x36 Common I/O--Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
CKE
ADV
A
A
NC
A
B
NC
A
E2
BD
BA
CK
W
G
A
A
NC
B
C
DQPC
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPB
C
D
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
D
E
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
E
F
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
F
G
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
G
H
FT
MCH
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
ZZ
H
J
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
J
K
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
K
L
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
L
M
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
M
N
DQPD
NC
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
DQPA
N
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
NC
P
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
9/37
2004, GSI Technology
GS8161Z18/32/36BD 165-Bump BGA Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
DQ
A
DQ
B
DQ
C
DQ
D
I/O
Data Input and Output pins
B
A
, B
B
, B
C
, B
D
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
NC
--
No Connect
CK
I
Clock Input Signal; active high
CKE
I
Clock Input Buffer Enable; active low
W
I
Write Enable; active low
E
1
I
Chip Enable; active low
E
3
I
Chip Enable; active low
E
2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active high
ZZ
I
Sleep mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
MCH
--
Must Connect High
V
DD
I
Core power supply
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
10/37
2004, GSI Technology
GS8161Z18/32/36B NBT SRAM Functional Block Diagram
K
18
SA1
SA0
Burs
t
Counter
LBO
ADV
Memory
Ar
ra
y
G
CK
CKE
D Q
FT
DQ
aDQ
n
K
SA1'
SA0'
D
Q
Match
W
r
it
e Addr
ess
Regist
er 2
W
r
it
e Add
r
ess
Regist
er 1
W
r
ite Da
t
a
Regist
er 2
W
r
ite
Dat
a
Regist
er 1
K
K
K
K
K
K
Se
nse Amps
Write Driver
s
Re
ad
, W
r
it
e an
d
Da
t
a
Co
he
re
nc
y
Co
ntro
l L
ogic
FT
A
0
An
E
3
E
2
E
1
W
B
D
B
C
B
B
B
A
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
11/37
2004, GSI Technology
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E
1
, E
2,
and E
3
) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is asserted low, and the write input is sampled low at the rising edge of
clock. The Byte Write Enable inputs (B
A
, B
B
, B
C
& B
D
) determine which bytes will be written. All or none may be activated. A
write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function
W
B
A
B
B
B
C
B
D
Read
H
X
X
X
X
Write Byte "a"
L
L
H
H
H
Write Byte "b"
L
H
L
H
H
Write Byte "c"
L
H
H
L
H
Write Byte "d"
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
12/37
2004, GSI Technology
Synchronous Truth Table
Operation
Type Address CK CKE ADV W Bx E
1
E
2
E
3
G ZZ
DQ
Notes
Read Cycle, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
L
L
Q
Read Cycle, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
L
L
Q
1,10
NOP/Read, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
H
L
High-Z
2
Dummy Read, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
H
L
High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L-H
L
L
L
L
L
H
L
X
L
D
3
Write Cycle, Continue Burst
B
Next
L-H
L
H
X
L
X
X
X
X
L
D
1,3,10
Write Abort, Continue Burst
B
Next
L-H
L
H
X
H
X
X
X
X
L
High-Z 1,2,3,10
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
H
X
X
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
X
H
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
L
X
X
L
High-Z
Deselect Cycle
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
1
Deselect Cycle, Continue
D
None
L-H
L
H
X
X
X
X
X
X
L
High-Z
1
Sleep Mode
None
X
X
X
X
X
X
X
X
X
H
High-Z
Clock Edge Ignore, Stall
Current
L-H
H
X
X
X
X
X
X
X
L
-
4
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
13/37
2004, GSI Technology
Pipelined and Flow Through Read Write Control State Diagram
Deselect
New Read
New Write
Burst Read
Burst Write
W
R
B
R
B
W
D
D
B
B
W
R
D
B
W
R
D
D
Current State (n)
Next State (n+1)
Transition
Input Command Code
Key
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State
Next State
n
n+1
n+2
n+3
Current State and Next State Definition for
Pipelined and Flow Through Read/Write Control State Diagram
W
R
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
14/37
2004, GSI Technology
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Current State (n)
Next State (n+2)
Transition
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Intermediate
n
n+1
n+2
n+3
Current State and Next State Definition for
Pipeline Mode Data I/O State Diagram
Next State
State
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
15/37
2004, GSI Technology
Flow Through Mode Data I/O State Diagram
High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Current State (n)
Next State (n+1)
Transition
Input Command Code
Key
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Next State
n
n+1
n+2
n+3
Current State and Next State Definition for:
Pipeline and Flow through Read Write Control State Diagram
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
16/37
2004, GSI Technology
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, I
DD
= I
SB
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
17/37
2004, GSI Technology
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V
DD
or V
DDQ
on pipelined parts and V
SS
on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
tZZR
tZZH
tZZS
tKL
tKL
tKH
tKH
tKC
tKC
CK
ZZ
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
18/37
2004, GSI Technology
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Absolute Maximum Ratings
(All voltages reference to V
SS
)
Symbol
Description
Value
Unit
V
DD
Voltage on V
DD
Pins
0.5 to 4.6
V
V
DDQ
Voltage in V
DDQ
Pins
0.5 to 4.6
V
V
I/O
Voltage on I/O Pins
0.5 to V
DDQ
+0.5 (
4.6 V max.)
V
V
IN
Voltage on Other Input Pins
0.5 to V
DD
+0.5 (
4.6 V max.)
V
I
IN
Input Current on Any Pin
+/20
mA
I
OUT
Output Current on Any I/O Pin
+/20
mA
P
D
Package Power Dissipation
1.5
W
T
STG
Storage Temperature
55 to 125
o
C
T
BIAS
Temperature Under Bias
55 to 125
o
C
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
3.3 V Supply Voltage
V
DD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
V
DD2
2.3
2.5
2.7
V
3.3 V V
DDQ
I/O Supply Voltage
V
DDQ3
3.0
3.3
3.6
V
2.5 V V
DDQ
I/O Supply Voltage
V
DDQ2
2.3
2.5
2.7
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
19/37
2004, GSI Technology
V
DDQ3
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
2.0
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.8
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
2.0
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.8
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
V
DDQ2
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
0.6*V
DD
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.3*V
DD
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
0.6*V
DD
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.3*V
DD
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
T
A
0
25
70
C
2
Ambient Temperature (Industrial Range Versions)
T
A
40
25
85
C
2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
20/37
2004, GSI Technology
Note:
These parameters are sample tested.
Capacitance
(T
A
= 25
o
C, f = 1 MH
Z
, V
DD
= 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
C
IN
V
IN
= 0 V
4
5
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0 V
6
7
pF
AC Test Conditions
Parameter
Conditions
Input high level
V
DD
0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DD
/2
Output reference level
V
DDQ
/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
50% tKC
V
SS
2.0 V
50%
V
SS
V
IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
50% tKC
V
DD
+ 2.0 V
50%
V
DD
V
IL
DQ
V
DDQ/2
50
30pF
*
Output Load 1
* Distributed Test Jig Capacitance
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
21/37
2004, GSI Technology
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
1 uA
1 uA
ZZ Input Current
I
IN1
V
DD
V
IN
V
IH
0 V
V
IN
V
IH
1 uA
1 uA
1 uA
100 uA
FT Input Current
I
IN2
V
DD
V
IN
V
IL
0 V
V
IN
V
IL
100 uA
1 uA
1 uA
1 uA
Output Leakage Current
I
OL
Output Disable, V
OUT
= 0 to V
DD
1 uA
1 uA
Output High Voltage
V
OH2
I
OH
= 8 mA, V
DDQ
= 2.375 V
1.7 V
--
Output High Voltage
V
OH3
I
OH
= 8 mA, V
DDQ
= 3.135 V
2.4 V
--
Output Low Voltage
V
OL
I
OL
= 8 mA
--
0.4 V
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
22/37
2004, GSI Technology
Notes:
1. I
DD
and I
DDQ
apply to any combination of V
DD3
, V
DD2
, V
DDQ3
, and V
DDQ2
operation.
2. All parameters listed are worst case scenario.
Operating Currents
Parameter
Test Conditions
Mode
Symbol
-250
-200
-150
Unit
0
to
70C
40
to
85C
0
to
70C
40
to
85C
0
to
70C
40
to
85C
Operating
Current
Device Selected;
All other inputs
V
IH
or
V
IL
Output open
(x32/
x36)
Pipeline
I
DD
I
DDQ
290
40
300
40
240
30
250
30
190
20
200
20
mA
Flow Through
I
DD
I
DDQ
220
20
230
20
190
15
200
15
175
15
185
15
mA
(x18)
Pipeline
I
DD
I
DDQ
260
20
270
20
215
15
225
15
170
15
180
15
mA
Flow Through
I
DD
I
DDQ
200
10
210
10
175
10
185
10
160
10
170
10
mA
Standby
Current
ZZ
V
DD
0.2 V
--
Pipeline
I
SB
40
50
40
50
40
50
mA
Flow Through
I
SB
40
50
40
50
40
50
mA
Deselect
Current
Device Deselected;
All other inputs
V
IH
or
V
IL
--
Pipeline
I
DD
85
90
75
80
60
65
mA
Flow Through
I
DD
60
65
50
55
50
55
mA
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
23/37
2004, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter
Symbol
-250
-200
-150
Unit
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
4.0
--
5.0
--
6.7
--
ns
Clock to Output Valid
tKQ
--
2.5
--
3.0
--
3.8
ns
Clock to Output Invalid
tKQX
1.5
--
1.5
--
1.5
--
ns
Clock to Output in Low-Z
tLZ
1
1.5
--
1.5
--
1.5
--
ns
Setup time
tS
1.2
--
1.4
--
1.5
--
ns
Hold time
tH
0.2
--
0.4
--
0.5
--
ns
Flow Through
Clock Cycle Time
tKC
5.5
--
6.5
--
7.5
--
ns
Clock to Output Valid
tKQ
--
5.5
--
6.5
--
7.5
ns
Clock to Output Invalid
tKQX
2.0
--
2.0
--
2.0
--
ns
Clock to Output in Low-Z
tLZ
1
2.0
--
2.0
--
2.0
--
ns
Setup time
tS
1.5
--
1.5
--
1.5
--
ns
Hold time
tH
0.5
--
0.5
--
0.5
--
ns
Clock HIGH Time
tKH
1.3
--
1.3
--
1.5
--
ns
Clock LOW Time
tKL
1.5
--
1.5
--
1.7
--
ns
Clock to Output in
High-Z
tHZ
1
1.5 2.5
1.5 3.0
1.5 3.0
ns
G to Output Valid
tOE
--
2.5
--
3.0
--
3.8
ns
G to output in Low-Z
tOLZ
1
0
--
0
--
0
--
ns
G to output in High-Z
tOHZ
1
--
2.5
--
3.0
--
3.8
ns
ZZ setup time
tZZS
2
5
--
5
--
5
--
ns
ZZ hold time
tZZH
2
1
--
1
--
1
--
ns
ZZ recovery
tZZR
20
--
20
--
20
--
ns
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
24/37
2004, GSI Technology
Pipeline Mode Timing (NBT)
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
Deselect
D(A)
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKL
tKC
tKL
tKH
tKH
A
B
C
D
E
F
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E*
ADV
W
Bn
A0An
DQaDQd
G
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
25/37
2004, GSI Technology
Flow Through Mode Timing (NBT)
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
DD
. The JTAG output
drivers are powered by V
DDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
D(A)
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
tKQX
tKQ
tLZ
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKC
tKL
tKL
tKH
tKH
A
B
C
D
E
F
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E*
ADV
W
Bn
A0An
DQ
G
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
26/37
2004, GSI Technology
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI
Test Data In
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO
Test Data Out
Out
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
27/37
2004, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x36
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x18
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0 0 1 1 0 1 1 0 0 1
1
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
108
1
0
Control Signals
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
28/37
2004, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
29/37
2004, GSI Technology
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
30/37
2004, GSI Technology
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
31/37
2004, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
V
IHJ3
2.0
V
DD3
+0.3
V
1
3.3 V Test Port Input Low Voltage
V
ILJ3
0.3
0.8
V
1
2.5 V Test Port Input High Voltage
V
IHJ2
0.6 * V
DD2
V
DD2
+0.3
V
1
2.5 V Test Port Input Low Voltage
V
ILJ2
0.3
0.3 * V
DD2
V
1
TMS, TCK and TDI Input Leakage Current
I
INHJ
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
I
INLJ
1
100
uA
3
TDO Output Leakage Current
I
OLJ
1
1
uA
4
Test Port Output High Voltage
V
OHJ
1.7
--
V
5, 6
Test Port Output Low Voltage
V
OLJ
--
0.4
V
5, 7
Test Port Output CMOS High
V
OHJC
V
DDQ
100 mV
--
V
5, 8
Test Port Output CMOS Low
V
OLJC
--
100 mV
V
5, 9
Notes:
1. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. V
ILJ
V
IN
V
DDn
3. 0 V
V
IN
V
ILJn
4. Output Disable, V
OUT
= 0 to V
DDn
5. The TDO output driver is served by the V
DDQ
supply.
6. I
OHJ
= 4 mA
7. I
OLJ
= + 4 mA
8. I
OHJC
= 100 uA
9. I
OHJC
= +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
V
DD
0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DDQ
/2
Output reference level
V
DDQ
/2
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
32/37
2004, GSI Technology
JTAG Port Timing Diagram
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
JTAG Port AC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
50
--
ns
TCK Low to TDO Valid
tTKQ
--
20
ns
TCK High Pulse Width
tTKH
20
--
ns
TCK Low Pulse Width
tTKL
20
--
ns
TDI & TMS Set Up Time
tTS
10
--
ns
TDI & TMS Hold Time
tTH
10
--
ns
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKL
tTKL
tTKH
tTKH
tTKC
tTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
33/37
2004, GSI Technology
TQFP Package Drawing (Package T)
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol
Description
Min. Nom. Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
--
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
--
0.65
--
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
--
1.00
--
Y
Coplanarity
0.10
Lead Angle
0
--
7
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
34/37
2004, GSI Technology
Package Dimensions--165-Bump FPBGA (Package D; Variation 2)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11
11 10 9 8 7 6 5 4 3 2 1
A1 CORNER
TOP VIEW
A1 CORNER
BOTTOM VIEW
1.0
1.0
10.0
1.
0
1.
0
14.
0
130.07
150.
07
A
B
0.20(4x)
0.10
0.25
C
C A B
M
M
0.44~0.64 (165x)
C
SEATING PLANE
0.
20
C
0.
3
6
~
0
.4
6
1.
40 MAX.
0.6
5
R
E
F
0.
35
C
0.
26 REF
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
35/37
2004, GSI Technology

Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
Status
1M x 18
GS8161Z18BT-250
NBT Pipeline/Flow Through
TQFP
250/5.5
C
1M x 18
GS8161Z18BT-200
NBT Pipeline/Flow Through
TQFP
200/6.5
C
1M x 18
GS8161Z18BT-150
NBT Pipeline/Flow Through
TQFP
150/7.5
C
1M x 18
GS8161Z18BGT-250
NBT Pipeline/Flow Through
Pb-Free TQFP
250/5.5
C
1M x 18
GS8161Z18BGT-200
NBT Pipeline/Flow Through
Pb-Free TQFP
200/6.5
C
1M x 18
GS8161Z18BGT-150
NBT Pipeline/Flow Through
Pb-Free TQFP
150/7.5
C
1M x 18
GS8161Z18BD-250
NBT Pipeline/Flow Through
165 BGA (var.2)
250/5.5
C
1M x 18
GS8161Z18BD-200
NBT Pipeline/Flow Through
165 BGA (var.2)
200/6.5
C
1M x 18
GS8161Z18BD-150
NBT Pipeline/Flow Through
165 BGA (var.2)
150/7.5
C
512K x 32
GS8161Z32BD-250
NBT Pipeline/Flow Through
165 BGA (var.2)
250/5.5
C
512K x 32
GS8161Z32BD-200
NBT Pipeline/Flow Through
165 BGA (var.2)
200/6.5
C
512K x 32
GS8161Z32BD-150
NBT Pipeline/Flow Through
165 BGA (var.2)
150/7.5
C
512K x 36
GS8161Z36BT-250
NBT Pipeline/Flow Through
TQFP
250/5.5
C
512K x 36
GS8161Z36BT-200
NBT Pipeline/Flow Through
TQFP
200/6.5
C
512K x 36
GS8161Z36BT-150
NBT Pipeline/Flow Through
TQFP
150/7.5
C
512K x 36
GS8161Z36BGT-250
NBT Pipeline/Flow Through
Pb-Free TQFP
250/5.5
C
512K x 36
GS8161Z36BGT-200
NBT Pipeline/Flow Through
Pb-Free TQFP
200/6.5
C
512K x 36
GS8161Z36BGT-150
NBT Pipeline/Flow Through
Pb-Free TQFP
150/7.5
C
512K x 36
GS8161Z36BD-250
NBT Pipeline/Flow Through
165 BGA (var.2)
250/5.5
C
512K x 36
GS8161Z36BD-200
NBT Pipeline/Flow Through
165 BGA (var.2)
200/6.5
C
512K x 36
GS8161Z36BD-150
NBT Pipeline/Flow Through
165 BGA (var.2)
150/7.5
C
1M x 18
GS8161Z18BT-250I
NBT Pipeline/Flow Through
TQFP
250/5.5
I
1M x 18
GS8161Z18BT-200I
NBT Pipeline/Flow Through
TQFP
200/6.5
I
1M x 18
GS8161Z18BT-150I
NBT Pipeline/Flow Through
TQFP
150/7.5
I
1M x 18
GS8161Z18BGT-250I
NBT Pipeline/Flow Through
Pb-Free TQFP
250/5.5
I
1M x 18
GS8161Z18BGT-200I
NBT Pipeline/Flow Through
Pb-Free TQFP
200/6.5
I
1M x 18
GS8161Z18BGT-150I
NBT Pipeline/Flow Through
Pb-Free TQFP
150/7.5
I
1M x 18
GS8161Z18BD-250I
NBT Pipeline/Flow Through
165 BGA (var.2)
250/5.5
I
1M x 18
GS8161Z18BD-200I
NBT Pipeline/Flow Through
165 BGA (var.2)
200/6.5
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8161Z18B-.150T
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
36/37
2004, GSI Technology
1M x 18
GS8161Z18BD-150I
NBT Pipeline/Flow Through
165 BGA (var.2)
150/7.5
I
512K x 32
GS8161Z32BD-250I
NBT Pipeline/Flow Through
165 BGA (var.2)
250/5.5
I
512K x 32
GS8161Z32BD-200I
NBT Pipeline/Flow Through
165 BGA (var.2)
200/6.5
I
512K x 32
GS8161Z32BD-150I
NBT Pipeline/Flow Through
165 BGA (var.2)
150/7.5
I
512K x 36
GS8161Z36BT-250I
NBT Pipeline/Flow Through
TQFP
250/5.5
I
512K x 36
GS8161Z36BT-200I
NBT Pipeline/Flow Through
TQFP
200/6.5
I
512K x 36
GS8161Z36BT-150I
NBT Pipeline/Flow Through
TQFP
150/7.5
I
512K x 36
GS8161Z36BGT-250I
NBT Pipeline/Flow Through
Pb-Free TQFP
250/5.5
I
512K x 36
GS8161Z36BGT-200I
NBT Pipeline/Flow Through
Pb-Free TQFP
200/6.5
I
512K x 36
GS8161Z36BGT-150I
NBT Pipeline/Flow Through
Pb-Free TQFP
150/7.5
I
512K x 36
GS8161Z36BD-250I
NBT Pipeline/Flow Through
165 BGA (var.2)
250/5.5
I
512K x 36
GS8161Z36BD-200I
NBT Pipeline/Flow Through
165 BGA (var.2)
200/6.5
I
512K x 36
GS8161Z36BD-150I
NBT Pipeline/Flow Through
165 BGA (var.2)
150/7.5
I
Ordering Information for GSI Synchronous Burst RAMs (Continued)
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8161Z18B-.150T
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
37/37
2004, GSI Technology
18Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
8161ZxxB_r1
Creation of new datasheet