Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

300 MHz150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp

Preliminary

Features

· User-configurable Pipeline and Flow Through mode
· NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization

· Fully pin-compatible with both pipelined and flow through

NtRAMTM, NoBLTM and ZBTTM SRAMs

· IEEE 1149.1 JTAG-compatible Boundary Scan
· 2.5 V or 3.3 V +10%/10% core power supply
· LBO pin for Linear or Interleave Burst mode
· Pin-compatible with 2M, 4M, and 8M devices
· Byte write operation (9-bit Bytes)
· 3 chip enable signals for easy depth expansion
· ZZ pin for automatic power-down
· JEDEC-standard 100-lead TQFP and 165-bump FP-BGA

packages

Functional Description

The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.

Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.

The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
is implemented with GSI's high performance CMOS
technology and is available in JEDEC-standard 100-pin TQFP
and 165-bump FP-BGA packages.

Parameter Synopsis

-300

-250

-200

-150

Unit

Pipeline

3-1-1-1

(x18/x36)

tCycle

2.5
3.3

2.5
4.0

3.0
5.0

3.8
6.7

ns
ns

Curr

(x18)

Curr

(x32/x36)

335
390

280
330

230
270

185
210

mA
mA

Flow Through

2-1-1-1

tCycle

5.0
5.0

5.5
5.5

6.5
6.5

7.5
7.5

ns
ns

Curr

(x18)

Curr

(x32/x36)

230
270

210
240

185
205

170
190

mA
mA

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

GS8161Z18AT Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

DQP

DDQ

NC
V

ZZ
DQ

DDQ

TMS

TDO

TCK

CKE

ADV

1M x 18

Top View

DQP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

GS8161Z36AT Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

NC
V

ZZ
DQ

DDQ

TMS

TDI

TCK

CKE

ADV

512K x 36

Top View

DQP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

100-Pin TQFP Pin Descriptions

Symbol

Type

Description

, A

Burst Address Inputs; Preload the burst counter

Address Inputs

Clock Input Signal

Byte Write signal for data inputs DQ

; active low

Byte Write signal for data inputs DQ

; active low

Byte Write signal for data inputs DQ

; active low

Byte Write signal for data inputs DQ

; active low

Write Enable; active low

Chip Enable; active low

Chip Enable--Active High. For self decoded depth expansion

Chip Enable--Active Low. For self decoded depth expansion

Output Enable; active low

ADV

Advance/Load; Burst address counter control pin

CKE

Clock Input Buffer Enable; active low

No Connect

I/O

Byte A Data Input and Output pins

I/O

Byte B Data Input and Output pins

I/O

Byte C Data Input and Output pins

I/O

Byte D Data Input and Output pins

Power down control; active high

Pipeline/Flow Through Mode Control; active low

LBO

Linear Burst Order; active low.

Core power supply

Ground

DDQ

Output driver power supply

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

165 Bump BGA--x18 Commom I/O--Top View (Package D)

CKE

ADV

DDQ

DQPA

DQB

DDQ

DQA

DQB

DDQ

DQA

DQB

DDQ

DQA

DQB

DDQ

DQA

MCH

DQB

DDQ

DQA

DQB

DDQ

DQA

DQB

DDQ

DQA

DQB

DDQ

DQA

DQPB

DDQ

TDI

TDO

LBO

TMS

TCK

11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

165 Bump BGA--x32 Common I/O--Top View (Package D)

CKE

ADV

DDQ

DQC

DDQ

DQB

DQC

DDQ

DQB

DQC

DDQ

DQB

DQC

DDQ

DQB

MCH

DQD

DDQ

DQA

DQD

DDQ

DQA

DQD

DDQ

DQA

DQD

DDQ

DQA

DDQ

TDI

TDO

LBO

TMS

TCK

11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

165 Bump BGA--x36 Common I/O--Top View (Package D)

CKE

ADV

DQPC

DDQ

DQPB

DQC

DDQ

DQB

DQC

DDQ

DQB

DQC

DDQ

DQB

DQC

DDQ

DQB

MCH

DQD

DDQ

DQA

DQD

DDQ

DQA

DQD

DDQ

DQA

DQD

DDQ

DQA

DQPD

DDQ

DQPA

TDI

TDO

LBO

TMS

TCK

11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

GS8161Z18/32/36AD 165-Bump BGA Pin Description

Symbol

Type

Description

, A

Address field LSBs and Address Counter Preset Inputs

Address Inputs

I/O

Data Input and Output pins

, B

Byte Write Enable for DQ

, DQ

I/Os; active low

No Connect

Clock Input Signal; active high

CKE

Clock Input Buffer Enable; active low

Write Enable; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

ADV

Burst address counter advance enable; active high

Sleep mode control; active high

Flow Through or Pipeline mode; active low

LBO

Linear Burst Order mode; active low

TMS

Scan Test Mode Select

TDI

Scan Test Data In

TDO

Scan Test Data Out

TCK

Scan Test Clock

MCH

Must Connect High

Core power supply

I/O and Core Ground

DDQ

Output driver power supply

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

GS8161Z18/32/36A NBT SRAM Functional Block Diagram

SA1

SA0

Coun

ter

ADV

Memory

Array

CKE

DQaDQn

SA1'

SA0'

r
i
t
e Ad

r
es

Regi

er 2

r
it
e A

ddre

s
s

Regist

i
t
e

t
a

e
gist

er 2

r
ite Data

Regist

nse Amps

Write Driver

, W

r
ite an

Data Coherency

Control Logic

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E

, E

and E

). Deassertion of any one of the Enable

inputs will deactivate the device.

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E

, E

and E

) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (B

, B

& B

) determine which bytes will be written. All or none may be activated. A write cycle

with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.

Function

Read

Write Byte "a"

Write Byte "b"

Write Byte "c"

Write Byte "d"

Write all Bytes

Write Abort/NOP

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Synchronous Truth Table

Operation

Type Address E

ZZ ADV W Bx G CKE CK

Notes

Deselect Cycle, Power Down

None

L-H High-Z

Deselect Cycle, Power Down

None

L-H High-Z

Deselect Cycle, Power Down

None

L-H High-Z

Deselect Cycle, Continue

None

L-H High-Z

Read Cycle, Begin Burst

External

L-H

Read Cycle, Continue Burst

L-H

1,10

NOP/Read, Begin Burst

External

L-H High-Z

Dummy Read, Continue Burst

L-H High-Z

1,2,10

Write Cycle, Begin Burst

External

L-H

Write Cycle, Continue Burst

L-H

1,3,10

NOP/Write Abort, Begin Burst

None

L-H High-Z

2,3

Write Abort, Continue Burst

L-H High-Z 1,2,3,10

Clock Edge Ignore, Stall

Current

L-H

Sleep Mode

None

High-Z

Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect

cycle is executed first.

2. Dummy Read and Write abort can be considered NOP's because the SRAM performs no operation. A Write abort occurs when the W pin

is sampled low but no Byte Write pins are active so no Write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write

cycles.

4. If CKE High occurs during a pipelined Read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a Write cycle, the bus

will remain in High Z.

5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals

are low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Deselect

New Read

New Write

Burst Read

Burst Write

Pipelined and Flow Through Read Write Control State Diagram

Current State (n)

Next State (n+1)

Transition

Input Command Code

Key

Notes:

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

Clock (CK)

Command

Current State

Next State

n+1

n+2

n+3

Current State and Next State Definition for

Pipelined and Flow Through Read/Write Control State Diagram

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Intermediate

High Z

(Data In)

Data Out

(Q Valid)

High Z

B W

Pipeline Mode Data I/O State Diagram

Current State (n)

Next State (n+2)

Transition

Input Command Code

Key

Transition

Intermediate State (N+1)

Notes:

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Clock (CK)

Command

Current State

Intermediate

n+1

n+2

n+3

Current State and Next State Definition for

Pipeline Mode Data I/O State Diagram

Next State

State

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

High Z

(Data In)

Data Out

(Q Valid)

High Z

B W

Current State (n)

Next State (n+1)

Transition

Input Command Code

Key

Notes:

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Flow Through Mode Data I/O State Diagram

Clock (CK)

Command

Current State

Next State

n+1

n+2

n+3

Current State and Next State Definition for:

Pipeline and Flow through Read Write Control State Diagram

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.

Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name

Pin

Name

State

Function

Burst Order Control

LBO

Linear Burst

Interleaved Burst

Output Register Control

Flow Through

H or NC

Pipeline

Power Down Control

L or NC

Active

Standby, I

= I

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V

or V

DDQ

on pipelined parts and V

on flow

through parts. GSI NBT SRAMs are fully compatible with these sockets.

tZZR

tZZH

tZZS

~ ~

Sleep

~ ~

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to
Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of
time, may affect reliability of this component.

Absolute Maximum Ratings

(All voltages reference to V

)

Symbol

Description

Value

Unit

Voltage on V

Pins

0.5 to 4.6

DDQ

Voltage in V

DDQ

Pins

0.5 to 4.6

I/O

Voltage on I/O Pins

0.5 to V

DDQ

+0.5 (

4.6 V max.)

Voltage on Other Input Pins

0.5 to V

+0.5 (

4.6 V max.)

Input Current on Any Pin

+/20

OUT

Output Current on Any I/O Pin

+/20

Package Power Dissipation

1.5

STG

Storage Temperature

55 to 125

BIAS

Temperature Under Bias

55 to 125

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Power Supply Voltage Ranges

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

3.3 V Supply Voltage

DD3

3.0

3.3

3.6

2.5 V Supply Voltage

DD2

2.3

2.5

2.7

3.3 V V

DDQ

I/O Supply Voltage

DDQ3

3.0

3.3

3.6

2.5 V V

DDQ

I/O Supply Voltage

DDQ2

2.3

2.5

2.7

Notes:
1.

The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDQ3

Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Input High Voltage

2.0

+ 0.3

Input Low Voltage

0.3

0.8

DDQ

I/O Input High Voltage

IHQ

2.0

DDQ

+ 0.3

1,3

DDQ

I/O Input Low Voltage

ILQ

0.3

0.8

1,3

Notes:
1.

2. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

DDQ2

Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Input High Voltage

0.6*V

+ 0.3

Input Low Voltage

0.3

0.3*V

DDQ

I/O Input High Voltage

IHQ

0.6*V

DDQ

+ 0.3

1,3

DDQ

I/O Input Low Voltage

ILQ

0.3

0.3*V

1,3

Notes:
1.

2. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

Rev: 1.03a 5/2003

19/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Note: These parameters are sample tested.

Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-

ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Recommended Operating Temperatures

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:
1.

2. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Capacitance

= 25

C, f = 1 MH

, V

= 2.5 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Input Capacitance

= 0 V

Input/Output Capacitance

I/O

OUT

= 0 V

Package Thermal Characteristics

Rating

Layer Board

Symbol

Max

Unit

Notes

Junction to Ambient (at 200 lfm)

single

C/W

1,2

Junction to Ambient (at 200 lfm)

four

C/W

1,2

Junction to Case (TOP)

C/W

20% tKC

2.0 V

50%

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

+ 2.0 V

50%

Rev: 1.03a 5/2003

20/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

AC Test Conditions

Parameter

Conditions

Input high level

0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

Output reference level

DDQ

Output load

Fig. 1

Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

= 0 to V

1 uA

ZZ Input Current

IN1

0 V

1 uA
1 uA

1 uA

100 uA

FT Input Current

IN2

0 V

100 uA

1 uA

1 uA
1 uA

Output Leakage Current

Output Disable, V

OUT

= 0 to V

1 uA

Output High Voltage

OH2

= 8 mA, V

DDQ

= 2.375 V

1.7 V

Output High Voltage

OH3

= 8 mA, V

DDQ

= 3.135 V

2.4 V

Output Low Voltage

= 8 mA

0.4 V

DDQ/2

30pF

Output Load 1

* Distributed Test Jig Capacitance

Rev: 1.03a 5/2003

21/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

erating Currents

Notes:

d I

DDQ

apply to any combination of V

DD3

, V

DD2

, V

, and V

DDQ2

operation.

All p

a
rameters listed are worst case scenario.

Parameter

T
est Conditions

Mode

Symbol

-300

-25

-200

-15

Unit

to 70°C

to 85°C

to 70°

to 85°C

to 70°C

to 85°C

to 70°C

to 85°C

p
er

r
r
e
n
t

Devi

ed;

All other

input

o
r

Output

pen

(x32

P
i
pe

li
ne

DDQ

355

290

250

190

200

Flow

rou

g
h

DDQ

250

220

200

175

185

(x18

)

P
i
pe

li
ne

DDQ

320

260

225

170

180

Flow

rou

g
h

DDQ

225

200

185

160

170

andby

r
r
e
n
t

0.2 V

P
i
pe

li
ne

4
0

Flow

rou

g
h

4
0

Des

e
lect

r
r
e
n
t

ce Des

e
l
e
ct

ed;

All other

input

P
i
pe

li
ne

8
5

6
0

Flow

rou

g
h

6
0

5
0

Rev: 1.03a 5/2003

22/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

AC Electrical Characteristics

Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times

as specified above.

Parameter

Symbol

-300

-250

-200

-150

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Pipeline

Clock Cycle Time

tKC

3.3

4.0

5.0

6.7

Clock to Output Valid

tKQ

2.5

3.0

3.8

Clock to Output Invalid

tKQX

1.5

Clock to Output in Low-Z

tLZ

1.5

Setup time

1.0

1.2

1.4

1.5

Hold time

0.1

0.2

0.4

0.5

Flow Through

Clock Cycle Time

tKC

5.0

5.5

6.5

7.5

Clock to Output Valid

tKQ

5.0

5.5

6.5

7.5

Clock to Output Invalid

tKQX

3.0

Clock to Output in Low-Z

tLZ

3.0

Setup time

1.4

1.5

Hold time

0.4

0.5

Clock HIGH Time

tKH

1.3

1.5

Clock LOW Time

tKL

1.5

1.7

Clock to Output in

High-Z

tHZ

1.5 2.5

1.5 3.0

G to Output Valid

tOE

2.5

3.0

3.8

G to output in Low-Z

tOLZ

G to output in High-Z

tOHZ

2.5

3.0

3.8

ZZ setup time

tZZS

ZZ hold time

tZZH

ZZ recovery

tZZR

Rev: 1.03a 5/2003

25/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V

. The JTAG output

drivers are powered by V

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V

or V

. TDO should be left unconnected.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and
0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising
edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI
and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

JTAG Pin Descriptions

Pin

Pin Name

I/O

Description

TCK

Test Clock

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.

TMS

Test Mode Select

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.

TDI

Test Data In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.

TDO

Test Data Out

Out

Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.

Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Rev: 1.03a 5/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM's JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Code

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

P
r
esence Register

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

x36

X X X X

0 0 1 1 0 1 1 0 0 1

x18

X X X X

0 0 1 1 0 1 1 0 0 1

Instruction Register

ID Code Register

Boundary Scan Register

· · ·

31 30 29

· · ·

Bypass Register

TDI

TDO

TMS

TCK

Test Access Port (TAP) Controller

Rev: 1.03a 5/2003

27/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

Rev: 1.03a 5/2003

28/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when
the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the
sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in
parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the
Boundary Scan Register location with which each output pin is associated.
IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

Rev: 1.03a 5/2003

29/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

JTAG TAP Instruction Set Summary

Instruction

Code

Description

Notes

EXTEST

000

Places the Boundary Scan Register between TDI and TDO.

IDCODE

001

Preloads ID Register and places it between TDI and TDO.

1, 2

SAMPLE-Z

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.

RFU

011

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

SAMPLE/

PRELOAD

100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.

GSI

101

GSI private instruction.

RFU

110

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

BYPASS

111

Places Bypass Register between TDI and TDO.

Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Rev: 1.03a 5/2003

30/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

3.3 V Test Port Input High Voltage

IHJ3

2.0

DD3

+0.3

3.3 V Test Port Input Low Voltage

ILJ3

0.3

0.8

2.5 V Test Port Input High Voltage

IHJ2

0.6 * V

DD2

+0.3

2.5 V Test Port Input Low Voltage

ILJ2

0.3

0.3 * V

DD2

TMS, TCK and TDI Input Leakage Current

INHJ

300

TMS, TCK and TDI Input Leakage Current

INLJ

100

TDO Output Leakage Current

OLJ

Test Port Output High Voltage

OHJ

1.7

5, 6

Test Port Output Low Voltage

OLJ

0.4

5, 7

Test Port Output CMOS High

OHJC

DDQ

100 mV

5, 8

Test Port Output CMOS Low

OLJC

100 mV

5, 9

Notes:
1. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. V

ILJ

DDn

3. 0 V

ILJn

4. Output Disable, V

OUT

= 0 to V

DDn

5. The TDO output driver is served by the V

DDQ

supply.

6. I

OHJ

= 4 mA

7. I

OLJ

= + 4 mA

8. I

OHJC

= 100 uA

9. I

OHJC

= +100 uA

Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.

JTAG Port AC Test Conditions

Parameter

Conditions

Input high level

0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

DDQ

Output reference level

DDQ

30pF

JTAG Port AC Test Load

* Distributed Test Jig Capacitance

Rev: 1.03a 5/2003

31/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

JTAG Port Timing Diagram

JTAG Port AC Electrical Characteristics

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.

Parameter

Symbol

Min

Max

Unit

TCK Cycle Time

tTKC

TCK Low to TDO Valid

tTKQ

TCK High Pulse Width

tTKH

TCK Low Pulse Width

tTKL

TDI & TMS Set Up Time

tTS

TDI & TMS Hold Time

tTH

tTKQ

tTS

tTH

tTKH

tTKL

TCK

TMS

TDI

TDO

tTKC

Rev: 1.03a 5/2003

32/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

TQFP Package Drawing

BPR 1999.05.18

Pin 1

TQFP Package Drawing

Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.

Symbol

Description

Min.

Nom.

Max

Standoff

0.05

0.10

0.15

Body Thickness

1.35

1.40

1.45

Lead Width

0.20

0.30

0.40

Lead Thickness

0.09

0.20

Terminal Dimension

21.9

22.0

20.1

Package Body

19.9

20.0

20.1

Terminal Dimension

15.9

16.0

16.1

Package Body

13.9

14.0

14.1

Lead Pitch

0.65

Foot Length

0.45

0.60

0.75

Lead Length

1.00

Coplanarity

0.10

Lead Angle

Rev: 1.03a 5/2003

34/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

Ordering Information--GSI NBT Synchronous SRAM

Org

Part Number

Type

Package

Speed

(MHz/ns)

Status

1M x 18

GS8161Z18AT-300

Pipeline/Flow Through

TQFP

300/5

1M x 18

GS8161Z18AT-250

Pipeline/Flow Through

TQFP

250/5.5

1M x 18

GS8161Z18AT-200

Pipeline/Flow Through

TQFP

200/6.5

1M x 18

GS8161Z18AT-150

Pipeline/Flow Through

TQFP

150/7.5

1M x 18

GS8161Z18AD-300

Pipeline/Flow Through

165 BGA

300/5

1M x 18

GS8161Z18AD-250

Pipeline/Flow Through

165 BGA

250/5.5

1M x 18

GS8161Z18AD-200

Pipeline/Flow Through

165 BGA

200/6.5

1M x 18

GS8161Z18AD-150

Pipeline/Flow Through

165 BGA

150/7.5

512K x 32

GS8161Z32AD-300

Pipeline/Flow Through

165 BGA

300/5

512K x 32

GS8161Z32AD-250

Pipeline/Flow Through

165 BGA

250/5.5

512K x 32

GS8161Z32AD-200

Pipeline/Flow Through

165 BGA

200/6.5

512K x 32

GS8161Z32AD-150

Pipeline/Flow Through

165 BGA

150/7.5

512K x 36

GS8161Z36AT-300

Pipeline/Flow Through

TQFP

300/5

512K x 36

GS8161Z36AT-250

Pipeline/Flow Through

TQFP

250/5.5

512K x 36

GS8161Z36AT-200

Pipeline/Flow Through

TQFP

200/6.5

512K x 36

GS8161Z36AT-150

Pipeline/Flow Through

TQFP

150/7.5

512K x 36

GS8161Z36AD-300

Pipeline/Flow Through

165 BGA

300/5

512K x 36

GS8161Z36AD-250

Pipeline/Flow Through

165 BGA

250/5.5

512K x 36

GS8161Z36AD-200

Pipeline/Flow Through

165 BGA

200/6.5

512K x 36

GS8161Z36AD-150

Pipeline/Flow Through

165 BGA

150/7.5

1M x 18

GS8161Z18AT-300I

Pipeline/Flow Through

TQFP

300/5

1M x 18

GS8161Z18AT-250I

Pipeline/Flow Through

TQFP

250/5.5

1M x 18

GS8161Z18AT-200I

Pipeline/Flow Through

TQFP

200/6.5

1M x 18

GS8161Z18AT-150I

Pipeline/Flow Through

TQFP

150/7.5

1M x 18

GS8161Z18AD-300I

Pipeline/Flow Through

165 BGA

300/5

1M x 18

GS8161Z18AD-250I

Pipeline/Flow Through

165 BGA

250/5.5

1M x 18

GS8161Z18AD-200I

Pipeline/Flow Through

165 BGA

200/6.5

1M x 18

GS8161Z18AD-150I

Pipeline/Flow Through

165 BGA

150/7.5

512K x 32

GS8161Z32AD-300I

Pipeline/Flow Through

165 BGA

300/5

512K x 32

GS8161Z32AD-250I

Pipeline/Flow Through

165 BGA

250/5.5

Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8161Z18AT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. T

= I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.03a 5/2003

35/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

512K x 32

GS8161Z32AD-200I

Pipeline/Flow Through

165 BGA

200/6.5

512K x 32

GS8161Z32AD-150I

Pipeline/Flow Through

165 BGA

150/7.5

512K x 36

GS8161Z36AT-300I

Pipeline/Flow Through

TQFP

300/5

512K x 36

GS8161Z36AT-250I

Pipeline/Flow Through

TQFP

250/5.5

512K x 36

GS8161Z36AT-200I

Pipeline/Flow Through

TQFP

200/6.5

512K x 36

GS8161Z36AT-150I

Pipeline/Flow Through

TQFP

150/7.5

512K x 36

GS8161Z36AD-300I

Pipeline/Flow Through

165 BGA

300/5

512K x 36

GS8161Z36AD-250I

Pipeline/Flow Through

165 BGA

250/5.5

512K x 36

GS8161Z36AD-200I

Pipeline/Flow Through

165 BGA

200/6.5

512K x 36

GS8161Z36AD-150I

Pipeline/Flow Through

165 BGA

150/7.5

Org

Part Number

Type

Package

Speed

(MHz/ns)

Status

device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. T

= I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.03a 5/2003

36/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)

Preliminary

18Mb Sync SRAM Data Sheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Page;Revisions;Reason

8161Z18A_r1

· Creation of new datasheet

8161Z18A_r1;

8161Z18A_r1_01

Content

· Updated FT power numbers
· Updated AC Characteristics table
· Updated ZZ recovery time diagram
· Updated AC Test Conditions table and removed Output Load

2 diagram

8161Z18A_r1_01;

8161Z18A_r1_02

Content

· Removed extraneous V

DDQ1

table on page 12 and changed

DDQ2

table to V

DDQ

· Removed pin locations from pin description table
· Removed BSR table

GS8161ZxxA_r1_02;

GS8161ZxxA_r1_03

Content

· Entire datasheet rewritten due to design changes

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS8161Z32AD-250

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS8161Z32AD-250