GS8162V72CC-333/300/250/200/150

256K x 72

18Mb S/DCD Sync Burst SRAMs

333 MHz150 MHz

1.8 V V

1.8 V I/O

209-Bump BGA
Commercial Temp
Industrial Temp

Preliminary

Rev: 1.01 2/2005

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Features

· FT pin for user-configurable flow through or pipeline operation
· Single/Dual Cycle Deselect selectable
· IEEE 1149.1 JTAG-compatible Boundary Scan
· ZQ mode pin for user-selectable high/low output drive
· 1.8 V +10%/10% core power supply
· LBO pin for Linear or Interleaved Burst mode
· Internal input resistors on mode pins allow floating mode pins
· Default to SCD x18/x36 Interleaved Pipeline mode
· Byte Write (BW) and/or Global Write (GW) operation
· Internal self-timed write cycle
· Automatic power-down for portable applications
· JEDEC-standard 209-bump BGA package
· Pb-Free 209-bump BGA package available

Functional Description

Applications

The GS8162V72CC is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although of a
type originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main store to
networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the user
via the FT mode . Holding the FT mode pin low places the RAM in
Flow Through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.

SCD and DCD Pipelined Reads

The GS8162V72CC is an SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read commands.
SCD SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs immediately
after the deselect command has been captured in the input registers.
DCD RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.

FLXDriveTM

The ZQ pin allows selection between high drive strength (ZQ low) for
multi-drop bus applications and normal drive strength (ZQ floating or
high) point-to-point applications. See the Output Driver
Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.

Core and Interface Voltages

The GS8162V72CC operates on a 1.8 V power supply. All input are
1.8 V compatible. Separate output power (V

DDQ

) pins are used to

decouple output noise from the internal circuits and are 1.8 V
compatible.

Parameter Synopsis

-333

-300

-250

-200

-150

Unit

Pipeline

3-1-1-1

tCycle

2.8
3.0

2.8
3.3

3.0
4.0

3.0
5.0

3.8
6.7

ns
ns

Curr

545

495

425

345

270

Flow Through

2-1-1-1

tCycle

4.5
4.5

5.0
5.0

5.5
5.5

6.5
6.5

7.5
7.5

ns
ns

Curr 380

345

315

275

250

GS8162V72CC-333/300/250/200/150

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.01 2/2005

2/29

GS8162V72C Pad Out--209-Bump BGA--Top View (Package C)

A DQG

DQG

ADSP

ADSC

ADV

DQB

B DQG

DQG

DQB

C DQG

DQG

DQB

D DQG

DQG

DQB

E DQPG

DQPC

DDQ

DQPF

DQPB

DQC

DQF

G DQC

DQC

DDQ

MCH

DDQ

DQF

H DQC

DQC

MCL

DQF

J DQC

DQC

DDQ

MCL

DDQ

DQF

K NC

MCL

L DQH

DQH

DDQ

DQA

M DQH

DQH

MCL

DQA

N DQH

DQH

DDQ

SCD

DDQ

DQA

P DQH

DQH

DQA

R DQPD

DQPH

DDQ

DQPA

DQPE

T DQD

DQD

LBO

DQE

DQD

DQE

DQD

DQE

DQD

TMS

TDI

TDO

TCK

DQE

Rev 10

11 x 19 Bump BGA--14 x 22 mm

Body--1 mm Bump Pitch

GS8162V72CC-333/300/250/200/150

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.01 2/2005

3/29

BPR1999.05.18

GS8162V72C BGA Pin Description

Symbol

Type

Description

, A

Address field LSBs and Address Counter Preset Inputs.

Address Inputs

I/O

Data Input and Output pins

, B

Byte Write Enable for DQ

, DQ

I/Os; active low

No Connect

Clock Input Signal; active high

Global Write Enable--Writes all bytes; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

ADV

Burst address counter advance enable; active low

ADSP, ADSC

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

LBO

Linear Burst Order mode; active low

SCD

Single Cycle Deselect/Dual Cycle Deselect Mode Control

MCH

Must Connect High

MCL

Must Connect Low

Byte Enable; active low

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

TMS

Scan Test Mode Select

TDI

Scan Test Data In

TDO

Scan Test Data Out

TCK

Scan Test Clock

Core power supply

I/O and Core Ground

DDQ

Output driver power supply

GS8162V72CC-333/300/250/200/150

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.01 2/2005

5/29

Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name

Pin

Name

State

Function

Burst Order Control

LBO

Linear Burst

Interleaved Burst

Power Down Control

L or NC

Active

Standby, I

= I

Single/Dual Cycle Deselect Control

SCD

Dual Cycle Deselect

H or NC

Single Cycle Deselect

FLXDrive Output Impedance Control

High Drive (Low Impedance)

H or NC

Low Drive (High Impedance)

Note:
The burst counter wraps to initial state on the 5th clock.

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

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