8182Sxx_r1

Rev: 1.01 6/2003

1/30

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8182S18/36D-333/300/250/200/167

18Mb

2x1B2

DDR SigmaSIO-II SRAM

167 MHz333 MHz

1.8 V V

1.8 V and 1.5 V I/O

165-Bump BGA
Commercial Temp
Industrial Temp

Features

· Simultaneous Read and Write SigmaQuadTM Interface
· JEDEC-standard pinout and package
· Dual Double Data Rate interface
· Byte Write controls sampled at data-in time
· DLL circuitry for wide output data valid window and future frequency

scaling

· Burst of 2 Read and Write
· 1.8 V +150/100 mV core power supply
· 1.5 V or 1.8 V HSTL Interface
· Pipelined read operation
· Fully coherent read and write pipelines
· ZQ mode pin for programmable output drive strength
· IEEE 1149.1 JTAG-compliant Boundary Scan
· 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
· Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

SigmaRAMTM Family Overview

GS8182S18/36 are built in compliance with the SigmaSIO-II SRAM
pinout standard for Separate I/O synchronous SRAMs. They are
18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide,
very low voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance networking
systems.

Clocking and Addressing Schemes

2x1B2

SigmaSIO-II SRAM is a synchronous device. It employs a

single input register clock input, K. The device also allows the user to
manipulate the output register clock input quasi independently with
the C clock input. If the C clock is tied high, the K clock is routed
internally to fire the output registers instead. Each

2x1B2

SigmaSIO-II SRAM also supplies an Echo Clock output, CQ, which is
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock output can be used to
fire input registers at the data's destination.

Because Separate I/O

2x1B2

RAMs always transfer data in two

packets, A0 is internally set to 0 for the first read or write transfer, and
automatically incremented by 1 for the next transfer. Because the LSB
is tied off internally, the address field of a

2x1B2

RAM is always one

address pin less than the advertised index depth (e.g., the 1M x 18
has a 512K addressable index).

Alternating Read-Write Operations

SigmaSIO-II SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to
interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and
re-started.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state
information with command inputs. See the Truth Table for details.

- 333

-300

-250

-200

-167

tKHKH

3.0 ns

3.3 ns

4.0 ns

5.0 ns

6.0 ns

tKHQV

0.45 ns

.045 ns

0.45 ns

0.5 ns

165-Bump, 13 mm x 15 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

Bottom View

JEDEC Std. MO-216, Variation CAB-1

Rev: 1.01 6/2003

2/30

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8182S18/36D-333/300/250/200/167

1M x 18 SigmaQuad SRAM -- Top View

A CQ

/SA

(144Mb)

NC/SA

(36Mb)

R/W

BW1

/SA

(72Mb)

B NC

BW0

C NC

D10

D NC

D11

Q10

E NC

Q11

DDQ

Q12

D12

DDQ

G NC

D13

Q13

DDQ

H D

OFF

REF

DDQ

REF

J NC

D14

DDQ

K NC

Q14

DDQ

L NC

Q15

D15

DDQ

M NC

D16

N NC

D17

Q16

P NC

Q17

R TDO

TCK

TMS

TDI

11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch

Notes:
1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. It is recommended that H1 be tied low for compatibility with future devices.

Rev: 1.01 6/2003

3/30

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8182S18/36D-333/300/250/200/167

512K x 36 SigmaQuad SRAM -- Top View

A CQ

/SA

(288Mb)

NC/SA

(36Mb)

R/W

BW2

BW1

NC/SA

(36Mb)

/SA

(144Mb)

B Q27

Q18

D18

BW3

BW0

D17

Q17

C D27

Q28

D19

D16

D D28

D20

Q19

Q16

D15

E Q29

D29

Q20

DDQ

Q15

Q30

Q21

D21

DDQ

D14

Q14

G D30

D22

Q22

DDQ

Q13

D13

H D

OFF

REF

DDQ

REF

J D31

Q31

D23

DDQ

D12

K Q32

D32

Q23

DDQ

Q12

L Q33

Q24

D24

DDQ

D11

Q11

M D33

Q34

D25

D10

N D34

D26

Q25

Q10

P Q35

D35

Q26

R TDO

TCK

TMS

TDI

11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch

Notes:
1. Expansion addresses: A9 for 36Mb, A3 for 72Mb, A10 for 144Mb, A2 for 288Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35.
4. It is recommended that H1 be tied low for compatibility with future devices.

Rev: 1.01 6/2003

4/30

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8182S18/36D-333/300/250/200/167

Pin Description Table

Symbol

Description

Type

Comments

Synchronous Address Inputs

Input

No Connect

Synchronous Read

Input

Active Low

Synchronous Write

Input

Active Low

BW0BW1

Synchronous Byte Writes

Input

Active Low

x18 Version

BW0BW3

Synchronous Byte Writes

Input

Active Low

x36 Version

Input Clock

Input

Active High

MCH

Must Connect High

Input

DC mode pin

Output Clock

Input

Active High

MCH

Must Connect High

Input

DC mode pin

TMS

Test Mode Select

Input

TDI

Test Data Input

Input

TCK

Test Clock Input

Input

TDO

Test Data Output

Output

REF

HSTL Input Reference Voltage

Input

Output Impedance Matching Input

Input

Input Clock

Input

Active Low

Output Clock

Output

Active Low

OFF

DLL Disable

Active Low

Synchronous Load Pin

Active Low

Output Echo Clock

Output

Active Low

Output Echo Clock

Output

Active High

MCL

Must Connect Low

DNU

Do Not Use

D0D35

Synchronous Data Inputs

Input

x36 Version

Q0Q35

Synchronous Data Outputs

Output

x36 Version

D0D17

Synchronous Data Inputs

Input

x18 Version

Q0Q17

Synchronous Data Outputs

Output

x18 Version

Notes:
1. C, C, K, or K cannot be set to V

REF

voltage.

2. When ZQ pin is directly connected to V

, output impedance is set to minimum value and it cannot be connected to ground or left uncon-

nected.

3. NC = Not Connected to die or any other pin

Rev: 1.01 6/2003

5/30

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8182S18/36D-333/300/250/200/167

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed.
Therefore, the SigmaSIO-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in
applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the
RAM's bandwidth in half.

A SigmaSIO-II SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM
that shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer
protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which
a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs
support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the
same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from
differences in how the RAM's interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application
at hand.

Power Supply

Supply

1.8 V Nominal

DDQ

Isolated Output Buffer Supply

Supply

1.8 or 1.5 V Nominal

Power Supply: Ground

Supply

Pin Description Table

Symbol

Description

Type

Comments

Notes:
1. C, C, K, or K cannot be set to V

REF

voltage.

2. When ZQ pin is directly connected to V

, output impedance is set to minimum value and it cannot be connected to ground or left uncon-

nected.

3. NC = Not Connected to die or any other pin

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