Rev: 1.04 2/2001

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

Preliminary

GS82032T/Q-150/138/133/117/100/66

64K x 32

2M Synchronous Burst SRAM

150 MHz66 MHz

9 ns18 ns

3.3 V V

3.3 V and 2.5 V I/O

TQFP, QFP
Commercial Temp
Industrial Temp

Features

· FT pin for user-configurable flow through or pipeline

operation

· Single Cycle Deselect (SCD) operation
· 3.3 V +10%/5% core power supply
· 2.5 V or 3.3 V I/O supply
· LBO pin for Linear or Interleaved Burst mode
· Internal input resistors on mode pins allow floating mode pins
· Default to Interleaved Pipeline mode
· Byte Write (BW) and/or Global Write (GW) operation
· Common data inputs and data outputs
· Clock Control, registered, address, data, and control
· Internal self-timed write cycle
· Automatic power-down for portable applications
· JEDEC-standard 100-lead TQFP or QFP package

Functional Description

Applications

The GS82032 is a 2,097,152-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications
ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E

, E

), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (Pin 14 in the TQFP, Bump
1F in the FP-BGA). Holding the FT mode pin/bump low,
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered
Data Output Register.

SCD Pipelined Reads

The GS82032 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS82032 operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (V

DDQ

) pins are used to decouple output noise from the

internal circuit.

-150 -138 -133 -117 -100

-66

Unit

Pipeline

3-1-1-1

tCycle

6.6
3.8

270

7.25

245

7.5

240

8.5
4.5

210

180

12.5

150

ns
ns

Flow

Through

2-1-1-1

tCycle

10.5

170

9.7

120

15
10

120

15
11

120

15
12

120

20
18
95

ns
ns

Rev: 1.04 2/2001

2/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

GS82032 100-Pin TQFP and QFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

NC
V

ZZ
DQ

DDQ

1
0

1
1

1
2

1
3

1
4

1
5

64K x 32

Top View

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 1.04 2/2001

3/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

TQFP Pin Description

Pin Location

Symbol

Type

Description

37, 36

, A

Address field LSBs and Address Counter preset Inputs

35, 34, 33, 32, 100, 99, 82, 81, 44, 45,

46, 47, 48, 49

Address Inputs

52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79

2, 3, 6, 7, 8, 9, 12, 13

18, 19, 22, 23, 24, 25, 28, 29

I/O

Data Input and Output pins

16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30

No Connect

Byte Write--Writes all enabled bytes; active low

93, 94

, B

Byte Write Enable for DQ

, DQ

Data I/Os; active low

95, 96

, B

Byte Write Enable for DQ

, DQ

Data I/Os; active low

Clock Input Signal; active high

Global Write Enable--Writes all bytes; active low

98, 92

, E

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

ADV

Burst address counter advance enable; active low

84, 85

ADSP, ADSC

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

LBO

Linear Burst Order mode; active low

15, 41, 65, 91

Core power supply

5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90

I/O and Core Ground

4, 11, 20, 27, 54, 61, 70, 77

DDQ

Output driver power supply

Rev: 1.04 2/2001

5/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.

Burst Counter Sequences

Byte Write Truth Table

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B

, B

, and/or B

may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

Mode Pin Functions

Mode Name

Pin

Name

State

Function

Burst Order Control

LBO

Linear Burst

H or NC

Interleaved Burst

Output Register Control

Flow Through

H or NC

Pipeline

Power Down Control

L or NC

Active

Standby, I

= I

Function

Notes

Read

Write byte

2, 3

Write byte

2, 3

Write byte

2, 3, 4

Write byte

2, 3, 4

Write all bytes

2, 3, 4

Write all bytes

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

Rev: 1.04 2/2001

6/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

Synchronous Truth Table

Operation

Address

Used

State

Diagram

Key

ADSP ADSC

ADV

Deselect Cycle, Power Down

None

High-Z

Deselect Cycle, Power Down

None

High-Z

Deselect Cycle, Power Down

None

High-Z

Read Cycle, Begin Burst

External

Read Cycle, Begin Burst

External

Write Cycle, Begin Burst

External

Read Cycle, Continue Burst

Next

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Next

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Current

Read Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst

Current

Notes:

1. X = Don't Care, H = High, L = Low.
2. E = T (True) if E

= 1 and E

= 0; E = F (False) if E

= 0 or E

= 1.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as "Q" in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.04 2/2001

7/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

First Write

First Read

Burst Write

Burst Read

Deselect

S
i
m

p
l
e

S
y
n
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r
o
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s

O

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s

O

p
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a
t
i
o
n

Simplified State Diagram

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E

) and Write (B

, B

, BW, and GW) control

inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.04 2/2001

8/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

First Write

First Read

Burst Write

Burst Read

Deselect

Simplified State Diagram with G

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.04 2/2001

9/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be
restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings,
for an extended period of time, may affect reliability of this component.

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V

DDQ

2.375 V (i.e., 2.5 V I/O)

and 3.6 V

DDQ

3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of

Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be 2 V > Vi < V

+2 V with a pulse width not to exceed 20% tKC.

Absolute Maximum Ratings

(All voltages reference to V

)

Symbol

Description

Value

Unit

Voltage on V

Pins

0.5 to 4.6

DDQ

Voltage in V

DDQ

Pins

0.5 to V

Voltage on Clock Input Pin

0.5 to 6

I/O

Voltage on I/O Pins

0.5 to V

DDQ

+0.5 (

4.6 V max.)

Voltage on Other Input Pins

0.5 to V

+0.5 (

4.6 V max.)

Input Current on Any Pin

+/20

OUT

Output Current on Any I/O Pin

+/20

Package Power Dissipation

1.5

STG

Storage Temperature

55 to 125

BIAS

Temperature Under Bias

55 to 125

Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Supply Voltage

3.135

3.3

3.6

I/O Supply Voltage

DDQ

2.375

2.5

Input High Voltage

1.7

+0.3

Input Low Voltage

0.3

0.8

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Rev: 1.04 2/2001

10/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

Note: This parameter is sample tested.

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.

Temperature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
4. For x18 configuration, consult factory.

Capacitance

= 25

C, f = 1 MH

, V

= 3.3 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Control Input Capacitance

= 3.3 V

Input Capacitance

= 0 V

Output Capacitance

OUT

= 0 V

Package Thermal Characteristics

Rating

Layer Board

Symbol

TQFP Max

QFP Max

Unit

Notes

Junction to Ambient (at 200 lfm)

single

TBD

C/W

1,2,4

Junction to Ambient (at 200 lfm)

four

TBD

C/W

1,2,4

Junction to Case (TOP)

TBD

C/W

3,4

20% tKC

-2.0V

50%

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

+-2.0V

50%

Rev: 1.04 2/2001

11/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

Notes:

1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t

, t

OLZ

and t

OHZ

4. Device is deselected as defined by the Truth Table.

AC Test Conditions

Parameter

Conditions

Input high level

2. 3V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

1.25 V

Output reference level

1.25 V

Output load

Fig. 1& 2

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

= 0 to V

1 uA

ZZ Input Current

INZZ

0 V

1 uA

300 uA

Mode Pin Input Current

INM

0 V

300 uA

1 uA

Output Leakage Current

Output Disable,

OUT

= 0 to V

1 uA

Output High Voltage

= 4 mA, V

DDQ

= 2.375 V

1.7 V

Output High Voltage

= 4 mA, V

DDQ

= 3.135 V

2.4 V

Output Low Voltage

= 4 mA

0.4 V

VT = 1.25 V

30pF

2.5 V

Output Load 1

Output Load 2

225

5pF

* Distributed Test Jig Capacitance

Rev: 1.04 2/2001

12/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

p
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Rev: 1.04 2/2001

13/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

AC Electrical Characteristics

Notes:

1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Parameter

Symbol

-150

-138

-133

-117

-100

-66

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Pipeline

Clock Cycle Time

tKC

6.6

7.25

7.5

8.5

12.5

Clock to Output Valid

tKQ

3.8

4.5

Clock to Output Invalid

tKQX

1.5

Clock to Output in Low-Z

tLZ

1.5

Flow

Through

Clock Cycle Time

tKC

10.5

Clock to Output Valid

tKQ

9.0

9.7

Clock to Output Invalid

tKQX

Clock to Output in Low-Z

tLZ

Clock HIGH Time

tKH

1.8

1.9

Clock LOW Time

tKL

1.8

1.9

Clock to Output in High-Z

tHZ

1.5

3.8

1.5

G to Output Valid

tOE

3.8

G to output in Low-Z

tOLZ

G to output in High-Z

tOHZ

Setup time

1.7

Hold time

0.5

ZZ setup time

tZZS

ZZ hold time

tZZH

ZZ recovery

tZZR

Rev: 1.04 2/2001

14/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

ADSP

ADSC

ADV

WR2

WR3

WR1

WR2

WR3

tKC

Single Write

Burst Write

tS tH

Write specified byte for 2

and all bytes for 2

, 2

& 2

ADV must be inactive for ADSP Write

ADSC initiated write

ADSP is blocked by E

inactive

Write

Deselected

Hi-Z

WR1

WR2

WR3

Write Cycle Timing

tS tH

and E

only sampled with ADSP or ADSC

masks ADSP

Deselected with E

Rev: 1.04 2/2001

19/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of "dummy read cycles" (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles, and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.

ADSP

ADSC

tKH tKL

tKC

tZZR

tZZH

tZZS

~ ~

Snooze

Sleep Mode Timing Diagram

Rev: 1.04 2/2001

21/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

TQFP and QFP Package Drawing

i
n

Notes:

1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion

TQFP

QFP

Symbol

Description

Min.

Nom.

Max

Min.

Nom.

Max

Standoff

0.05

0.10

0.15

0.25

0.35

0.45

Body Thickness

1.35

1.40

1.45

2.55

2.72

2.90

Lead Width

0.20

0.30

0.40

0.20

0.30

0.40

Lead Thickness

0.09

0.20

0.10

0.15

0.20

Terminal Dimension

21.9

22.0

22.1

22.95

23.2

23.45

Package Body

19.9

20.0

20.1

19.9

20.0

20.1

Terminal Dimension

15.9

16.0

16.1

17.0

17.2

17.4

Package Body

13.9

14.0

14.1

13.9

14.0

14.1

Lead Pitch

0.65

Foot Length

0.45

0.60

0.75

.60

0.80

1.00

Lead Length

1.00

1.60

Coplanarity

0.10

Lead Angle

Rev: 1.04 2/2001

22/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

Ordering Information

Org

Part Number

Type

Package

Speed

(MHz/ns)

Status

64K x 32

GS82032T-150

Pipeline/Flow Through

TQFP

150/9

64K x 32

GS820322T-138

Pipeline/Flow Through

TQFP

138/9.7

64K x 32

GS82032T-133

Pipeline/Flow Through

TQFP

133/10

64K x 32

GS82032T-4

Pipeline/Flow Through

TQFP

133/10

64K x 32

GS82032T-5

Pipeline/Flow Through

TQFP

100/12

64K x 32

GS82032T-6

Pipeline/Flow Through

TQFP

66/18

64K x 32

GS82032T-150I

Pipeline/Flow Through

TQFP

150/9

Not Available

64K x 32

GS82032T-138I

Pipeline/Flow Through

TQFP

138/9.7

64K x 32

GS82032T-133I

Pipeline/Flow Through

TQFP

133/10

64K x 32

GS82032T-4I

Pipeline/Flow Through

TQFP

133/10

64K x 32

GS82032T-5I

Pipeline/Flow Through

TQFP

100/12

64K x 32

GS82032T-6I

Pipeline/Flow Through

TQFP

66/18

64K x 32

GS82032Q-150

Pipeline/Flow Through

QFP

150/9

64K x 32

GS82032Q-138

Pipeline/Flow Through

QFP

138/9.7

64K x 32

GS82032Q-133

Pipeline/Flow Through

QFP

133/10

64K x 32

GS82032Q-4

Pipeline/Flow Through

QFP

133/10

64K x 32

GS82032Q-5

Pipeline/Flow Through

QFP

100/12

64K x 32

GS82032Q-6

Pipeline/Flow Through

QFP

66/18

64K x 32

GS82032Q-150I

Pipeline/Flow Through

QFP

150/9

Not Available

64K x 32

GS82032Q-138I

Pipeline/Flow Through

QFP

138/9.7

64K x 32

GS82032Q-133I

Pipeline/Flow Through

QFP

133/10

64K x 32

GS82032Q-4I

Pipeline/Flow Through

QFP

133/10

64K x 32

GS82032Q-5I

Pipeline/Flow Through

QFP

100/12

64K x 32

GS82032Q-6I

Pipeline/Flow Through

QFP

66/18

Notes:

1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS82032T-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. T

= I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site(www.gsitechnology.com)for a complete listing of current offerings.

Rev: 1.04 2/2001

23/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Revisions

GS82032 Rev 1.00 9/

1999A

Format

· This was the first release of 2 Meg Burst Datasheets in the

new format. They included information for the Fine Pitch BGA
package.

GS82032 Rev 1.00 9/

1999A; 1.01 11/1999B

Content

· Took out the Fine Pitch BGA information.

GS82032 Rev 1.01 11/

1999B; 1.02 1/2000C

Content

· Ordering information. Changed 128K x 32 to 64K x 32; Typo
· Ordering information. Changed "0" to go before "H" or "E" in

part number.

· Ordering information. Changed - 117 to -4, -100 to -5. and -66

to -6.

GS820321.02 1/

2000C;820321.03 2/2000D

Format/Content

· New GSI Logo
· Switched TKQ with TCycle in Flow Through part of table on

page 1.

820321.03 2/2000D;

82032_r1_04

Format/Content

· Updated format to comply with Technical Publication

Standards

· Changed all -4 references in ordering information table on

page 22 from 117/11 to 133/10.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS82032Q-100