Preliminary
GS832018/32/36T-250/225/200/166/150/133
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
250 MHz133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.02 10/2004
1/25
2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
FT pin for user-configurable flow through or pipeline
operation
Single Cycle Deselect (SCD) operation
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS832018/32/36T is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832018/32/36T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.5
6.0
3.8
6.6
4.0
7.5
ns
ns
Curr
(x18)
Curr
(x32/x36)
285
350
265
320
245
295
220
260
210
240
185
215
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
6.5
6.5
7.0
7.0
7.5
7.5
8.0
8.0
8.5
8.5
8.5
8.5
ns
ns
Curr
(x18)
Curr
(x32/x36)
205
235
195
225
185
210
175
200
165
190
155
175
mA
mA
GS832018/32/36T-250/225/200/166/150/133
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 10/2004
2/25
2003, GSI Technology
GS832018 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
LBO
A
A
A
A
A
1
A
0
NC
A
V
SS
V
DD
A
A
A
A
A
A
A
A
A
A
E
1
E
2
NC
NC
B
B
B
A
E
3
CK
GW
BW
V
DD
V
SS
G
AD
SC
ADSP
ADV
A
A
A
2M x 18
Top View
DQP
A
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
GS832018/32/36T-250/225/200/166/150/133
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 10/2004
3/25
2003, GSI Technology
GS832032 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D3
DQ
D
DQ
D
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
LBO
A
A
A
A
A
1
A
0
NC
A
V
SS
V
DD
A
A
A
A
A
A
A
A
A
A
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
GW
BW
V
DD
V
SS
G
AD
SC
ADSP
ADV
A
A
A
1M x 32
Top View
DQ
B
NC
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
NC
DQ
C
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
NC
DQ
C
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
GS832018/32/36T-250/225/200/166/150/133
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 10/2004
4/25
2003, GSI Technology
GS832036 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D3
DQ
D
DQ
D
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
LBO
A
A
A
A
A
1
A
0
NC
A
V
SS
V
DD
A
A
A
A
A
A
A
A
A
A
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
GW
BW
V
DD
V
SS
G
AD
SC
ADSP
ADV
A
A
A
1M x 32
Top View
DQ
B
DQP
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
DQ
C
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
DQP
D
DQ
C
DQP
C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
GS832018/32/36T-250/225/200/166/150/133
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 10/2004
5/25
2003, GSI Technology
TQFP Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter preset Inputs
A
I
Address Inputs
DQ
A
DQ
B1
DQ
C
DQ
D
I/O
Data Input and Output pins
NC
No Connect
BW
I
Byte Write--Writes all enabled bytes; active low
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
B
C
, B
D
I
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
CK
I
Clock Input Signal; active high
GW
I
Global Write Enable--Writes all bytes; active low
E
1
, E
3
I
Chip Enable; active low
E
2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
V
DD
I
Core power supply
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
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