Rev: 1.10 5/2003
1/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
190 MHz100 MHz
3.3 V V
DD
3.3 V and 2.5 V I/O
TQFP, BGA
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipelined
operation
Dual Cycle Deselect (DCD) operation
3.3 V +10%/5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipelined mode
Byte Write (BW) and/or Global Write (GW) operation
Common data inputs and data outputs
Clock control, registered, address, data, and control
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC standard 100-lead TQFP or 119-Bump BGA package
Functional Description
Applications
The GS840E18/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36A is
available in a JEDEC standard 100-lead TQFP or 119-Bump
BGA package.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (pin 14 in the TQFP and
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
DCD Pipelined Reads
The GS840E18/32/36A is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS840E18/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to de-couple output noise
from the internal circuit.
190
180
166
150
100
Pipeline
3-1-1-1
tCycle
t
KQ
I
DD
5.3 ns
3.0 ns
200 mA
5.5 ns
3.0 ns
185 mA
6.0 ns
3.5 ns
170 mA
6.6 ns
3.8 ns
155 mA
10 ns
4.5 ns
105 mA
Flow
Through
2-1-1-1
t
KQ
tCycle
I
DD
7.5 ns
8.5 ns
125 mA
8 ns
9 ns
115 mA
8.5 ns
10 ns
105 mA
10 ns
12 ns
100 mA
12 ns
15 ns
80 mA
Rev: 1.10 5/2003
2/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
GS840E18A 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B
DQ
B2
V
SS
V
DDQ
DQ
B
DQ
B
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
VDDQ
DQ
A
DQ
A
V
SS
NC
VDD
ZZ
DQ
A
DQ
A
VDDQ
V
SS
DQ
A
DQ
A
V
SS
VDDQ
LBO
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
A
E
1
E
2
NC
NC
B
B
B
A
E
3
CK
GW
BW
V
DD
V
SS
G
ADSC
ADSP
ADV
A
A
A
256K x 18
Top View
DQP
A
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.10 5/2003
3/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
GS840E32A 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
LBO
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
A
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
GW
BW
V
DD
V
SS
G
ADSC
ADSP
ADV
A
A
A
128K x 32
Top View
DQ
B
NC
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
NC
DQ
C
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
NC
DQ
C
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.10 5/2003
4/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
GS840E36A 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
V
SS
V
DDQ
LBO
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
A
E
1
E
2
B
D
B
C
B
B
B
A
E
3
CK
GW
BW
V
DD
V
SS
G
ADSC
ADSP
ADV
A
A
A
128K x 36
Top View
DQ
B
DQP
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
DQ
C
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
DQP
D
DQ
C
DQP
C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.10 5/2003
5/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
TQFP Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter preset Inputs
A
I
Address Inputs
DQ
A
DQ
B
DQ
C
DQ
D
I/O
Data Input and Output pins
BW
I
Byte Write--Writes all enabled bytes; active low
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
Data I/'s; active low
B
C
, B
D
I
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
CK
I
Clock Input Signal; active high
GW
I
Global Write Enable--Writes all bytes; active low
E
1
, E
3
I
Chip Enable; active low
E
2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
V
DD
I
Core power supply
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
NC
-
No Connect
Rev: 1.10 5/2003
6/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
GS840E18A Pad Out
119-Bump BGA--Top View
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
B
NC
E
A
ADSC
A
E
3
NC
C
NC
A
A
V
DD
A
A
NC
D
DQ
B
NC
V
SS
NC
V
SS
DQP
A
NC
E
NC
DQ
B
V
SS
E
1
V
SS
NC
DQ
A
F
V
DDQ
NC
V
SS
G
V
SS
DQ
A
V
DDQ
G
NC
DQ
B
B
B
ADV
NC
NC
DQ
A
H
DQ
B
NC
V
SS
GW
V
SS
DQ
A
NC
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
NC
DQ
B
V
SS
CK
V
SS
NC
DQ
A
L
DQ
B
NC
NC
NC
B
A
DQ
A
NC
M
V
DDQ
DQ
B
V
SS
BW
V
SS
NC
V
DDQ
N
DQ
B
NC
V
SS
A
1
V
SS
DQ
A
NC
P
NC
DQP
B
V
SS
A
0
V
SS
NC
DQ
A
R
NC
A
LBO
V
DD
FT
A
NC
T
NC
A
A
NC
A
A
ZZ
U
V
DDQ
NC
NC
NC
NC
NC
V
DDQ
Rev: 1.10 5/2003
7/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
GS840E32A Pad Out
119-Bump BGA--Top View
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
B
NC
E
A
ADSC
A
E
3
NC
C
NC
A
A
V
DD
A
A
NC
D
DQ
C
NC
V
SS
NC
V
SS
NC
DQ
B
E
DQ
C
DQ
C
V
SS
E
1
V
SS
DQ
B
DQ
B
F
V
DDQ
DQ
C
V
SS
G
V
SS
DQ
B
V
DDQ
G
DQ
C
DQ
C
B
C
ADV
B
B
DQ
B
DQ
B
H
DQ
C
DQ
C
V
SS
GW
V
SS
DQ
B
DQ
B
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
DQ
D
DQ
D
V
SS
CK
V
SS
DQ
A
DQ
A
L
DQ
D
DQ
D
B
D
NC
B
A
DQ
A
DQ
A
M
V
DDQ
DQ
D
V
SS
BW
V
SS
DQ
A
V
DDQ
N
DQ
D
DQ
D
V
SS
A
1
V
SS
DQ
A
DQ
A
P
DQ
D
NC
V
SS
A
0
V
SS
NC
DQ
A
R
NC
A
LBO
V
DD
FT
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
V
DDQ
NC
NC
NC
NC
NC
V
DDQ
Rev: 1.10 5/2003
8/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
GS840E36APad Out
119-Bump BGA--Top View
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
B
NC
E
A
ADSC
A
E
3
NC
C
NC
A
A
V
DD
A
A
NC
D
DQ
C
DQP
C
V
SS
NC
V
SS
DQP
B
DQ
B
E
DQ
C
DQ
C
V
SS
E
1
V
SS
DQ
B
DQ
B
F
V
DDQ
DQ
C
V
SS
G
V
SS
DQ
B
V
DDQ
G
DQ
C
DQ
C
B
C
ADV
B
B
DQ
B
DQ
B
H
DQ
C
DQ
C
V
SS
GW
V
SS
DQ
B
DQ
B
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
DQ
D
DQ
D
V
SS
CK
V
SS
DQ
A
DQ
A
L
DQ
D
DQ
D
B
D
NC
B
A
DQ
A
DQ
A
M
V
DDQ
DQ
D
V
SS
BW
V
SS
DQ
A
V
DDQ
N
DQ
D
DQ
D
V
SS
A
1
V
SS
DQ
A
DQ
A
P
DQ
D
DQP
D
V
SS
A
0
V
SS
DQP
A
DQ
A
R
NC
A
LBO
V
DD
FT
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
V
DDQ
NC
NC
NC
NC
NC
V
DDQ
Rev: 1.10 5/2003
9/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
BGA Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
DQ
A
DQ
B
DQ
C
DQ
D
I/O
Data Input and Output pins
B
A
, B
B
, B
C
, B
D
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
CK
I
Clock Input Signal; active high
BW
I
Byte Write--Writes all enabled bytes; active low
GW
I
Global Write Enable--Writes all bytes; active low
E
1
, E
3
I
Chip Enable; active low
E
2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
V
DD
I
Core power supply
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
NC
--
No Connect
Rev: 1.10 5/2003
10/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
GS840E18/32/36A Block Diagram
A1
A0
A0
A1
D0
D1
Q1
Q0
Counter
Load
D
Q
D
Q
Register
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Regist
er
D
Q
Regist
er
A0An
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
B
B
B
C
B
D
E
1
G
ZZ
Power Down
Control
Memory
Array
36
36
4
A
Q
D
E
3
E
2
DQx0DQx9
Note: Only x36 version shown for simplicity.
1
FT
Rev: 1.10 5/2003
11/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Byte Write Truth Table
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes "
C
" and "
D
" are only available on the x32 and x36 versions.
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H or NC
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, I
DD
= I
SB
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte
A
H
L
L
H
H
H
2, 3
Write byte
B
H
L
H
L
H
H
2, 3
Write byte
C
H
L
H
H
L
H
2, 3, 4
Write byte
D
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Rev: 1.10 5/2003
12/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key
5
E
1
E
2
ADSP ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
None
X
H
X
X
L
X
X
High-Z
Deselect Cycle, Power Down
None
X
L
F
L
X
X
X
High-Z
Deselect Cycle, Power Down
None
X
L
F
H
L
X
X
High-Z
Read Cycle, Begin Burst
External
R
L
T
L
X
X
X
Q
Read Cycle, Begin Burst
External
R
L
T
H
L
X
F
Q
Write Cycle, Begin Burst
External
W
L
T
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
X
H
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
X
H
H
H
T
D
Write Cycle, Suspend Burst
Current
H
X
X
H
H
T
D
Notes:
1. X = Don't Care, H = High, L = Low.
2. E = T (True) if E
2
= 1 and E
3
= 0; E = F (False) if E
2
= 0 or E
3
= 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as "Q" in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.10 5/2003
13/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
Simple Synchronous Operation
Simple Burst Synchronou
s Operation
CR
R
CW
CR
CR
Simplified State Diagram
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E
1,
E
2,
E
3
) and Write (B
A
, B
B
, B
C
, B
D
, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 1.10 5/2003
14/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.10 5/2003
15/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be
restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings,
for an extended period of time, may affect reliability of this component.
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V
V
DDQ
2.375 V
(i.e., 2.5 V I/O) and 3.6 V
V
DDQ
3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be 2 V > Vi < V
DD
+2 V with a pulse width not to exceed 20% tKC.
Absolute Maximum Ratings
(All voltages reference to V
SS
)
Symbol
Description
Value
Unit
V
DD
Voltage on V
DD
Pins
0.5 to 4.6
V
V
DDQ
Voltage in V
DDQ
Pins
0.5 to V
DD
V
V
CK
Voltage on Clock Input Pin
0.5 to 6
V
V
I/O
Voltage on I/O Pins
0.5 to V
DDQ
+0.5 (
4.6 V max.)
V
V
IN
Voltage on Other Input Pins
0.5 to V
DD
+0.5 (
4.6 V max.)
V
I
IN
Input Current on Any Pin
+/20
mA
I
OUT
Output Current on Any I/O Pin
+/20
mA
P
D
Package Power Dissipation
1.5
W
T
STG
Storage Temperature
55 to 125
o
C
T
BIAS
Temperature Under Bias
55 to 125
o
C
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Supply Voltage
V
DD
3.135
3.3
3.6
V
I/O Supply Voltage
V
DDQ
2.375
2.5
V
DD
V
1
Input High Voltage
V
IH
1.7
--
V
DD
+0.3
V
2
Input Low Voltage
V
IL
0.3
--
0.8
V
2
Ambient Temperature (Commercial Range Versions)
T
A
0
25
70
C
3
Ambient Temperature (Industrial Range Versions)
T
A
40
25
85
C
3
Rev: 1.10 5/2003
16/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Note: This parameter is sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
Capacitance
(T
A
= 25
o
C, f = 1 MH
Z
, V
DD
= 3.3 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Control Input Capacitance
C
I
V
DD
= 3.3 V
3
4
pF
Input Capacitance
C
IN
V
IN
= 0 V
4
5
pF
Output Capacitance
C
OUT
V
OUT
= 0 V
6
7
pF
Package Thermal Characteristics
Rating
Layer Board
Symbol
TQFP Max
BGA Max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
R
JA
40
38
C/W
1,2,4
Junction to Ambient (at 200 lfm)
four
R
JA
24
21
C/W
1,2,4
Junction to Case (TOP)
R
JC
9
5
C/W
3,4
20% tKC
V
SS
-2.0V
50%
V
SS
V
IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
V
DD
+-2.0V
50%
V
DD
V
IL
Rev: 1.10 5/2003
17/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t
LZ
, t
HZ
, t
OLZ
and t
OHZ
.
4. Device is deselected as defined by the Truth Table.
AC Test Conditions
Parameter
Conditions
Input high level
2.3 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
1.25 V
Output reference level
1.25 V
Output load
Fig. 1& 2
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
1 uA
1uA
ZZ Input Current
I
INZZ
V
DD
V
IN
V
IH
0V
V
IN
V
IH
1 uA
1 uA
1 uA
300 uA
Mode Pin Input Current
I
INM
V
DD
V
IN
V
IL
0V
V
IN
V
IL
300 uA
1uA
1 uA
1 uA
Output Leakage Current
I
OL
Output Disable,
V
OUT
= 0 to V
DD
1 uA
1 uA
Output High Voltage
V
OH
I
OH
= 4 mA, V
DDQ
= 2.375 V
1.7 V
Output High Voltage
V
OH
I
OH
= 4 mA, V
DDQ
= 3.135 V
2.4 V
Output Low Voltage
V
OL
I
OL
= 4 mA
0.4 V
DQ
VT = 1.25 V
50
30pF
*
DQ
2.5 V
Output Load 1
Output Load 2
225
225
5pF
*
* Distributed Test Jig Capacitance
Rev: 1.10 5/2003
18/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Operating Currents
Parameter Test Conditions
Symbol
-190
-180
-166
-150
-100
Unit
0
to
70C
40
to
85C
0
to
70C
40
to
85C
0
to
70C
40
to
85C
0
to
70C
40
to
85C
0
to
70C
40
to
85C
Operating
Current
Device Selected;
All other
inputs
VIH or
VIL
Output open
IDD
Pipeline
200
210
185
195
170
180
155
165
105
115
mA
IDD
Flow
Through
125
135
115
125
105
115
100
110
80
90
mA
Standby
Current
ZZ
VDD
0.2 V
ISB
Pipeline
20
30
20
30
20
30
20
30
20
30
mA
ISB
Flow
Through
20
30
20
30
20
30
20
30
20
30
mA
Deselect
Current
Device
Deselected;
All other
inputs
VIH or
VIL
IDD
Pipeline
35
45
35
45
30
40
30
40
20
30
mA
IDD
Flow
Through
20
30
20
30
20
30
15
25
15
25
mA
Rev: 1.10 5/2003
19/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Parameter
Symbol
-190
-180
-166
-150
-100
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
5.3
--
5.5
--
6.0
--
6.7
--
10
--
ns
Clock to Output Valid
tKQ
--
3.0
--
3.0
--
3.5
--
3.8
--
4.5
ns
Clock to Output Invalid
tKQX
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Clock to Output in Low-Z
tLZ
1
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Flow
Through
Clock Cycle Time
tKC
8.5
--
9.0
--
10.0
--
12.0
--
15.0
--
ns
Clock to Output Valid
tKQ
--
7.5
--
8.0
--
8.5
--
10.0
--
12.0
ns
Clock to Output Invalid
tKQX
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
ns
Clock to Output in Low-Z
tLZ
1
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
ns
Clock HIGH Time
tKH
1.3
--
1.3
--
1.3
--
1.3
--
1.3
--
ns
Clock LOW Time
tKL
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Clock to Output in High-Z
tHZ
1
1.5 3.0
1.5 3.2
1.5
3.5
1.5 3.8
1.5
5
ns
G to Output Valid
tOE
--
3.0
--
3.2
--
3.5
--
3.8
--
5
ns
G to output in Low-Z
tOLZ
1
0
--
0
--
0
--
0
--
0
--
ns
G to output in High-Z
tOHZ
1
--
3.0
--
3.2
--
3.5
--
3.8
--
5
ns
Setup time
tS
1.5
--
1.5
--
1.5
--
1.5
--
2.0
--
ns
Hold time
tH
0.5
--
0.5
--
0.5
--
0.5
--
0.5
--
ns
ZZ setup time
tZZS
2
5
--
5
--
5
--
5
--
5
--
ns
ZZ hold time
tZZH
2
1
--
1
--
1
--
1
--
1
--
ns
ZZ recovery
tZZR
20
--
20
--
20
--
20
--
20
--
ns
Rev: 1.10 5/2003
20/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Pipeline Mode Timing
Begi
n
R
ea
d A
C
ont
Cont
D
e
s
e
lec
t
Writ
e B
R
e
a
d C
R
e
a
d C+1
R
e
a
d C+2
R
ea
d C+3
C
ont
Desele
ct
tH
Z
tK
QX
tK
Q
tL
Z
tH
tS
tO
HZ
tO
E
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tS
tH
tS
tH
tS
tH
tS
Burs
t
Rea
d
Burs
t
Rea
d
S
i
ngle W
r
it
e
tK
C
tK
C
tK
L
tK
L
tK
H
S
i
ngle W
r
it
e
Si
ngle Re
ad
tK
H
Si
ngle Re
ad
Q(A)
D(
B
)
Q(
C
)
Q(C+1
)
Q
(
C+
2)
Q(C+3)
AB
C
De
se
le
ct
ed
wit
h
E1
E1 m
a
sk
s A
D
S
P
E2
and
E
3
only
samp
l
e
d
wit
h
ADSP
and
AD
SC
ADSC i
n
i
tia
te
d
re
ad
CK
ADS
P
AD
SC
ADV
A0
A
n
GW
BW
Ba
Bd
E1
E2
E3
G
DQaDQ
d
Rev: 1.10 5/2003
21/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Flow Through Mode Timing
Begin
R
ead A
C
on
t
C
ont
1
W
rit
e
B
R
ead C
R
e
a
d C+1
R
ea
d C+
2
R
ead C+3
R
e
a
d C
C
ont2
D
e
s
e
l
ec
t
tH
Z
tK
QX
tK
Q
tL
Z
tH
tS
tO
HZ
tO
E
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tK
C
tK
C
tK
L
tK
L
tK
H
tK
H
AB
C
Q(A)
D(
B
)
Q(C)
Q(
C+
1)
Q(C+2
)
Q(C+3
)
Q(C)
E2 an
d E
3
o
n
l
y
sa
mple
d
with
ADSC
ADSC i
n
it
ia
te
d r
e
a
d
De
se
l
ect
ed
wit
h
E1
Fix
e
d H
i
gh
CK
AD
SP
AD
S
C
AD
V
A0An
GW
BW
Ba
Bd
E1
E2
E3
G
D
Q
aDQd
Rev: 1.10 5/2003
22/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of "dummy read cycles" (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
Snooze
Sleep Mode Timing Diagram
Rev: 1.10 5/2003
23/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
GS840E18/32/36A Output Driver Characteristics
-80
-60
-40
-20
0
20
40
60
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Dow n)
VDDQ - V Out (Pull Up)
I Out (mA)
3.6V PD LD
3.3V PD LD
3.1V PD LD
3.1V PU LD
3.3V PU LD
3.6V PU LD
Pull Up Drivers
Pull Down Drivers
V
DDQ
VOut
I Out
V
SS
Rev: 1.10 5/2003
24/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
TQFP Package Drawing
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol
Description
Min. Nom. Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
--
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
--
0.65
--
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
--
1.00
--
Y
Coplanarity
--
--
0.10
Lead Angle
0
--
7
Rev: 1.10 5/2003
25/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Package Dimensions--119-Pin BGA
N
P
A
B
Pin 1
Corner
K
E
F
CT
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
G
S
D
1
2
3
4
5
6
7
Package Dimensions--119-Pin BGA
Unit: mm
Symbol
Description
Min. Nom. Max
A
Width
13.8
14.0
14.2
B
Length
21.8
22.0
22.2
C
Package Height (including ball)
--
--
2.40
D
Ball Size
0.60
0.75
0.90
E
Ball Height
0.50
0.60
0.70
F
Package Height (excluding balls)
--
1.46
1.70
G
Width between Balls
--
1.27
--
K
Package Height above board
0.80
0.90
1.00
N
Cut-out Package Width
--
12.00
--
P
Foot Length
--
19.50
--
R
Width of package between balls
--
7.62
--
S
Length of package between balls
--
20.32
--
T
Variance of Ball Height
--
0.15
--
Bottom View
R
Top View
Side View
Rev: 1.10 5/2003
26/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Ordering Information for GSI Synchronous Burst RAMS
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
Status
256K x 18
GS840E18AT-190
DCD Pipeline/Flow Through
TQFP
190/7.5
C
256K x 18
GS840E18AT-180
DCD Pipeline/Flow Through
TQFP
180/8
C
256K x 18
GS840E18AT-166
DCD Pipeline/Flow Through
TQFP
166/8.5
C
256K x 18
GS840E18AT-150
DCD Pipeline/Flow Through
TQFP
150/10
C
256K x 18
GS840E18AT-100
DCD Pipeline/Flow Through
TQFP
100/12
C
128K x 32
GS840E32AT-190
DCD Pipeline/Flow Through
TQFP
190/7.5
C
128K x 32
GS840E32AT-180
DCD Pipeline/Flow Through
TQFP
180/8
C
128K x 32
GS840E32AT-166
DCD Pipeline/Flow Through
TQFP
166/8.5
C
128K x 32
GS840E32AT-150
DCD Pipeline/Flow Through
TQFP
150/10
C
128K x 32
GS840E32AT-100
DCD Pipeline/Flow Through
TQFP
100/12
C
128K x 36
GS840E36AT-190
DCD Pipeline/Flow Through
TQFP
190/7.5
C
128K x 36
GS840E36AT-180
DCD Pipeline/Flow Through
TQFP
180/8
C
128K x 36
GS840E36AT-166
DCD Pipeline/Flow Through
TQFP
166/8.5
C
128K x 36
GS840E36AT-150
DCD Pipeline/Flow Through
TQFP
150/10
C
128K x 36
GS840E36AT-100
DCD Pipeline/Flow Through
TQFP
100/12
C
256K x 18
GS840E18AT-190I
DCD Pipeline/Flow Through
TQFP
190/7.5
I
256K x 18
GS840E18AT-180I
DCD Pipeline/Flow Through
TQFP
180/8
I
256K x 18
GS840E18AT-166I
DCD Pipeline/Flow Through
TQFP
166/8.5
I
256K x 18
GS840E18AT-150I
DCD Pipeline/Flow Through
TQFP
150/10
C
256K x 18
GS840E18AT-100I
DCD Pipeline/Flow Through
TQFP
100/12
C
128K x 32
GS840E32AT-190I
DCD Pipeline/Flow Through
TQFP
190/7.5
I
128K x 32
GS840E32AT-180I
DCD Pipeline/Flow Through
TQFP
180/8
I
128K x 32
GS840E32AT-166I
DCD Pipeline/Flow Through
TQFP
166/8.5
I
128K x 32
GS840E32AT-150I
DCD Pipeline/Flow Through
TQFP
150/10
C
128K x 32
GS840E32AT-100I
DCD Pipeline/Flow Through
TQFP
100/12
C
128K x 36
GS840E36AT-190I
DCD Pipeline/Flow Through
TQFP
190/7.5
I
128K x 36
GS840E36AT-180I
DCD Pipeline/Flow Through
TQFP
180/8
I
128K x 36
GS840E36AT-166I
DCD Pipeline/Flow Through
TQFP
166/8.5
I
128K x 36
GS840E36AT-150I
DCD Pipeline/Flow Through
TQFP
150/10
C
128K x 36
GS840E36AT-100I
DCD Pipeline/Flow Through
TQFP
100/12
C
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS840E32AT-8T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode.
Each device is Pipeline/Flow through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.10 5/2003
27/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
256K x 18
GS840E18AB-190
DCD Pipeline/Flow Through
BGA
190/7.5
C
256K x 18
GS840E18AB-180
DCD Pipeline/Flow Through
BGA
180/8
C
256K x 18
GS840E18AB-166
DCD Pipeline/Flow Through
BGA
166/8.5
C
256K x 18
GS840E18AB-150
DCD Pipeline/Flow Through
BGA
150/10
C
256K x 18
GS840E18AB-100
DCD Pipeline/Flow Through
BGA
100/12
C
128K x 32
GS840E32AB-190
DCD Pipeline/Flow Through
BGA
190/7.5
C
128K x 32
GS840E32AB-180
DCD Pipeline/Flow Through
BGA
180/8
C
128K x 32
GS840E32AB-166
DCD Pipeline/Flow Through
BGA
166/8.5
C
128K x 32
GS840E32AB-150
DCD Pipeline/Flow Through
BGA
150/10
C
128K x 32
GS840E32AB-100
DCD Pipeline/Flow Through
BGA
100/12
C
128K x 36
GS840E36AB-190
DCD Pipeline/Flow Through
BGA
190/7.5
C
128K x 36
GS840E36AB-180
DCD Pipeline/Flow Through
BGA
180/8
C
128K x 36
GS840E36AB-166
DCD Pipeline/Flow Through
BGA
166/8.5
C
128K x 36
GS840E36AB-150
DCD Pipeline/Flow Through
BGA
150/10
C
128K x 36
GS840E36AB-100
DCD Pipeline/Flow Through
BGA
100/12
C
256K x 18
GS840E18AB-190I
DCD Pipeline/Flow Through
BGA
190/7.5
I
256K x 18
GS840E18AB-180I
DCD Pipeline/Flow Through
BGA
180/8
I
256K x 18
GS840E18AB-166I
DCD Pipeline/Flow Through
BGA
166/8.5
I
256K x 18
GS840E18AB-150I
DCD Pipeline/Flow Through
BGA
150/10
C
256K x 18
GS840E18AB-100I
DCD Pipeline/Flow Through
BGA
100/12
C
128K x 32
GS840E32AB-190I
DCD Pipeline/Flow Through
BGA
190/7.5
I
128K x 32
GS840E32AB-180I
DCD Pipeline/Flow Through
BGA
180/8
I
128K x 32
GS840E32AB-166I
DCD Pipeline/Flow Through
BGA
166/8.5
I
128K x 32
GS840E32AB-150I
DCD Pipeline/Flow Through
BGA
150/10
C
128K x 32
GS840E32AB-100I
DCD Pipeline/Flow Through
BGA
100/12
C
128K x 36
GS840E36AB-190I
DCD Pipeline/Flow Through
BGA
190/7.5
I
128K x 36
GS840E36AB-180I
DCD Pipeline/Flow Through
BGA
180/8
I
128K x 36
GS840E36AB-166I
DCD Pipeline/Flow Through
BGA
166/8.5
I
128K x 36
GS840E36AB-150I
DCD Pipeline/Flow Through
BGA
150/10
C
128K x 36
GS840E36AB-100I
DCD Pipeline/Flow Through
BGA
100/12
C
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS840E32AT-8T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode.
Each device is Pipeline/Flow through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.10 5/2003
28/28
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840E18/32/36AT/B-190/180/166/150/100
Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page /Revisions;Reason
GS840E18/32/36 Rev 1.02c 5/
1999;
GS840E18/32/36 2.00 8/1999D
Format/Typos
Document/Continued changing to new format.
Content
Added Fine Pitch BGA Package.
GS840E18/32/362.00 8/
1999;GS840E18/32/362.01 9/
1999E
Format/Typos
Took "E" out of 840HE...in Core and Interface Voltages.
Pin outs/New small caps format.
Timing Diagrams/New format.
Block Diagrams/New small caps format.
Content
Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to
DQB3.
Pin Description/Rearranged Address Inputs to match order on
TQFP Pinout.
TQFP Package Diagram/Corrected Dimension D Max from
20.1 to 22.1.
GS840E18/32/362.01 9/
1999E;GS840E18/32/362.02
Took out Fine Pitch BGA Package. Package change in
progress.
GS840E18/32/362.0210-11/
1999;GS840E18/32/362.032/
2000G
Format
New GSI Logo
Took "Pin" out of heading for consistency.
GS840E18/32/362.032/2000G;
840E18_r1_04
Content
Updated pin description table
840E18_r1_04; 840E18_r1_05
Content
Updated BGA pin description table to meet JEDEC standard
840E18A_r1_05; 840E18A_r1_06
Content/Format
Added "non-A" speed bins to Operating Currents table, AC
Electrical Characteristics table, and Ordering Information
table
Updated format to fit Technical Documentation standards
840E18A_r1_06; 840E18A_r1_07
Content/Format
Updated table on page 1
Updated Operating Currents table on page 18
Updated Electrical Characteristics table on page 19
Updated format to comply with present Technical
Documentation standards
Corrected typos in revision history table on page 31
840E18A_r1_07, 840E18A_r1_08
Content
Reduced I
DD
by 20 mA in table on page 1 and Operating
Currents table
840E18A_r1_08, 840E18A_r1_09
Content
Removed 200 MHz references from entire datasheet
840E18A_r1_09, 840E18A_r1_10
Content
Updated format
Added 190 MHz speed bin
PDF 
ZIP