Rev: 1.05 7/2002

1/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

256K x 18, 128K x 32, 128K x 36

4Mb Sync Burst SRAMs

8 ns12 ns

3.3 V V

3.3 V and 2.5 V I/O

TQFP
Commercial Temp
Industrial Temp

Features

· Flow Through mode operation
· 3.3 V +10%/5% core power supply
· 2.5 V or 3.3 V I/O supply
· LBO pin for Linear or Interleaved Burst mode
· Internal input resistors on mode pins allow floating mode pins
· Default to Interleaved Pipeline mode
· Byte Write (BW) and/or Global Write (GW) operation
· Common data inputs and data outputs
· Clock Control, registered, address, data, and control
· Internal self-timed write cycle
· Automatic power-down for portable applications
· JEDEC-standard 100-lead TQFP

Functional Description

Applications

The GS840FH18/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS840FH18/32/36A is
available in a JEDEC-standard 100-lead TQFP package.

Controls

Addresses, data I/Os, chip enables (E

, E

), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.

Designing For Compatibility

The JEDEC standard for Burst RAMs calls for a FT mode pin
option (Pin 14 on TQFP). Board sites for flow through Burst
RAMs should be designed with V

connected to the FT pin

location to ensure the broadest access to multiple vendor
sources. Boards designed with FT pin pads tied low may be
stuffed with GSI's pipeline/flow through-configurable Burst
RAMs or any vendor's flow through or configurable Burst
SRAM. Bumps designed with the FT pin location tied high or
floating must employ a non-configurable flow through Burst
RAM, (e.g., GS840FH18/32/36A), to achieve flow through
functionality.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS840FH18/32/36A operates on a 3.3 V power supply
and all inputs/outputs are 3.3 V- and 2.5 V-compatible.
Separate output power (V

DDQ

) pins are used to decouple

output noise from the internal circuit.

-8

-8.5

-10

-12

Unit

Flow

Through

2-1-1-1

tCycle

9.1

115

8.5

105

10
10

105

12
15
80

ns
ns

Rev: 1.05 7/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

GS840FH18A 100-Pin TQFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

NC
V

ZZ
DQ

DDQ

LBO

ADSC

ADSP

ADV

256K x 18

Top View

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

GS840FH32A 100-Pin TQFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

NC
V

ZZ
DQ

DDQ

LBO

ADSC

ADSP

ADV

128K x 32

Top View

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

GS840FH36A 100-Pin TQFP Pinout

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DDQ

NC
V

ZZ
DQ

DDQ

LBO

ADSC

ADSP

ADV

128K x 36

Top View

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

TQFP Pin Description

Pin Location

Symbol

Type

Description

37, 36

, A

Address field LSBs and Address Counter preset Inputs

35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,

47, 48, 49, 50

Address Inputs

Address Inputs (x18 versions)

52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79

2, 3, 6, 7, 8, 9, 12, 13

18, 19, 22, 23, 24, 25, 28, 29

I/O

Data Input and Output pins. (x32, x36 Version)

51, 80, 1, 30

, DQ

I/O

Data Input and Output pins. (x36 Version)

51, 80, 1, 30

No Connect (x32 Version)

58, 59, 62, 63, 68, 69, 72, 73, 74

8, 9, 12, 13, 18, 19, 22, 23, 24

-DQ

B98

I/O

Data Input and Output pins. (x18 Version)

51, 52, 53, 56, 57

75, 78, 79

1, 2, 3, 6, 7

25, 28, 29, 30

No Connect (x18 Version)

Byte Write--Writes all enabled bytes; active low

93, 94

, B

Byte Write Enable for DQ

, DQ

Data I/O's; active low

95, 96

, B

Byte Write Enable for DQ

, DQ

Data I/O's; active low

(x32, x36 Version)

95, 96

No Connect (x18 Version)

Clock Input Signal; active high

Global Write Enable--Writes all bytes; active low

98, 92

, E

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

ADV

Burst address counter advance enable; active low

84, 85

ADSP, ADSC

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

LBO

Linear Burst Order mode; active low

15, 41, 65, 91

Core power supply

5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90

I/O and Core Ground

4, 11, 20, 27, 54, 61, 70, 77

DDQ

Output driver power supply

14, 16, 38, 39, 42, 43, 66

No Connect

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Note:
There is a are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.

Burst Counter Sequences

Byte Write Truth Table

Notes:
1. All byte outputs are active in read cycles regardle

of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs B

, B

and/or B

may be used in any combination with BW to write single or multiple bytes.

3. All byte I/O's remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes "

" and "

" are only available on the x32 and x36 versions.

Mode Pin Functions

Mode Name

Pin

Name

State

Function

Burst Order Control

LBO

Linear Burst

H or NC

Interleaved Burst

Output Register Control

Flow Through

H or NC

Pipeline

Power Down Control

L or NC

Active

Standby, I

= I

Function

Notes

Read

Write byte

2, 3

Write byte

2, 3

Write byte

2, 3, 4

Write byte

2, 3, 4

Write all bytes

2, 3, 4

Write all bytes

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Synchronous Truth Table

Operation

Address

Used

State

Diagram

Key

ADSP ADSC

ADV

Deselect Cycle, Power Down

None

High-Z

Deselect Cycle, Power Down

None

High-Z

Deselect Cycle, Power Down

None

High-Z

Read Cycle, Begin Burst

External

Read Cycle, Begin Burst

External

Write Cycle, Begin Burst

External

Read Cycle, Continue Burst

Next

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Next

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Current

Read Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst

Current

Notes:
1. X = Don't Care, H = High, L = Low.
2. E = T (True) if E

= 1 and E

= 0; E = F (False) if E

= 0 or E

= 1.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as "Q" in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.05 7/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

First Write

First Read

Burst Write

Burst Read

Deselect

Simple Synchronous Operation

Simple Burst Synchronou

s Operation

Simplified State Diagram

Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E

) and Write (B

, B

, BW, and GW) control

inputs and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.05 7/2002

10/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

First Write

First Read

Burst Write

Burst Read

Deselect

Simplified State Diagram with G

Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.05 7/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.

Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V

VDDQ

2.375V (i.e. 2.5V I/O)

and 3.6V

VDDQ

3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.

2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of

Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be -2V > Vi < V

+2V with a pulse width not to exceed 20% tKC.

Absolute Maximum Ratings

(All voltages reference to V

)

Symbol

Description

Value

Unit

Voltage on V

Pins

0.5 to 4.6

DDQ

Voltage in V

DDQ

Pins

0.5 to V

Voltage on Clock Input Pin

0.5 to 6

I/O

Voltage on I/O Pins

0.5 to V

DDQ

+0.5 (

4.6 V max.)

Voltage on Other Input Pins

0.5 to V

+0.5 (

4.6 V max.)

Input Current on Any Pin

+/20

OUT

Output Current on Any I/O Pin

+/20

Package Power Dissipation

1.5

STG

Storage Temperature

55 to 125

BIAS

Temperature Under Bias

55 to 125

Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Supply Voltage

3.135

3.3

3.6

I/O Supply Voltage

DDQ

2.375

2.5

Input High Voltage

1.7

+0.3

Input Low Voltage

0.3

0.8

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Rev: 1.05 7/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Note: This parameter is sample tested.

Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.

Temperature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
4. For x18 configuration, consult factory.

Capacitance

= 25

C, f = 1 MH

, V

= 3.3 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Control Input Capacitance

= 3.3 V

Input Capacitance

= 0 V

Output Capacitance

OUT

= 0 V

Package Thermal Characteristics

Rating

Layer Board

Symbol

TQFP Max

Unit

Notes

Junction to Ambient (at 200 lfm)

single

C/W

1,2,4

Junction to Ambient (at 200 lfm)

four

C/W

1,2,4

Junction to Case (TOP)

C/W

3,4

20% tKC

-2.0V

50%

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

+-2.0V

50%

Rev: 1.05 7/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t

, t

OLZ

and t

OHZ

4. Device is deselected as defined by the Truth Table.

AC Test Conditions

Parameter

Conditions

Input high level

2.3 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

1.25 V

Output reference level

1.25 V

Output load

Fig. 1& 2

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

= 0 to V

1 uA

ZZ Input Current

INZZ

0 V

1 uA

300 uA

Mode Pin Input Current

INM

0 V

300 uA

1 uA

Output Leakage Current

Output Disable,

OUT

= 0 to V

1 uA

Output High Voltage

= 8 mA, V

DDQ

=2.375 V

1.7 V

Output High Voltage

= 8 mA, V

DDQ

=3.135 V

2.4 V

Output Low Voltage

= 8 mA

0.4 V

VT=1.25V

30pF

2.5 V

Output Load 1

Output Load 2

225

5pF

* Distributed Test Jig Capacitance

Rev: 1.05 7/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Operating Currents

AC Electrical Characteristics

Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Parameter

Test Conditions

Symbol

-8

-8.5

-10

-12

Unit

70°C

-40

85°C

70°C

-40

85°C

70°C

-40

85°C

70°C

-40

85°C

Operating

Current

Device Selected;

All other inputs

Output open

Flow Through

115

125

105

115

105

115

Standby

Current

0.2 V

Flow Through

Deselect

Current

Device Deselected;

All other inputs

Flow Through

Parameter

Symbol

-8

-8.5

-10

-12

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Flow

Through

Clock Cycle Time

tKC

9.1

10.0

15.0

Clock to Output Valid

tKQ

8.0

8.5

Clock to Output Invalid

tKQX

3.0

Clock to Output in Low-Z

tLZ

3.0

Clock HIGH Time

tKH

1.3

Clock LOW Time

tKL

1.5

Clock to Output in High-Z

tHZ

1.5 3.2

1.5

3.5

1.5

3.8

1.5

G to Output Valid

tOE

3.2

3.5

3.8

G to output in Low-Z

tOLZ

G to output in High-Z

tOHZ

3.2

3.5

3.8

Setup time

1.5

Hold time

0.5

ZZ setup time

tZZS

ZZ hold time

tZZH

ZZ recovery

tZZR

Rev: 1.05 7/2002

15/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

ADSP

ADSC

ADV

WR2

WR3

WR1

WR2

WR3

tKC

Single Write

Burst Write

D2a

D2b

D2c

D2d

D3a

D1a

tS tH

Write specified byte for 2a and all bytes for 2b, 2c& 2d

ADV must be inactive for ADSP Write

ADSC initiated write

ADSP is blocked by E

inactive

Write

Deselected

Hi-Z

WR1

WR2

WR3

Write Cycle Timing

tS tH

and E

only sampled with ADSP or ADSC

masks ADSP

Deselected with E

Rev: 1.05 7/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Q1a

Q3a

Q2d

Q2c

Q2b

Q2a

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

ADSP

ADSC

ADV

Burst Read

RD2

RD3

tKL

tS tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E

inactive

tKH

tKC

tS tH

RD1

Hi-Z

Suspend Burst

Flow Through Read Cycle Timing

masks ADSP

and E

only sampled with ADSP or ADSC

Deselected with E

Rev: 1.05 7/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Flow Through Read-Write Cycle Timing

ADSP

ADSC

ADV

RD1

WR1

RD2

Q1a

D1a

Q2a

Q2b

Q2c

Q2d

Single Read

Burst Read

tOE

tOHZ

tS tH

tKH

ADSC initiated read

A0An

tKL

tKC

Single Write

ADSP is blocked by E inactive

tKQ

Hi-Z

Q2a

Burst wrap around to it's initial state

WR1

tS tH

masks ADSP

and E

only sampled with ADSP and ADSC

Deselected with E

Rev: 1.05 7/2002

20/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

TQFP Package Drawing

Pin 1

Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion

Symbol

Description

Min.

Nom.

Max.

Standoff

0.05

0.10

0.15

Body Thickness

1.35

1.40

1.45

Lead Width

0.20

0.30

0.40

Lead Thickness

0.09

0.20

Terminal Dimension

21.9

22.0

22.1

Package Body

19.9

20.0

20.1

Terminal Dimension

15.9

16.0

16.1

Package Body

13.9

14.0

14.1

Lead Pitch

0.65

Foot Length

0.45

0.60

0.75

Lead Length

1.00

Coplanarity

0.10

Lead Angle

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Ordering Information for GSI Synchronous Burst RAMS

Org

Part Number

Type

Package

Speed

(MHz/ns)

Status

256K x 18

GS840FH18AT-8

Flow Through

TQFP

256K x 18

GS840FH18AT-8.5

Flow Through

TQFP

8.5

256K x 18

GS840FH18AT-10

Flow Through

TQFP

256K x 18

GS840FH18AT-12

Flow Through

TQFP

128K x 32

GS840FH32AT-8

Flow Through

TQFP

128K x 32

GS840FH32AT-8.5

Flow Through

TQFP

8.5

128K x 32

GS840FH32AT-10

Flow Through

TQFP

128K x 32

GS840FH32AT-12

Flow Through

TQFP

128K x 36

GS840FH36AT-8

Flow Through

TQFP

128K x 36

GS840FH36AT-8.5

Flow Through

TQFP

8.5

128K x 36

GS840FH36AT-10

Flow Through

TQFP

128K x 36

GS840FH36AT-12

Flow Through

TQFP

256K x 18

GS840FH18AT-8I

Flow Through

TQFP

256K x 18

GS840FH18AT-8.5I

Flow Through

TQFP

8.5

256K x 18

GS840FH18AT-10I

Flow Through

TQFP

256K x 18

GS840FH18AT-12I

Flow Through

TQFP

128K x 32

GS840FH32AT-8I

Flow Through

TQFP

128K x 32

GS840FH32AT-8.5I

Flow Through

TQFP

8.5

128K x 32

GS840FH32AT-10I

Flow Through

TQFP

128K x 32

GS840FH32AT-12I

Flow Through

TQFP

128K x 36

GS840FH36AT-8I

Flow Through

TQFP

128K x 36

GS840FH36AT-8.5I

Flow Through

TQFP

8.5

128K x 36

GS840FH36AT-10I

Flow Through

TQFP

128K x 36

GS840FH36AT-12I

Flow Through

TQFP

Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS840FH32AT-7.5T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. T

= I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.05 7/2002

22/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS840FH18/32/36AT-8/8.5/10/12

Revision History

Rev. Code: Old;

New

Types of Changes

Format or Content

Page /Revisions;Reason

840FH18A_r1_02

Content

· Updated pin description table

840FH18A_r1_02;

840FH18A_r1_03

Content/Format

· Updated table on page 1
· Updated Operating Currents table on page 14
· Updated AC Electrical Characteristics table on page 14
· Updated Ordering Information table on page 21
· Updated entire document to comply with Technical

Publications standards

840FH18A_r1_03;

840FH18A_r1_04

Content

· Reduced I

by 20 mA in table on page 1 and Operating

Currents table

840FH18A_r1_04;

840FH18A_r1_05

Content

· Removed 7.5 ns references from entire datasheet

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS840FH18

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS840FH18