Rev: 1.00 9/2002
1/27
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Trademark Notice (if any) Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS84118AT/B-166/150/133/100
256K x 18 Sync
Cache Tag
166 MHz100 MHz
8.5 ns12 ns
3.3 V V
DD
3.3 V and 2.5 V I/O
TQFP, BGA
Commercial Temp
Industrial Temp
Features
3.3 V +10%/5% core power supply, 2.5 V or 3.3 V I/O
supply
Intergrated data comparator for Tag RAM application
FT mode pin for flow through or pipeline operation
LBO pin for Linear or Interleave (Pentium
TM
and X86) Burst
mode
Synchronous address, data I/O, and control inputs
Synchronous Data Enable (DE)
Asynchronous Output Enable (OE)
Asynchronous Match Output Enable (MOE)
Byte Write (BWE) and Global Write (GW) operation
Three chip enable signals for easy depth expansion
Internal self-timed write cycle
JTAG Test mode conforms to IEEE standard 1149.1
JEDEC-standard 100-lead TQFP package and 119-BGA:
T:TQFP or B: BGA
Functional Description
The GS84118A is a 256K x 18 high performance synchronous
SRAM with integrated Tag RAM comparator. A 2-bit burst
counter is included to provide burst interface with Pentium
TM
and other high performance CPUs. It is designed to be used as
a Cache Tag SRAM, as well as data SRAM. Addresses, data
IOs, match output, chip enables (CE1, CE2, CE3), address
control inputs (ADSP, ADSC, ADV), and write control inputs
(BW1, BW2, BWE, GW, DE) are synchronous and are
controlled by a positive-edge-triggered clock (CLK).
Output Enable (OE), Match Output Enable, and power down
control (ZZ) are asynchronous. Burst can be initiated with
either ADSP or ADSC inputs. Subsequent burst addresses are
generated internally and are controlled by ADV. The burst
sequence is either interleave order (Pentium
TM
or x86) or
linear order, and is controlled by LBO.
Output registers and the Match output register are provided and
controlled by the FT mode pin (Pin 14). Through use of the FT
mode pin, I/O registers can be programmed to perform pipeline
or flow through operation. Flow Through mode reduces
latency.
Byte write operation is performed by using Byte Write Enable
(BWE) input combined with two individual byte write signals
BW1-2. In addition, Global Write (GW) is available for writing
all bytes at one time.
Compare cycles begin as a read cycle with output disabled so
that compare data can be loaded into the data input register.
The comparator compares the read data with the registered
input data and a match signal is generated. The match output
can be either in Pipeline or Flow Through modes controlled by
the FT signal.
Low power (Standby mode) is attained through the assertion of
the ZZ signal, or by stopping the clock (CLK). Memory data is
retained during Standby mode.
JTAG boundary scan interface is provided using IEEE standard
1149.1 protocol. Four pins--Test Data In (TDI), Test Data Out
(TDO), Test Clock (TCK) and Test Mode Select (TMS)--are
used to perform JTAG function.
The GS84118A operates on a 3.3 V power supply and all
inputs/outputs are 3.3 V- or 2.5 V-LVTTL-compatible.
Separate output (V
DDQ
) pins are used to allow both 3.3 V or
2.5 V IO interface.
* Pentium is a trademark of Intel Corp.
-166
-150
-133
-100
Pipeline
3-1-1-1
t
cycle
t
KQ
I
DD
6.0 ns
3.5 ns
310 mA
6.6 ns
3.8 ns
275 mA
7.5 ns
4.0 ns
250 mA
10 ns
4.5 ns
190 mA
Flow
Through
2-1-1-1
t
KQ
t
cycle
I
DD
8.5 ns
10 ns
190 mA
10 ns
10 ns
190 mA
11 ns
15 ns
140 mA
12 ns
15 ns
140 mA
Rev: 1.00 9/2002
2/27
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118AT/B-166/150/130/100
Pin Configuration
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
9
DQ
10
V
SS
V
DDQ
DQ
11
DQ
12
V
DD
NC
V
SS
DQ
13
DQ
14
V
DDQ
V
SS
DQ
15
DQ
16
DQ
P2
V
SS
V
DDQ
V
DDQ
V
SS
DQ
8
DQ
7
V
SS
VDDQ
DQ
6
DQ
5
V
SS
NC
V
DD
ZZ
DQ
4
DQ
3
V
DDQ
V
SS
DQ
2
DQ
1
V
SS
V
DDQ
LBO
A
5
A
4
A
3
A
2
A
1
A
0
TM
S
TDI
V
SS
V
DD
TDO
TCK
A
15
A
14
A
13
A
12
A
11
A
17
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
3
CLK
GW
BWE
V
DD
V
SS
OE
ADSC
ADSP
ADV
A
8
A
9
A
16
256K x 18
Top View
DQ
P1
A
10
NC
NC
NC
NC
NC
DE
MATCH
MOE
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.00 9/2002
4/27
2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118AT/B-166/150/130/100
Pin Description
Symbol
Description
A0A17
Address Input Signals
CLK
Clock Input Signal
BWE
Byte Write Enable Signal--The byte write enable signal needs to be combined with one of the four
byte write signals for a write operation to occur.
BW1
Byte Write signal for data outputs 1 thru 8
BW2
Byte Write signal for data outputs 9 thru 16
GW
Global Write Enable
CE1,CE2, CE3
Chip Enables
OE
Output Enable
ADV
Burst address advance
ADSP, ADSC
Address status signals
DQ1DQ16
Data Input and Output pins
DQP1DQP2
Parity Input and Output pins
MATCH
Match Output
MOE
Match Output Enable
DE
Data Enable--Data input registers are updated only when DE is active.
ZZ
Power down control--Application of ZZ will result in a low standby power consumption.
FT
Flow Through or Pipeline mode
LBO
Linear Order Burst mode
TMS
Test Mode Select
TDI
Test Data In
TDO
Test Data Out
TCK
Test Clock
V
DD
3.3 V power supply
V
SS
Ground
V
DDQ
2.5 V/3.3 V output power supply
NC
No Connect
PDF 
ZIP
