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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Preliminary

GS842Z18/36AB-180/166/150/100

4Mb Pipelined and Flow Through

Synchronous NBT SRAMs

180 MHz100 MHz

3.3 V V

2.5 V and 3.3 V V

DDQ

119-Bump BGA
Commercial Temp
Industrial Temp

Features

· 256K x 18 and 128K x 36 configurations
· User configurable Pipeline and Flow Through mode
· NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization

· Fully pin compatible with both pipelined and flow through

NtRAMTM, NoBLTM and ZBTTM SRAMs

· Pin-compatible with 2M, 8M, and 16M devices
· 3.3 V +10%/10% core power supply
· 2.5 V or 3.3 V I/O supply
· LBO pin for Linear or Interleave Burst mode
· Byte write operation (9-bit Bytes)
· 3 chip enable signals for easy depth expansion
· Clock Control, registered address, data, and control
· ZZ Pin for automatic power-down
· JEDEC-standard 119-bump BGA package

Functional Description

The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS842Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.

The GS842Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump BGA package.

180

166

150

100

Pipeline

3-1-1-1

tCycle

5.5 ns
3.2 ns

335 mA

6.0 ns
3.5 ns

310 mA

6.6 ns
3.8 ns

280 mA

10 ns

4.5 ns

190 mA

Flow

Through

2-1-1-1

tCycle

8 ns

9.1 ns

210 mA

8.5 ns

10 ns

190 mA

10 ns
12 ns

165 mA

12 ns
15 ns

135 mA

Clock

Address

Read/Write

Flow Through

Data I/O

Pipelined

Data I/O

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

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Preliminary

GS842Z18/36AB-180/166/150/100

GS842Z18A Pad Out

119 Bump BGA--Top View

DDQ

ADV

DDQ

CKE

DDQ

LBO

DDQ

TMS

TDI

TCK

TDO

DDQ

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Preliminary

GS842Z18/36AB-180/166/150/100

GS842Z36A Pad Out

119 Bump BGA--Top View

DDQ

ADV

DDQ

CKE

DDQ

LBO

DDQ

TMS

TDI

TCK

TDO

DDQ

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Preliminary

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GS842Z18/36A Pin Description

Symbol

Type

Description

, A

Address field LSBs and Address Counter Preset Inputs

Address Inputs

I/O

Data Input and Output pins

, B

Byte Write Enable for DQ

, DQ

I/Os; active low ( x36 Version)

Clock Input Signal; active high

CKE

Clock Input Buffer Enable; active low

Write Enable. Writes all enabled bytes; active low

, E

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

ADV

Burst address counter advance enable; active high

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

LBO

Linear Burst Order mode; active low

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

No Connect

TMS

Scan Test Mode Select

TDI

Scan Test Data In

TDO

Scan Test Data Out

TCK

Scan Test Clock

Core power supply

I/O and Core Ground

DDQ

Output driver power supply

Clock Input Signal; active high

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Preliminary

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Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipelined Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E

, E

and E

). Deassertion of any one of the Enable

inputs will deactivate the device.

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.

Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (B

, B

and B

) determine which bytes will be written. All or none may be activated. A write cycle

with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.

Flow through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.

Function

Read

Write Byte "a"

Write Byte "b"

Write Byte "c"

Write Byte "d"

Write all Bytes

Write Abort/NOP

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Preliminary

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Synchronous Truth Table

Operation

Type Address E

ZZ ADV W Bx G CKE CK

Notes

Deselect Cycle, Power Down

None

L-H High-Z

Deselect Cycle, Power Down

None

L-H High-Z

Deselect Cycle, Power Down

None

L-H High-Z

Deselect Cycle, Continue

None

L-H High-Z

Read Cycle, Begin Burst

External

L-H

Read Cycle, Continue Burst

L-H

1,10

NOP/Read, Begin Burst

External

L-H High-Z

Dummy Read, Continue Burst

L-H High-Z

1,2,10

Write Cycle, Begin Burst

External

L-H

Write Cycle, Continue Burst

L-H

1,3,10

NOP/Write Abort, Begin Burst

None

L-H High-Z

2,3

Write Abort, Continue Burst

L-H High-Z 1,2,3,10

Clock Edge Ignore, Stall

Current

L-H

Sleep Mode

None

High-Z

Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect

cycle is executed first

2. Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A write abort occurs when the W pin is

sampled low, but no byte write pins are active, so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write

cycles.

4. If CKE high occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE high occurs during a write cycle, the bus will

remain in High Z.

5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals

are low

6. All inputs, except G and ZZ, must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.

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Preliminary

GS842Z18/36AB-180/166/150/100

Deselect

New Read

New Write

Burst Read

Burst Write

Pipelined and Flow Through Read-Write Control State Diagram

Current State (n)

Next State (n+1)

Transition

Input Command Code

Key

Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

Clock (CK)

Command

Current State

Next State

n+1

n+2

n+3

Current State and Next State Definition for

Pipelined and Flow Through Read/Write Control State Diagram

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Intermediate

High Z

(Data In)

Data Out

(Q Valid)

High Z

B W

Pipeline Mode Data I/O State Diagram

Current State (n)

Next State (n+2)

Transition

Input Command Code

Key

Transition

Intermediate State (N+1)

Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Clock (CK)

Command

Current State

Intermediate

n+1

n+2

n+3

Current State and Next State Definition for

Pipeline Mode Data I/O State Diagram

Next State

State

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Preliminary

GS842Z18/36AB-180/166/150/100

High Z

(Data In)

Data Out

(Q Valid)

High Z

B W

Current State (n)

Next State (n+1)

Transition

Input Command Code

Key

Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Flow Through Mode Data I/O State Diagram

Clock (CK)

Command

Current State

Next State

n+1

n+2

n+3

Current State and Next State Definition for:

Pipelined and Flow Through Read Write Control State Diagram

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Preliminary

GS842Z18/36AB-180/166/150/100

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables
below for details.

FLXDriveTM

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Note:
There is a are pull-up devices on the LBO, ZQ, and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above table.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name

Pin Name

State

Function

Burst Order Control

LBO

Linear Burst

H or NC

Interleaved Burst

Output Register Control

Flow Through

H or NC

Pipeline

Power Down Control

L or NC

Active

Standby, I

= I

FLXDrive Output Impedance Control

High Drive (Low Impedance)

H or NC

Low Drive (High Impedance)

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0]

1st address

2nd address

3rd address

4th address

A[1:0]

1st address

2nd address

3rd address

4th address

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Preliminary

GS842Z18/36AB-180/166/150/100

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

2. The duration of

Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on Bump R5. Not all vendors offer this option, however, most mark Bump R5 as V

or V

DDQ

on pipelined parts and V

on flow

through parts. GSI NBT SRAMs are fully compatible with these sockets.

tZZR

tZZH

tZZS

~ ~

Sleep

~ ~

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Preliminary

GS842Z18/36AB-180/166/150/100

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.

Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V

DDQ

2.375 V

(i.e., 2.5 V I/O) and 3.6 V

DDQ

3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of

Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be 2 V > Vi < V

+2 V with a pulse width not to exceed 20% tKC.

Absolute Maximum Ratings

(All voltages reference to V

)

Symbol

Description

Value

Unit

Voltage on V

Pins

0.5 to 4.6

DDQ

Voltage in V

DDQ

Pins

0.5 to V

Voltage on Clock Input Pin

0.5 to 6

I/O

Voltage on I/O Pins

0.5 to V

DDQ

+0.5 (

4.6 V max.)

Voltage on Other Input Pins

0.5 to V

+0.5 (

4.6 V max.)

Input Current on Any Pin

+/20

OUT

Output Current on Any I/O Pin

+/20

Package Power Dissipation

1.5

STG

Storage Temperature

55 to 125

BIAS

Temperature Under Bias

55 to 125

Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Supply Voltage

3.135

3.3

3.6

I/O Supply Voltage

DDQ

2.375

2.5

Input High Voltage

1.7

+0.3

Input Low Voltage

0.3

0.8

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

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Preliminary

GS842Z18/36AB-180/166/150/100

Note: These parameters are sample tested.

Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.

Temperature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Capacitance

= 25

C, f = 1 MH

, V

= 3.3 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Input Capacitance

= 0 V

Input/Output Capacitance

I/O

OUT

= 0 V

Package Thermal Characteristics

Rating

Layer Board

Symbol

Max

Unit

Notes

Junction to Ambient (at 200 lfm)

single

C/W

1,2

Junction to Ambient (at 200 lfm)

four

C/W

1,2

Junction to Case (TOP)

C/W

20% tKC

2.0 V

50%

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

+ 2.0 V

50%

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Preliminary

GS842Z18/36AB-180/166/150/100

Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t

, t

OLZ

and t

OHZ

4. Device is deselected as defined by the Truth Table.

AC Test Conditions

Parameter

Conditions

Input high level

2.3 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

1.25 V

Output reference level

1.25 V

Output load

Fig. 1& 2

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

= 0 to V

1 uA

ZZ Input Current

INZZ

0 V

1 uA
1 uA

1 uA

300 uA

Mode Pin Input Current

INM

0 V

300 uA

1 uA

1 uA
1 uA

Output Leakage Current

Output Disable,

OUT

= 0 to V

1 uA

Output High Voltage

= 8 mA, V

DDQ

= 2.375 V

1.7 V

Output High Voltage

= 8 mA, V

DDQ

= 3.135 V

2.4 V

Output Low Voltage

= 8 mA

0.4 V

VT = 1.25 V

30pF

2.5 V

Output Load 1

Output Load 2

225

5pF

* Distributed Test Jig Capacitance

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Preliminary

GS842Z18/36AB-180/166/150/100

Operating Currents

Parameter Test Conditions Symbol

180

166

150

100

Unit

0 to

70°C

40 to

85°C

0 to

70°C

40 to

85°C

0 to

70°C

40 to

85°C

0 to

70°C

40 to

85°C

Operating

Current

Device Selected;

All other inputs

Output open

Pipeline

335

345

310

320

280

290

190

200

Flow-Thru

210

220

190

200

165

175

135

145

Standby

Current

0.2 V

Pipeline

Flow-Thru

Deselect

Current

Device Deselected;

All other inputs

Pipeline

Flow-Thru

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Preliminary

GS842Z18/36AB-180/166/150/100

AC Electrical Characteristics

Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Parameter

Symbol

-180

-166

-150

-100

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Pipeline

Clock Cycle Time

tKC

5.5

6.0

6.7

Clock to Output Valid

tKQ

3.2

3.5

3.8

4.5

Clock to Output Invalid

tKQX

1.5

Clock to Output in Low-Z

tLZ

1.5

Flow

Through

Clock Cycle Time

tKC

9.1

10.0

12.0

15.0

Clock to Output Valid

tKQ

8.0

8.5

10.0

12.0

Clock to Output Invalid

tKQX

3.0

Clock to Output in Low-Z

tLZ

3.0

Clock HIGH Time

tKH

1.3

Clock LOW Time

tKL

1.5

Clock to Output in High-Z

tHZ

1.5 3.2

1.5

3.5

1.5 3.8

1.5

G to Output Valid

tOE

3.2

3.5

3.8

G to output in Low-Z

tOLZ

G to output in High-Z

tOHZ

3.2

3.5

3.8

Setup time

1.5

2.0

Hold time

0.5

ZZ setup time

tZZS

ZZ hold time

tZZH

ZZ recovery

tZZR

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Pipeline Mode Read/Write Cycle Timing

*Note: E = High (False) if E

= 1 or E

= 0 or E

= 1

CKE

ADV

tKH

tKL

tKC

D(A1)

D(A2)

Q(A3)

Q(A6)

D(A5)

tLZ

tKQ

tKQX

tOHZ

tOLZ

tKQX

tHZ

tOE

COMMAND

Write
D(A1)

Write
D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

Read
Q(A4)

BURST
Read
Q(A4+1)

Write
D(A5)

Read
Q(A6)

Write
D(A7)

DESELECT

DON'T CARE

UNDEFINED

Q(A4)

(A4+1)

(A2+1)

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Preliminary

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Flow Through Mode Read/Write Cycle Timing

*Note: E = High (False) if E

= 1 or E

= 0 or E

= 1

CKE

ADV

tKH

tKL

tKC

COMMAND

Write
D(A1)

Write
D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

Read
Q(A4)

BURST
Read
Q(A4+1)

Write
D(A5)

Read
Q(A6)

Write
D(A7)

DESELECT

DON'T CARE

UNDEFINED

D(A1)

D(A2)

Q(A3)

Q(A6)

D(A5)

tLZ

tKQ

tKQX

tOLZ

tKQX

tHZ

tOE

Q(A4)

(A4+1)

(A2+1)

tOHZ

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Preliminary

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JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard
(commonly referred to as JTAG). The JTAG Port input interface levels scale with V

. The JTAG output drivers are powered by V

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI,
and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may
be left floating or tied to either V

or V

. TDO should be left unconnected.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied
to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes
serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data
register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The
Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset
state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's
JTAG Port to another device in the scan chain with as little delay as possible.

JTAG Pin Descriptions

Pin

Pin Name

I/O

Description

TCK

Test Clock

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.

TMS

Test Mode Select

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.

TDI

Test Data In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.

TDO

Test Data Out

Out

Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.

Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

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Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are
then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also
includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan
Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the
contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is
moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with
the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the
register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Code

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

x36

X X X X

0 0 1 1 0 1 1 0 0 1

x18

X X X X

0 0 1 1 0 1 1 0 0 1

Instruction Register

ID Code Register

Boundary Scan Register

· · ·

31 30 29

· · ·

Bypass Register

TDI

TDO

TMS

TCK

Test Access Port (TAP) Controller

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Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private)
instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed
ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the
RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the
controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially
loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions
only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

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SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

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JTAG TAP Instruction Set Summary

Instruction

Code

Description

Notes

EXTEST

000

Places the Boundary Scan Register between TDI and TDO.

IDCODE

001

Preloads ID Register and places it between TDI and TDO.

1, 2

SAMPLE-Z

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.

RFU

011

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

SAMPLE/PRELOAD

100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

GSI

101

GSI private instruction.

RFU

110

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

BYPASS

111

Places Bypass Register between TDI and TDO.

Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

3.3 V Test Port Input High Voltage

IHJ3

2.0

DD3

+0.3

3.3 V Test Port Input Low Voltage

ILJ3

0.3

0.8

2.5 V Test Port Input High Voltage

IHJ2

0.6 * V

DD2

+0.3

2.5 V Test Port Input Low Voltage

ILJ2

0.3

0.3 * V

DD2

TMS, TCK and TDI Input Leakage Current

INHJ

300

TMS, TCK and TDI Input Leakage Current

INLJ

100

TDO Output Leakage Current

OLJ

Test Port Output High Voltage

OHJ

1.7

5, 6

Test Port Output Low Voltage

OLJ

0.4

5, 7

Test Port Output CMOS High

OHJC

DDQ

100 mV

5, 8

Test Port Output CMOS Low

OLJC

100 mV

5, 9

Notes:
1. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. V

ILJ

DDn

3. 0 V

ILJn

4. Output Disable, V

OUT

= 0 to V

DDn

5. The TDO output driver is served by the V

DDQ

supply.

6. I

OHJ

= 4 mA

7. I

OLJ

= + 4 mA

8. I

OHJC

= 100 uA

9. I

OHJC

= +100 uA

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Package Dimensions--119-Bump BGA

BPR 1999.05.18

Pin 1
Corner

Package Dimensions--119-Pin BGA

Unit: mm

Symbol

Description

Min. Nom. Max

Width

13.8

14.0

14.2

Length

21.8

22.0

22.2

Package Height (including ball)

2.40

Ball Size

0.60

0.75

0.90

Ball Height

0.50

0.60

0.70

Package Height (excluding balls)

1.46

1.70

Width between Balls

1.27

Package Height above board

0.80

0.90

1.00

Cut-out Package Width

12.00

Foot Length

19.50

Width of package between balls

7.62

Length of package between balls

20.32

Variance of Ball Height

0.15

Bottom View

Top View

Side View

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Ordering Information--GSI NBT Synchronous SRAM

Org

Part Number

Type

Package

Speed

(MHz/ns)

Status

256K x 18

GS842Z18AB-180

NBT Pipeline/Flow Through

BGA

180/8

256K x 18

GS842Z18AB-166

NBT Pipeline/Flow Through

BGA

166/8.5

256K x 18

GS842Z18AB-150

NBT Pipeline/Flow Through

BGA

150/10

256K x 18

GS842Z18AB-100

NBT Pipeline/Flow Through

BGA

100/12

128K x 36

GS842Z36AB-180

NBT Pipeline/Flow Through

BGA

180/8

128K x 36

GS842Z36AB-166

NBT Pipeline/Flow Through

BGA

166/8.5

128K x 36

GS842Z36AB-150

NBT Pipeline/Flow Through

BGA

150/10

128K x 36

GS842Z36AB-100

NBT Pipeline/Flow Through

BGA

100/12

256K x 18

GS842Z18AB-180I

NBT Pipeline/Flow Through

BGA

180/8

256K x 18

GS842Z18AB-166I

NBT Pipeline/Flow Through

BGA

166/8.5

256K x 18

GS842Z18AB-150I

NBT Pipeline/Flow Through

BGA

150/10

256K x 18

GS842Z18AB-100I

NBT Pipeline/Flow Through

BGA

100/12

128K x 36

GS842Z36AB-180I

NBT Pipeline/Flow Through

BGA

180/8

128K x 36

GS842Z36AB-166I

NBT Pipeline/Flow Through

BGA

166/8.5

128K x 36

GS842Z36AB-150I

NBT Pipeline/Flow Through

BGA

150/10

128K x 36

GS842Z36AB-100I

NBT Pipeline/Flow Through

BGA

100/12

Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS842Z36AB-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. T

= I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some

of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

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4Mb Synchronous NBT Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Page /Revisions/Reason

842Z18A_r1

· Creation of new datasheet

842Z18A_r1;

842Z18A_r1_01

Content

· Updated power numbers in table on page 1 and Operating

Currents table

· Updated pinout for x18
· Updated Pin Description table
· Removed ByteSafe references
· Changed DP and QE to NC
· Delete PE from entire document (changed to NC)

842Z18A_r1_01;

842Z18A_r1_02

Content

· Removed 200 MHz speed bin
· Removed pin locations from pin description table

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS842Z18AB-100I

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS842Z18AB-100I