ChipFind - документация

Электронный компонент: GS8642Z18

Скачать:  PDF   ZIP

Document Outline

Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz167 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119- & 209-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.02 5/2005
1/34
2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAMTM, NoBLTM and
ZBTTM SRAMs
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 119- or 209-bump BGA package
Pb-Free 119- and 209-bump BGA packages available
Functional Description
The GS8642Z18/36/72 is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8642Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8642Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
Parameter Synopsis
-300
-250
-200
-167
Unit
Pipeline
3-1-1-1
t
KQ
(x18/x36)
t
KQ
(x72)
tCycle
2.3
3.0
3.3
2.5
3.0
4.0
3.0
3.0
5.0
3.5
3.5
6.0
ns
ns
ns
Curr (x18)
Curr (x36)
Curr (x72)
400
480
590
340
410
520
290
350
435
260
305
380
mA
mA
mA
Flow Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
8.0
8.0
ns
ns
Curr (x18)
Curr (x36)
Curr (x72)
285
330
425
245
280
370
220
250
315
210
240
300
mA
mA
mA
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
2/34
2004, GSI Technology
GS8642Z72C Pad Out209-Bump BGA--Top View
1
2
3
4
5
6
7
8
9
10
11
A
DQ
G
DQ
G
A
E2
A
ADV
A
E3
A
DQ
B
DQ
B
A
B
DQ
G
DQ
G
BC
BG
NC
W
A
BB
BF
DQ
B
DQ
B
B
C
DQ
G
DQ
G
BH
BD
NC
E1
NC
BE
BA
DQ
B
DQ
B
C
D
DQ
G
DQ
G
V
SS
NC
NC
G
NC
NC
V
SS
DQ
B
DQ
B
D
E
DQP
G
DQP
C
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
DQP
F
DQP
B
E
F
DQ
C
DQ
C
V
SS
V
SS
V
SS
ZQ
V
SS
V
SS
V
SS
DQ
F
DQ
F
F
G
DQ
C
DQ
C
V
DDQ
V
DDQ
V
DD
MCH
V
DD
V
DDQ
V
DDQ
DQ
F
DQ
F
G
H
DQ
C
DQ
C
V
SS
V
SS
V
SS
MCL
V
SS
V
SS
V
SS
DQ
F
DQ
F
H
J
DQ
C
DQ
C
V
DDQ
V
DDQ
V
DD
MCH
V
DD
V
DDQ
V
DDQ
DQ
F
DQ
F
J
K
NC
NC
CK
NC
V
SS
CKE
V
SS
NC
NC
NC
NC
K
L
DQ
H
DQ
H
V
DDQ
V
DDQ
V
DD
FT
V
DD
V
DDQ
V
DDQ
DQ
A
DQ
A
L
M
DQ
H
DQ
H
V
SS
V
SS
V
SS
MCL
V
SS
V
SS
V
SS
DQ
A
DQ
A
M
N
DQ
H
DQ
H
V
DDQ
V
DDQ
V
DD
MCH
V
DD
V
DDQ
V
DDQ
DQ
A
DQ
A
N
P
DQ
H
DQ
H
V
SS
V
SS
V
SS
ZZ
V
SS
V
SS
V
SS
DQ
A
DQ
A
P
R
DQP
D
DQP
H
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
DQP
A
DQP
E
R
T
DQ
D
DQ
D
V
SS
NC
NC
LBO
NC
NC
V
SS
DQ
E
DQ
E
T
U
DQ
D
DQ
D
NC
A
A
A
A
A
NC
DQ
E
DQ
E
U
V
DQ
D
DQ
D
A
A
A
A1
A
A
A
DQ
E
DQ
E
V
W
DQ
D
DQ
D
TMS
TDI
A
A0
A
TDO
TCK
DQ
E
DQ
E
W
11 x 19 Bump BGA--14 x 22 mm
2
Body--1 mm Bump Pitch
(Package C)
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
3/34
2004, GSI Technology
GS8642Z72 209-Bump BGA Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
An
I
Address Inputs
DQ
A
DQ
B
DQ
C
DQ
D
DQ
E
DQ
F
DQ
G
DQ
H
I/O
Data Input and Output pins
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low
B
C
,B
D
I
Byte Write Enable for DQ
C
, DQ
D
I/Os; active low
B
E
, B
F
, B
G
,B
H
I
Byte Write Enable for DQ
E
, DQ
F
, DQ
G
, DQ
H
I/Os; active low
NC
--
No Connect
CK
I
Clock Input Signal; active high
E
1
I
Chip Enable; active low
E
3
I
Chip Enable; active low
E
2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
MCH
I
Must Connect High
MCH
I
Must Connect High
MCL
Must Connect Low
W
I
Write Enable; active low
ZQ
I
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive],
High = High Impedance [Low Drive]
CKE
I
Clock Enable; active low
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
4/34
2004, GSI Technology
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
V
DD
I
Core power supply
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
GS8642Z72 209-Bump BGA Pin Description
Symbol
Type
Description
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
5/34
2004, GSI Technology
GS8642Z36B Pad Out119-Bump BGA--Top View
1
2
3
4
5
6
7
A
V
DDQ
A
A
A
A
A
V
DDQ
A
B
NC
E2
A
ADV
A
E3
NC
B
C
NC
A
A
V
DD
A
A
NC
C
D
DQC
DQPC
V
SS
ZQ
V
SS
DQPB
DQB
D
E
DQC
DQC
V
SS
E1
V
SS
DQB
DQB
E
F
V
DDQ
DQC
V
SS
G
V
SS
DQB
V
DDQ
F
G
DQC
DQC
BC
A
BB
DQB
DQB
G
H
DQC
DQC
V
SS
W
V
SS
DQB
DQB
H
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
J
K
DQD
DQD
V
SS
CK
V
SS
DQA
DQA
K
L
DQD
DQD
BD
NC
BA
DQA
DQA
L
M
V
DDQ
DQD
V
SS
CKE
V
SS
DQA
V
DDQ
M
N
DQD
DQD
V
SS
A1
V
SS
DQA
DQA
N
P
DQD
DQPD
V
SS
A0
V
SS
DQPA
DQA
P
R
NC
A
LBO
V
DD
FT
A
NC
R
T
NC
A
A
A
A
A
ZZ
T
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
U
7 x 17 Bump BGA--14 x 22 mm
2
Body--1.27 mm Bump Pitch
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
6/34
2004, GSI Technology
GS8642Z18B Pad Out119-Bump BGA--Top View
1
2
3
4
5
6
7
A
V
DDQ
A
A
A
A
A
V
DDQ
A
B
NC
E2
A
ADV
A
E3
NC
B
C
NC
A
A
V
DD
A
A
NC
C
D
DQB
NC
V
SS
ZQ
V
SS
DQPA
NC
D
E
NC
DQB
V
SS
E1
V
SS
NC
DQA
E
F
V
DDQ
NC
V
SS
G
V
SS
DQA
V
DDQ
F
G
NC
DQB
BB
A
NC
NC
DQA
G
H
DQB
NC
V
SS
W
V
SS
DQA
NC
H
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
J
K
NC
DQB
V
SS
CK
V
SS
NC
DQA
K
L
DQB
NC
NC
NC
BA
DQA
NC
L
M
V
DDQ
DQB
V
SS
CKE
V
SS
NC
V
DDQ
M
N
DQB
NC
V
SS
A1
V
SS
DQA
NC
N
P
NC
DQPB
V
SS
A0
V
SS
NC
DQA
P
R
NC
A
LBO
V
DD
FT
A
NC
R
T
A
A
A
A
A
A
ZZ
T
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
U
7 x 17 Bump BGA--14 x 22 mm
2
Body--1.27 mm Bump Pitch
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
7/34
2004, GSI Technology
GS8642Z18/36 119-Bump BGA Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
An
I
Address Inputs
DQ
A
DQ
B
DQ
C
DQ
D
I/O
Data Input and Output pins
B
A
, B
B
, B
C
, B
D
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
NC
--
No Connect
CK
I
Clock Input Signal; active high
CKE
I
Clock Enable; active low
W
I
Write Enable; active low
E
1
I
Chip Enable; active low
E
3
I
Chip Enable; active low
E
2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable
ZZ
I
Sleep mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
ZQ
I
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
V
DD
I
Core power supply
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
BPR1999.05.18
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
8/34
2004, GSI Technology
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
W
B
A
B
B
B
C
B
D
Read
H
X
X
X
X
Write Byte "a"
L
L
H
H
H
Write Byte "b"
L
H
L
H
H
Write Byte "c"
L
H
H
L
H
Write Byte "d"
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E
1
, E
2,
and E
3
) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Synchronous Truth Table
Operation
Type Address CK CKE ADV W Bx E
1
E
2
E
3
G ZZ
DQ
Notes
Read Cycle, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
L
L
Q
Read Cycle, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
L
L
Q
1,10
NOP/Read, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
H
L
High-Z
2
Dummy Read, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
H
L
High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L-H
L
L
L
L
L
H
L
X
L
D
3
Write Cycle, Continue Burst
B
Next
L-H
L
H
X
L
X
X
X
X
L
D
1,3,10
Write Abort, Continue Burst
B
Next
L-H
L
H
X
H
X
X
X
X
L
High-Z 1,2,3,10
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
H
X
X
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
X
H
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
L
X
X
L
High-Z
Deselect Cycle
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
1
Deselect Cycle, Continue
D
None
L-H
L
H
X
X
X
X
X
X
L
High-Z
1
Sleep Mode
None
X
X
X
X
X
X
X
X
X
H
High-Z
Clock Edge Ignore, Stall
Current
L-H
H
X
X
X
X
X
X
X
L
-
4
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
9/34
2004, GSI Technology
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
10/34
2004, GSI Technology
Deselect
New Read
New Write
Burst Read
Burst Write
W
R
B
R
B
W
D
D
B
B
W
R
D
B
W
R
D
D
Current State (n)
Next State (n+1)
Transition
Input Command Code
Key
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State
Next State
n
n+1
n+2
n+3
Current State and Next State Definition for
Pipelined and Flow through Read/Write Control State Diagram
W
R
Pipelined and Flow Through Read Write Control State Diagram
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
11/34
2004, GSI Technology
Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
Intermediate
High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Current State (n)
Next State (n+2)
Transition
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Intermediate
n
n+1
n+2
n+3
Current State and Next State Definition for
Pipeline Mode Data I/O State Diagram
Next State
State
Pipeline Mode Data I/O State Diagram
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
12/34
2004, GSI Technology
High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Current State (n)
Next State (n+1)
Transition
Input Command Code
Key
Notes
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Next State
n
n+1
n+2
n+3
Current State and Next State Definition for:
Pipeline and Flow Through Read Write Control State Diagram
Flow Through Mode Data I/O State Diagram
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
13/34
2004, GSI Technology
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDriveTM
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, I
DD
= I
SB
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
Note:
Thereis a are pull-up devicesonthe ZQ and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected and
the chip will operate in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
14/34
2004, GSI Technology
Burst Counter Sequences
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tZZR
tZZH
tZZS
tKL
tKL
tKH
tKH
tKC
tKC
CK
ZZ
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal. Not
all vendors offer this option, however most mark the pin V
DD
or V
DDQ
on pipelined parts and V
SS
on flow through parts. GSI NBT
SRAMs are fully compatible with these sockets. Other vendors mark the pin as a No Connect (NC). GSI RAMs have an internal
pull-up device on the FT pin so a floating FT pin will result in pipelined operation. If the part being replaced is a pipelined mode
part, the GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device,
the pin will need to be pulled low for correct operation.
Absolute Maximum Ratings
(All voltages reference to V
SS
)
Symbol
Description
Value
Unit
V
DD
Voltage on V
DD
Pins
0.5 to 4.6
V
V
DDQ
Voltage in V
DDQ
Pins
0.5 to 4.6
V
V
I/O
Voltage on I/O Pins
0.5 to V
DDQ
+0.5 (
4.6 V max.)
V
V
IN
Voltage on Other Input Pins
0.5 to V
DD
+0.5 (
4.6 V max.)
V
I
IN
Input Current on Any Pin
+/20
mA
I
OUT
Output Current on Any I/O Pin
+/20
mA
P
D
Package Power Dissipation
1.5
W
T
STG
Storage Temperature
55 to 125
o
C
T
BIAS
Temperature Under Bias
55 to 125
o
C
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
15/34
2004, GSI Technology
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
3.3 V Supply Voltage
V
DD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
V
DD2
2.3
2.5
2.7
V
3.3 V V
DDQ
I/O Supply Voltage
V
DDQ3
3.0
3.3
3.6
V
2.5 V V
DDQ
I/O Supply Voltage
V
DDQ2
2.3
2.5
2.7
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
16/34
2004, GSI Technology
V
DDQ3
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
2.0
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.8
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
2.0
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.8
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
V
DDQ2
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
0.6*V
DD
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.3*V
DD
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
0.6*V
DD
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.3*V
DD
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
T
A
0
25
70
C
2
Ambient Temperature (Industrial Range Versions)
T
A
40
25
85
C
2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
17/34
2004, GSI Technology
20% tKC
V
SS
2.0 V
50%
V
SS
V
IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
V
DD
+ 2.0 V
50%
V
DD
V
IL
Capacitance
o
C, f = 1 MH
Z
, V
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
C
IN
V
IN
= 0 V
4
5
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0 V
6
7
pF
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
Input high level
V
DD
0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DDQ
/2
Output reference level
V
DDQ
/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DQ
V
DDQ/2
50
30pF
*
Output Load 1
* Distributed Test Jig Capacitance
(T
A
= 25
= 2.5 V)
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
2 uA
2 uA
ZZInput Current
I
IN1
V
DD
V
IN
V
IH
0 V
V
IN
V
IH
1 uA
1 uA
1 uA
100 uA
Output Leakage Current (x36/x72)
I
OL
Output Disable, V
OUT
= 0 to V
DD
1 uA
1 uA
Output Leakage Current (x18)
I
OL
Output Disable, V
OUT
= 0 to V
DD
1 uA
1 uA
Output High Voltage
V
OH2
I
OH
= 8 mA, V
DDQ
= 2.375 V
1.7 V
--
Output High Voltage
V
OH3
I
OH
= 8 mA, V
DDQ
= 3.135 V
2.4 V
--
Output Low Voltage
V
OL
I
OL
= 8 mA
--
0.4 V
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
18/34
2004, GSI Technology
Operating Currents
Parameter
Test Conditions
Mode
Symbol
-300
-250
-200
-167
Unit
0
to
70C
40
to
85C
0
to
70C
40
to
85C
0
to
70C
40
to
85C
0
to
70C
40
to
85C
Operating
Current
Device Selected;
All other inputs
V
IH
or
V
IL
Output open
(x72)
Pipeline
I
DD
I
DDQ
520
70
540
70
460
60
480
60
385
50
405
50
340
40
360
40
mA
Flow
Through
I
DD
I
DDQ
375
50
385
50
330
40
340
40
285
30
295
30
270
30
280
30
mA
(x32/
x36)
Pipeline
I
DD
I
DDQ
420
60
440
60
360
50
380
50
310
40
330
40
270
35
290
35
mA
Flow
Through
I
DD
I
DDQ
300
30
320
30
255
25
275
25
230
20
250
20
220
20
240
20
mA
(x18)
Pipeline
I
DD
I
DDQ
370
30
390
30
315
25
335
25
270
20
290
20
240
20
260
20
mA
Flow
Through
I
DD
I
DDQ
270
15
290
15
230
15
250
15
205
15
225
15
195
15
215
15
mA
Standby
Current
ZZ
V
DD
0.2 V
--
Pipeline
I
SB
100
120
100
120
100
120
100
120
mA
Flow
Through
I
SB
100
120
100
120
100
120
100
120
mA
Deselect
Current
Device Deselected;
All other inputs
V
IH
or
V
IL
--
Pipeline
I
DD
150
165
140
155
130
146
125
140
mA
Flow
Through
I
DD
135
150
125
140
120
135
120
135
mA
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
19/34
2004, GSI Technology
Notes:
1. I
DD
and I
DDQ
apply to any combination of V
DD3
, V
DD2
, V
DDQ3
, and V
DDQ2
operation.
2. All parameters listed are worst case scenario.
AC Electrical Characteristics
Parameter
Symbol
-300
-250
-200
-167
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
3.3
--
4.0
--
5.0
--
6.0
--
ns
Clock to Output Valid
(x18/x36)
tKQ
--
2.3
--
2.5
--
3.0
--
3.5
ns
Clock to Output Valid
(x72)
tKQ
--
3.0
--
3.0
--
3.0
--
3.5
ns
Clock to Output Invalid
tKQX
1.5
--
1.5
--
1.5
--
1.5
--
ns
Clock to Output in Low-Z
tLZ
1
1.5
--
1.5
--
1.5
--
1.5
--
ns
Setup time
tS
1.1
--
1.2
--
1.4
--
1.5
--
ns
Hold time
tH
0.1
--
0.2
--
0.4
--
0.5
--
ns
Flow
Through
Clock Cycle Time
tKC
5.5
--
6.5
--
7.5
--
8.0
--
ns
Clock to Output Valid
tKQ
--
5.5
--
6.5
--
7.5
--
8.0
ns
Clock to Output Invalid
tKQX
3.0
--
3.0
--
3.0
--
3.0
--
ns
Clock to Output in Low-Z
tLZ
1
3.0
--
3.0
--
3.0
--
3.0
--
ns
Setup time
tS
1.5
--
1.5
--
1.5
--
1.5
--
ns
Hold time
tH
0.5
--
0.5
--
0.5
--
0.5
--
ns
Clock HIGH Time
tKH
1.0
--
1.3
--
1.3
--
1.3
--
ns
Clock LOW Time
tKL
1.2
--
1.5
--
1.5
--
1.5
--
ns
Clock to Output in
High-Z (x18/x36)
tHZ
1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0
ns
Clock to Output in
High-Z (x72)
tHZ
1
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
G to Output Valid
(x18/x36)
tOE
--
2.3
--
2.5
--
3.0
--
3.5
ns
G to Output Valid
(x72)
tOE
--
3.0
--
3.0
--
3.0
--
3.5
ns
G to output in Low-Z
tOLZ
1
0
--
0
--
0
--
0
--
ns
G to output in High-Z
(x18/36)
tOHZ
1
--
2.3
--
2.5
--
3.0
--
3.0
ns
G to output in High-Z
(x72)
tOHZ
1
--
3.0
--
3.0
--
3.0
--
3.0
ns
ZZ setup time
tZZS
2
5
--
5
--
5
--
5
--
ns
ZZ hold time
tZZH
2
1
--
1
--
1
--
1
--
ns
ZZ recovery
tZZR
20
--
20
--
20
--
20
--
ns
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
20/34
2004, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
21/34
2004, GSI Technology
Pipeline Mode Timing (NBT)
Write A
Read B
Suspend
Read C
Write D
writeno-op
Read E
Deselect
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKC
tKL
tKL
tKH
tKH
A
B
C
D
E
D(A)
D(D)
Q(E)
Q(B)
Q(C)
CK
A
CKE
E*
ADV
W
Bn
DQ
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
22/34
2004, GSI Technology
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
D(A)
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
tKQX
tKQ
tLZ
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKC
tKL
tKL
tKH
tKH
A
B
C
D
E
F
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E
ADV
W
Bn
A0An
DQ
G
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
DD
. The JTAG output
drivers are powered by V
DDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI
Test Data In
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO
Test Data Out
Out
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
23/34
2004, GSI Technology
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
108
1
0
Control Signals
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
24/34
2004, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
r
esence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x72
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0 0 1 1 0 1 1 0 0 1
1
x36
X X X X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x32
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x18
X X X X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
1
0
0
0 0 1 1 0 1 1 0 0 1
1
x16
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0 0 1 1 0 1 1 0 0 1
1
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
25/34
2004, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
26/34
2004, GSI Technology
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is
still determined by its input pins.
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
27/34
2004, GSI Technology

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
V
IHJ3
2.0
V
DD3
+0.3
V
1
3.3 V Test Port Input Low Voltage
V
ILJ3
0.3
0.8
V
1
2.5 V Test Port Input High Voltage
V
IHJ2
0.6 * V
DD2
V
DD2
+0.3
V
1
2.5 V Test Port Input Low Voltage
V
ILJ2
0.3
0.3 * V
DD2
V
1
TMS, TCK and TDI Input Leakage Current
I
INHJ
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
I
INLJ
1
100
uA
3
TDO Output Leakage Current
I
OLJ
1
1
uA
4
Test Port Output High Voltage
V
OHJ
1.7
--
V
5, 6
Test Port Output Low Voltage
V
OLJ
--
0.4
V
5, 7
Test Port Output CMOS High
V
OHJC
V
DDQ
100 mV
--
V
5, 8
Test Port Output CMOS Low
V
OLJC
--
100 mV
V
5, 9
Notes:
1. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. V
ILJ
V
IN
V
DDn
3. 0 V
V
IN
V
ILJn
4. Output Disable, V
OUT
= 0 to V
DDn
5. The TDO output driver is served by the V
DDQ
supply.
6. I
OHJ
= 4 mA
7. I
OLJ
= + 4 mA
8. I
OHJC
= 100 uA
9. I
OLJC
= +100 uA
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
28/34
2004, GSI Technology
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
V
DD
0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DDQ
/2
Output reference level
V
DDQ
/2
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
29/34
2004, GSI Technology
JTAG Port Timing Diagram
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKL
tTKL
tTKH
tTKH
tTKC
tTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
50
--
ns
TCK Low to TDO Valid
tTKQ
--
20
ns
TCK High Pulse Width
tTKH
20
--
ns
TCK Low Pulse Width
tTKL
20
--
ns
TDI & TMS Set Up Time
tTS
10
--
ns
TDI & TMS Hold Time
tTH
10
--
ns
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
30/34
2004, GSI Technology
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
A
A1
C
b
e
e
E
E1
D1
D
aaa
Bottom View
Side View
Symbol
Min
Typ
Max
Units
A
1.70
mm
A1
0.40
0.50
0.60
mm
b
0.50
0.60
0.70
mm
c
0.31
0.36
0.38
mm
D
21.9
22.0
22.1
mm
D1
18.0 (BSC)
mm
E
13.9
14.0
14.1
mm
E1
10.0 (BSC)
mm
e
1.00 (BSC)
mm
aaa
0.15
mm
Rev 1.0
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
31/34
2004, GSI Technology
Package Dimensions--119-Bump FPBGA (Package B, Variation 2
)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1 2 3 4 5 6 7
7 6 5 4 3 2 1
A1
TOP VIEW
A1
BOTTOM VIEW
1.27
7.62
1.
27
20
.3
2
140.10
220.10
B
A
0.20(4x)
0.10
0.30
C
C A B
S
S
0.60~0.90 (119x)
C
SEATING PLANE
0.
15
C
0.
50
~0
.70
1.
86.
0.
13
0.
700
.
0
5
0.1
5
C
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.
56
0
.0
5
S
S
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
32/34
2004, GSI Technology

Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
4M x 18
GS8642Z18B-300
NBT Pipeline/Flow Through
119 BGA (var.2)
300/5.5
C
4M x 18
GS8642Z18B-250
NBT Pipeline/Flow Through
119 BGA (var.2)
250/6.5
C
4M x 18
GS8642Z18B-200
NBT Pipeline/Flow Through
119 BGA (var.2)
200/7.5
C
4M x 18
GS8642Z18B-167
NBT Pipeline/Flow Through
119 BGA (var.2)
167/8
C
2M x 36
GS8642Z36B-300
NBT Pipeline/Flow Through
119 BGA (var.2)
300/5.5
C
2M x 36
GS8642Z36B-250
NBT Pipeline/Flow Through
119 BGA (var.2)
250/6.5
C
2M x 36
GS8642Z36B-200
NBT Pipeline/Flow Through
119 BGA (var.2)
200/7.5
C
2M x 36
GS8642Z36B-167
NBT Pipeline/Flow Through
119 BGA (var.2)
167/8
C
1M x 72
GS8642Z72C-300
NBT Pipeline/Flow Through
209 BGA
300/5.5
C
1M x 72
GS8642Z72C-250
NBT Pipeline/Flow Through
209 BGA
250/6.5
C
1M x 72
GS8642Z72C-200
NBT Pipeline/Flow Through
209 BGA
200/7.5
C
1M x 72
GS8642Z72C-167
NBT Pipeline/Flow Through
209 BGA
167/8
C
4M x 18
GS8642Z18B-300I
NBT Pipeline/Flow Through
119 BGA (var.2)
300/5.5
I
4M x 18
GS8642Z18B-250I
NBT Pipeline/Flow Through
119 BGA (var.2)
250/6.5
I
4M x 18
GS8642Z18B-200I
NBT Pipeline/Flow Through
119 BGA (var.2)
200/7.5
I
4M x 18
GS8642Z18B-167I
NBT Pipeline/Flow Through
119 BGA (var.2)
167/8
I
2M x 36
GS8642Z36B-300I
NBT Pipeline/Flow Through
119 BGA (var.2)
300/5.5
I
2M x 36
GS8642Z36B-250I
NBT Pipeline/Flow Through
119 BGA (var.2)
250/6.5
I
2M x 36
GS8642Z36B-200I
NBT Pipeline/Flow Through
119 BGA (var.2)
200/7.5
I
2M x 36
GS8642Z36B-167I
NBT Pipeline/Flow Through
119 BGA (var.2)
167/8
I
1M x 72
GS8642Z72C-300I
NBT Pipeline/Flow Through
209 BGA
300/5.5
I
1M x 72
GS8642Z72C-250I
NBT Pipeline/Flow Through
209 BGA
250/6.5
I
1M x 72
GS8642Z72C-200I
NBT Pipeline/Flow Through
209 BGA
200/7.5
I
1M x 72
GS8642Z72C-167I
NBT Pipeline/Flow Through
209 BGA
167/8
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8642Z18B-167IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
33/34
2004, GSI Technology
4M x 18
GS8642Z18GB-300
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
300/5.5
C
4M x 18
GS8642Z18GB-250
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
250/6.5
C
4M x 18
GS8642Z18GB-200
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
200/7.5
C
4M x 18
GS8642Z18GB-167
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
167/8
C
2M x 36
GS8642Z36GB-300
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
300/5.5
C
2M x 36
GS8642Z36GB-250
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
250/6.5
C
2M x 36
GS8642Z36GB-200
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
200/7.5
C
2M x 36
GS8642Z36GB-167
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
167/8
C
1M x 72
GS8642Z72GC-300
NBT Pipeline/Flow Through
Pb-Free 209 BGA
300/5.5
C
1M x 72
GS8642Z72GC-250
NBT Pipeline/Flow Through
Pb-Free 209 BGA
250/6.5
C
1M x 72
GS8642Z72GC-200
NBT Pipeline/Flow Through
Pb-Free 209 BGA
200/7.5
C
1M x 72
GS8642Z72GC-167
NBT Pipeline/Flow Through
Pb-Free 209 BGA
167/8
C
4M x 18
GS8642Z18GB-300I
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
300/5.5
I
4M x 18
GS8642Z18GB-250I
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
250/6.5
I
4M x 18
GS8642Z18GB-200I
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
200/7.5
I
4M x 18
GS8642Z18GB-167I
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
167/8
I
2M x 36
GS8642Z36GB-300I
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
300/5.5
I
2M x 36
GS8642Z36GB-250I
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
250/6.5
I
2M x 36
GS8642Z36GB-200I
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
200/7.5
I
2M x 36
GS8642Z36GB-167I
NBT Pipeline/Flow Through
Pb-Free 119 BGA (var.2)
167/8
I
1M x 72
GS8642Z72GC-300I
NBT Pipeline/Flow Through
Pb-Free 209 BGA
300/5.5
I
1M x 72
GS8642Z72GC-250I
NBT Pipeline/Flow Through
Pb-Free 209 BGA
250/6.5
I
1M x 72
GS8642Z72GC-200I
NBT Pipeline/Flow Through
Pb-Free 209 BGA
200/7.5
I
1M x 72
GS8642Z72GC-167I
NBT Pipeline/Flow Through
Pb-Free 209 BGA
167/8
I
Ordering Information for GSI Synchronous Burst RAMs
(Cont.)
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8642Z18B-167IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
72Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
8642Zxx_r1
Creation of new datasheet
8642Zxx_r1; 8642Zxx_r1_01
Content
Changed "E" package to "F"
Added Pb-Free information
8642Zxx_r1_01;
8642Zxx_r1_02
Content
Removed F package entirely
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
34/34
2004, GSI Technology