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Электронный компонент: GS864418B-225

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Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
4M x 18, 2M x 36, 1M x 72
72Mb S/DCD Sync Burst SRAMs
250 MHz133MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119-, 165-, & 209-Pin BGA
Commercial Temp
Industrial Temp
Rev: 1.03 11/2004
1/41
2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
2.5 V or 3.3 V +10%/10% core power supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119-, 165-, and 209-bump BGA package
Functional Description
Applications
The GS864418/36/72 is a
75,497,472
-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although of a
type originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main store to
networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode . Holding the FT mode pin low places the RAM in
Flow Through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS864418/36/72 is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM.
DCD SRAMs
pipeline disable commands to the same degree as read commands.
SCD SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs immediately
after the deselect command has been captured in the input registers.
DCD RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
FLXDriveTM
The ZQ pin allows selection between high drive strength (ZQ low) for
multi-drop bus applications and normal drive strength (ZQ floating or
high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS864418/36/72 operates on a 2.5 V or 3.3 V power supply. All
input are 3.3 V and 2.5 V compatible. Separate output power (V
DDQ
)
pins are used to decouple output noise from the internal circuits and
are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
(x18/x36)
t
KQ
(x72)
tCycle
2.5
3.0
4.0
2.7
3.0
4.4
3.0
3.0
5.0
3.5
3.5
6.0
3.8
3.8
6.7
4.0
4.0
7.5
ns
ns
ns
Curr (x18)
Curr (x36)
Curr (x72)
385
450
540
360
415
505
335
385
460
305
345
405
295
325
385
265
295
345
mA
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
6.5
6.5
6.5
6.5
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
Curr (x18)
Curr (x36)
Curr (x72)
265
290
345
265
290
345
265
290
345
255
280
335
240
265
315
225
245
300
mA
mA
mA
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
2/41
2003, GSI Technology
GS864472C Pad Out--209-Bump BGA--Top View (Package C)
1
2
3
4
5
6
7
8
9
10
11
A
DQ
G
DQ
G
A
E2
ADSP
ADSC
ADV
E3
A
DQ
B
DQ
B
A
B
DQ
G
DQ
G
BC
BG
NC
BW
A
BB
BF
DQ
B
DQ
B
B
C
DQ
G
DQ
G
BH
BD
NC
E1
NC
BE
BA
DQ
B
DQ
B
C
D
DQ
G
DQ
G
V
SS
NC
NC
G
GW
NC
V
SS
DQ
B
DQ
B
D
E
DQP
G
DQP
C
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
DQP
F
DQP
B
E
F
DQ
C
DQ
C
V
SS
V
SS
V
SS
ZQ
V
SS
V
SS
V
SS
DQ
F
DQ
F
F
G
DQ
C
DQ
C
V
DDQ
V
DDQ
V
DD
MCH
V
DD
V
DDQ
V
DDQ
DQ
F
DQ
F
G
H
DQ
C
DQ
C
V
SS
V
SS
V
SS
MCL
V
SS
V
SS
V
SS
DQ
F
DQ
F
H
J
DQ
C
DQ
C
V
DDQ
V
DDQ
V
DD
MCL
V
DD
V
DDQ
V
DDQ
DQ
F
DQ
F
J
K
NC
NC
CK
NC
V
SS
MCL
V
SS
NC
NC
NC
NC
K
L
DQ
H
DQ
H
V
DDQ
V
DDQ
V
DD
FT
V
DD
V
DDQ
V
DDQ
DQ
A
DQ
A
L
M
DQ
H
DQ
H
V
SS
V
SS
V
SS
MCL
V
SS
V
SS
V
SS
DQ
A
DQ
A
M
N
DQ
H
DQ
H
V
DDQ
V
DDQ
V
DD
SCD
V
DD
V
DDQ
V
DDQ
DQ
A
DQ
A
N
P
DQ
H
DQ
H
V
SS
V
SS
V
SS
ZZ
V
SS
V
SS
V
SS
DQ
A
DQ
A
P
R
DQP
D
DQP
H
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
DQP
A
DQP
E
R
T
DQ
D
DQ
D
V
SS
NC
NC
LBO
NC
NC
V
SS
DQ
E
DQ
E
T
U
DQ
D
DQ
D
A
A
A
A
A
A
A
DQ
E
DQ
E
U
V
DQ
D
DQ
D
A
A
A
A1
A
A
A
DQ
E
DQ
E
V
W
DQ
D
DQ
D
TMS
TDI
A
A0
A
TDO
TCK
DQ
E
DQ
E
W
11 x 19 Bump BGA--14 x 22 mm
2
Body--1 mm Bump Pitch
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
3/41
2003, GSI Technology
GS864472 209-Bump BGA Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs.
A
I
Address Inputs
DQ
A
DQ
B
DQ
C
DQ
D
DQ
E
DQ
F
DQ
G
DQ
H
I/O
Data Input and Output pins
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low
B
C
,B
D
I
Byte Write Enable for DQ
C
, DQ
D
I/Os; active low
B
E
, B
F
, B
G
,B
H
I
Byte Write Enable for DQ
E
, DQ
F
, DQ
G
, DQ
H
I/Os; active low
NC
--
No Connect
CK
I
Clock Input Signal; active high
GW
I
Global Write Enable--Writes all bytes; active low
E
1
I
Chip Enable; active low
E
3
I
Chip Enable; active low
E
2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
SCD
I
Single Cycle Deselect/Dual Cycle Deselect Mode Control
MCH
I
Must Connect High
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
4/41
2003, GSI Technology
MCL
Must Connect Low
BW
I
Byte Enable; active low
ZQ
I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
V
DD
I
Core power supply
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
GS864472 209-Bump BGA Pin Description (Continued)
Symbol
Type
Description
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
5/41
2003, GSI Technology
165-Bump BGA--x18 Commom I/O--Top View (Package E)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BB
NC
E3
BW
ADSC
ADV
A
A
A
B
NC
A
E2
NC
BA
CK
GW
G
ADSP
A
NC
B
C
NC
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPA
C
D
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
D
E
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
E
F
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
F
G
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
G
H
FT
MCL
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZQ
ZZ
H
J
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
J
K
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
K
L
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
L
M
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
M
N
DQPB
SCD
V
DDQ
V
SS
NC
A
NC
V
SS
V
DDQ
NC
NC
N
P
NC
A
A
A
TDI
A1
TDO
A
A
A
A
P
R
LBO
A
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA--15 mm x 17 mm Body--1.0 mm Bump Pitch
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
6/41
2003, GSI Technology
165-Bump BGA--x36 Common I/O--Top View (Package E)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
A
NC
A
B
NC
A
E2
BD
BA
CK
GW
G
ADSP
A
NC
B
C
DQPC
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPB
C
D
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
D
E
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
E
F
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
F
G
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
G
H
FT
MCL
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZQ
ZZ
H
J
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
J
K
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
K
L
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
L
M
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
M
N
DQPD
SCD
V
DDQ
V
SS
NC
A
NC
V
SS
V
DDQ
NC
DQPA
N
P
NC
A
A
A
TDI
A1
TDO
A
A
A
A
P
R
LBO
A
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA--15 mm x 17 mm Body--1.0 mm Bump Pitch
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
7/41
2003, GSI Technology
GS864418/36 165-Bump BGA Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
DQ
A
DQ
B
DQ
C
DQ
D
I/O
Data Input and Output pins
B
A
, B
B
, B
C
, B
D
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low (x36 Version)
NC
--
No Connect
CK
I
Clock Input Signal; active high
BW
I
Byte Write--Writes all enabled bytes; active low
GW
I
Global Write Enable--Writes all bytes; active low
E
1
I
Chip Enable; active low
E
3
I
Chip Enable; active low
E
2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active l0w
ADSC, ADSP
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
ZQ
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
MCL
--
Must Connect Low
SCD
--
Single Cycle Deselect/Dual Cyle Deselect Mode Control
V
DD
I
Core power supply
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
8/41
2003, GSI Technology
GS864436B Pad Out--119-Bump BGA--Top View (Package B)
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
A
B
NC
A
A
ADSC
A
A
NC
B
C
NC
A
A
V
DD
A
A
NC
C
D
DQ
C
DQP
C
V
SS
ZQ
V
SS
DQP
B
DQ
B
D
E
DQ
C
DQ
C
V
SS
E1
V
SS
DQ
B
DQ
B
E
F
V
DDQ
DQ
C
V
SS
G
V
SS
DQ
B
V
DDQ
F
G
DQ
C
DQ
C
BC
ADV
BB
DQ
B
DQ
B
G
H
DQ
C
DQ
C
V
SS
GW
V
SS
DQ
B
DQ
B
H
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
J
K
DQ
D
DQ
D
V
SS
CK
V
SS
DQ
A
DQ
A
K
L
DQ
D
DQ
D
BD
SCD
BA
DQ
A
DQ
A
L
M
V
DDQ
DQ
D
V
SS
BW
V
SS
DQ
A
V
DDQ
M
N
DQ
D
DQ
D
V
SS
A1
V
SS
DQ
A
DQ
A
N
P
DQ
D
DQP
D
V
SS
A0
V
SS
DQP
A
DQ
A
P
R
NC
A
LBO
V
DD
FT
A
NC
R
T
NC
A
A
A
A
A
ZZ
T
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
U
7 x 17 Bump BGA--14 x 22 mm
2
Body--1.27 mm Bump Pitch
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
9/41
2003, GSI Technology
GS864418B Pad Out--119-Bump BGA--Top View (Package B)
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
A
B
NC
A
A
ADSC
A
A
NC
B
C
NC
A
A
V
DD
A
A
NC
C
D
DQ
B
NC
V
SS
ZQ
V
SS
DQP
A
NC
D
E
NC
DQ
B
V
SS
E1
V
SS
NC
DQ
A
E
F
V
DDQ
NC
V
SS
G
V
SS
DQ
A
V
DDQ
F
G
NC
DQ
B
BB
ADV
NC
NC
DQ
A
G
H
DQ
B
NC
V
SS
GW
V
SS
DQ
A
NC
H
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
J
K
NC
DQ
B
V
SS
CK
V
SS
NC
DQ
A
K
L
DQ
B
NC
NC
SCD
BA
DQ
A
NC
L
M
V
DDQ
DQ
B
V
SS
BW
V
SS
NC
V
DDQ
M
N
DQ
B
NC
V
SS
A1
V
SS
DQ
A
NC
N
P
NC
DQP
B
V
SS
A0
V
SS
NC
DQ
A
P
R
NC
A
LBO
V
DD
FT
A
NC
R
T
A
A
A
A
A
A
ZZ
T
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
U
7 x 17 Bump BGA--14 x 22 mm
2
Body--1.27 mm Bump Pitch
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
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Rev: 1.03 11/2004
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GS864418/36 119-Bump BGA Pin Description
Symbol
Type
Description
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
DQ
A
DQ
B
DQ
C
DQ
D
I/O
Data Input and Output pins
B
A
, B
B
, B
C
, B
D
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
NC
--
No Connect
CK
I
Clock Input Signal; active high
BW
I
Byte Write--Writes all enabled bytes; active low
GW
I
Global Write Enable--Writes all bytes; active low
E
1
I
Chip Enable; active low
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
ZQ
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
SCD
I
Single Cycle Deselect/Dual Cyle Deselect Mode Control
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
V
DD
I
Core power supply
V
SS
I
I/O and Core Ground
V
SS
I
I/O and Core Ground
V
DDQ
I
Output driver power supply
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
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2003, GSI Technology
GS864418/36/72 Block Diagram
A1
A0
A0
A1
D0
D1
Q1
Q0
Counter
Load
D
Q
D
Q
Register
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Reg
i
ster
D
Q
Re
giste
r
A0An
LBO
ADV
CK
ADSC
ADSP
GW
BW
E
1
FT
G
ZZ
Power Down
Control
Memory
Array
36
36
4
A
Q
D
DQx1DQx9
36
36
Note: Only x36 version shown for simplicity.
SCD
36
36
B
A
B
B
B
C
B
D
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
12/41
2003, GSI Technology
Note:
There are pull-up devices onthe ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, I
DD
= I
SB
Single/Dual Cycle Deselect Control
SCD
L
Dual Cycle Deselect
H or NC
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
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2003, GSI Technology
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
A
, B
B
, B
C
, and/or B
D
may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes "
C
" and "
D
" are only available on the x36 version.
Byte Write Truth Table
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
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2003, GSI Technology
Synchronous Truth Table
Operation
Address Used
State
Diagram
Key
5
E
1
ADSP
ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
None
X
H
X
L
X
X
High-Z
Read Cycle, Begin Burst
External
R
L
L
X
X
X
Q
Read Cycle, Begin Burst
External
R
L
H
L
X
F
Q
Write Cycle, Begin Burst
External
W
L
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
H
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
H
H
H
T
D
Write Cycle, Suspend Burst
Current
H
X
H
H
T
D
Notes:
1. X = Don't Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as "Q" in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
15/41
2003, GSI Technology
Simplified State Diagram
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
Simple Synchronous Operation
Simple Burst Synchronou
s Operation
CR
R
CW
CR
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B
A
, B
B
, B
C
, B
D
, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
16/41
2003, GSI Technology
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet
Data Input Set Up Time.
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
17/41
2003, GSI Technology
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Absolute Maximum Ratings
(All voltages reference to V
SS
)
Symbol
Description
Value
Unit
V
DD
Voltage on V
DD
Pins
0.5 to 4.6
V
V
DDQ
Voltage in V
DDQ
Pins
0.5 to 4.6
V
V
I/O
Voltage on I/O Pins
0.5 to V
DDQ
+0.5 (
4.6 V max.)
V
V
IN
Voltage on Other Input Pins
0.5 to V
DD
+0.5 (
4.6 V max.)
V
I
IN
Input Current on Any Pin
+/20
mA
I
OUT
Output Current on Any I/O Pin
+/20
mA
P
D
Package Power Dissipation
1.5
W
T
STG
Storage Temperature
55 to 125
o
C
T
BIAS
Temperature Under Bias
55 to 125
o
C
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
3.3 V Supply Voltage
V
DD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
V
DD2
2.3
2.5
2.7
V
3.3 V V
DDQ
I/O Supply Voltage
V
DDQ3
3.0
3.3
3.6
V
2.5 V V
DDQ
I/O Supply Voltage
V
DDQ2
2.3
2.5
2.7
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
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2003, GSI Technology
V
DDQ3
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
2.0
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.8
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
2.0
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.8
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
V
DDQ2
Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
0.6*V
DD
--
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
0.3
--
0.3*V
DD
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
0.6*V
DD
--
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
0.3
--
0.3*V
DD
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
T
A
0
25
70
C
2
Ambient Temperature (Industrial Range Versions)
T
A
40
25
85
C
2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
19/41
2003, GSI Technology
Note:
These parameters are sample tested.
Capacitance
(T
A
= 25
o
C, f = 1 MH
Z
, V
DD
= 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
C
IN
V
IN
= 0 V
8
10
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0 V
12
14
pF
AC Test Conditions
Parameter
Conditions
Input high level
V
DD
0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DD
/2
Output reference level
V
DDQ
/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
20% tKC
V
SS
2.0 V
50%
V
SS
V
IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
V
DD
+ 2.0 V
50%
V
DD
V
IL
DQ
V
DDQ/2
50
30pF
*
Output Load 1
* Distributed Test Jig Capacitance
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
20/41
2003, GSI Technology
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
IL
V
IN
= 0 to V
DD
1 uA
1 uA
ZZ Input Current
I
IN1
V
DD
V
IN
V
IH
0 V
V
IN
V
IH
1 uA
1 uA
1 uA
100 uA
FT, SCD, and ZQ Input Current
I
IN2
V
DD
V
IN
V
IL
0 V
V
IN
V
IL
100 uA
1 uA
1 uA
1 uA
Output Leakage Current
I
OL
Output Disable, V
OUT
= 0 to V
DD
1 uA
1 uA
Output High Voltage
V
OH2
I
OH
= 8 mA, V
DDQ
= 2.375 V
1.7 V
--
Output High Voltage
V
OH3
I
OH
= 8 mA, V
DDQ
= 3.135 V
2.4 V
--
Output Low Voltage
V
OL
I
OL
= 8 mA
--
0.4 V
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
21/41
2003, GSI Technology
Notes:
1.
I
DD
a
nd I
DDQ
apply to an
y combination of V
DD3
, V
DD2
, V
DD
Q
3
, and V
DDQ2
operation.
2.
All p
a
rameters listed are worst case scenario.
Operating Currents
Par
a
meter
T
est
Co
nd
itio
ns
Mo
de
Sym
b
o
l
-250
-225
-200
-166
-150
-133
Un
it
0
to
70C
40
to
85C
0
to
70C

40
to
85C
0
to
70C
40
to
85C
0
to
70
C

40
to
85C
0
to
70C
40
to
85C
0
to
70C

40
to
85C
Operating
Current
Devi
ce Selec
t
ed;
All other input
s

V
IH

o
r
V
IL
Output

o
pen
(x72)
Pipeline
I
DD
I
DDQ
48
0
60
515
60
445
60
480
60
410
50
445
50
365
40
400
40
345
40
38
0
40
315
30
350
30
mA
Flow
Through
I
DD
I
DDQ
31
5
30
340
30
315
30
340
30
315
30
340
30
305
30
330
30
285
30
31
0
30
280
20
305
20
mA
(x36)
Pipeline
I
DD
I
DDQ
40
0
50
435
50
370
45
405
45
345
40
380
40
310
35
345
35
295
30
33
0
30
270
25
305
25
mA
Flow
Through
I
DD
I
DDQ
27
0
20
295
20
270
20
295
20
270
20
295
20
260
20
285
20
245
20
27
0
20
230
15
255
15
mA
(x18)
Pipeline
I
DD
I
DDQ
36
0
25
395
25
335
25
370
25
315
20
350
20
285
20
320
20
275
20
31
0
20
250
15
285
15
mA
Flow
Through
I
DD
I
DDQ
25
0
15
275
15
250
15
275
15
250
15
275
15
240
15
260
15
225
15
25
0
15
210
15
235
15
mA
Standby
Current
ZZ

V
DD
0.2 V
--
Pipeline
I
SB
1
2
0
160
120
160
120
160
120
160
120
1
6
0
120
160
mA
Flow
Through
I
SB
1
2
0
160
120
160
120
160
120
160
120
1
6
0
120
160
mA
Des
e
lect
Current
Dev
i
ce D
e
selec
t
ed;
All other input
s
V
IH

or


V
IL
--
Pipeline
I
DD
2
0
0
230
190
220
180
210
170
200
170
2
0
0
160
190
mA
Flow
Through
I
DD
1
7
0
200
170
200
160
190
160
190
150
1
8
0
140
170
mA
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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2003, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter
Symbol
-250
-225
-200
-166
-150
-133
Unit
Min
Max
Min
Max
Min
Max
Min
Max Min Max Min Max
Pipeline
Clock Cycle Time
tKC
4.0
--
4.4
--
5.0
--
6.0
--
6.7
--
7.5
--
ns
Clock to Output Valid
(x18/x36)
tKQ
--
2.5
--
2.7
--
3.0
--
3.5
--
3.8
--
4.0
ns
Clock to Output Valid
(x72)
tKQ
--
3.0
--
3.0
--
3.0
--
3.5
--
3.8
--
4.0
ns
Clock to Output Invalid
tKQX
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Clock to Output in Low-Z
tLZ
1
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Setup time
tS
1.3
--
1.3
--
1.4
--
1.5
--
1.5
--
1.5
--
ns
Hold Time
tH
0.2
--
0.3
--
0.4
--
0.5
--
0.5
--
0.5
--
ns
Flow
Through
Clock Cycle Time
tKC
6.5
--
6.5
--
6.5
--
7.0
--
7.5
--
8.5
--
ns
Clock to Output Valid
tKQ
--
6.5
--
6.5
--
6.5
--
7.0
--
7.5
--
8.5
ns
Clock to Output Invalid
tKQX
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
ns
Clock to Output in Low-Z
tLZ
1
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
ns
Setup time
tS
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
Hold time
tH
0.5
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
--
ns
Clock HIGH Time
tKH
1.3
--
1.3
--
1.3
--
1.3
--
1.5
--
1.7
--
ns
Clock LOW Time
tKL
1.5
--
1.5
--
1.5
--
1.5
--
1.7
--
2
--
ns
Clock to Output in
High-Z
(x18/x36)
tHZ
1
1.5 2.5
1.5 2.7
1.5 3.0
1.5
3.0
1.5 3.0
1.5 3.0
ns
Clock to Output in
High-Z (x72)
tHZ
1
1.5 3.0
1.5 3.0
1.5 3.0
1.5
3.0
1.5 3.0
1.5 3.0
ns
G to Output Valid
(x18/x36)
tOE
--
2.5
--
2.7
--
3.2
--
3.5
--
3.8
--
4.0
ns
G to Output Valid
(x72)
tOE
--
3.0
--
3.0
--
3.2
--
3.5
--
3.8
--
4.0
ns
G to output in Low-Z
tOLZ
1
0
--
0
--
0
--
0
--
0
--
0
--
ns
G to output in High-Z (x18/
x36)
tOHZ
1
--
2.5
--
2.7
--
3.0
--
3.0
--
3.0
--
3.0
ns
G to output in High-Z (x72)
tOHZ
1
--
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
3.0
ns
ZZ setup time
tZZS
2
5
--
5
--
5
--
5
--
5
--
5
--
ns
ZZ hold time
tZZH
2
1
--
1
--
1
--
1
--
1
--
1
--
ns
ZZ recovery
tZZR
20
--
20
--
20
--
20
--
20
--
20
--
ns
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Pipeline Mode Timing (SCD)
Begin
Read A
Cont
Cont
Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Cont
Deselect
tHZ
tKQX
tKQ
tLZ
tH
tS
tOHZ
tOE
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tS
tH
tS
tH
tS
tH
tS
Burst Read
Burst Read
Single Write
tKC
tKC
tKL
tKL
tKH
Single Write
Single Read
tKH
Single Read
Q(A)
D(B)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
A
B
C
Deselected with E1
E1 masks ADSP
E2 and E3 only sampled with ADSP and ADSC
ADSC initiated read
CK
ADSP
ADSC
ADV
A0An
GW
BW
BaBd
E1
E2
E3
G
DQaDQd
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Flow Through Mode Timing (SCD)
Begin
Read A
Cont
Cont
Write B
Read C
Read C+1 Read C+2 Read C+3 Read C
Cont
Deselect
tHZ
tKQX
tKQ
tLZ
tH
tS
tOHZ
tOE
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKC
tKL
tKL
tKH
tKH
A
B
C
Q(A)
D(B)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
E2 and E3 only sampled with ADSC
ADSC initiated read
Deselected with E1
Fixed High
CK
ADSP
ADSC
ADV
A0An
GW
BW
BaBd
E1
E2
E3
G
DQaDQd
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Pipeline Mode Timing (DCD)
Begin
Read A
Cont
Deselect Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Cont
Deselect Deselect
tHZ
tKQX
tKQ
tLZ
tH
tS
tOHZ
tOE
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tS
tH
tS
tH
tS
tH
tS
tKC
tKC
tKL
tKL
tKH
tKH
Q(A)
D(B)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
A
B
C
Hi-Z
Deselected with E1
E2 and E3 only sampled with ADSC
ADSC initiated read
CK
ADSP
ADSC
ADV
AoAn
GW
BW
BaBd
E1
E2
E3
G
DQaDQd
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Flow Through Mode Timing (DCD)
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Begin
Read A
Cont
Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Read C
Deselect
tHZ
tKQX
tLZ
tH
tS
tOHZ
tOE
tKQ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKC
tKL
tKL
tKH
tKH
A
B
C
Q(A)
D(B)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
E2 and E3 only sampled with ADSP and ADSC
E1 masks ADSP
ADSC initiated read
Deselected with E1
E1 masks ADSP
Fixed High
CK
ADSP
ADSC
ADV
AoAn
GW
BW
BaBd
E1
E2
E3
G
DQaDQd
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Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of "dummy read cycles" (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
DD
. The JTAG output
drivers are powered by V
DDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
tZZR
tZZH
tZZS
Hold
Setup
tKL
tKL
tKH
tKH
tKC
tKC
CK
ADSP
ADSC
ZZ
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JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI
Test Data In
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO
Test Data Out
Out
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
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JTAG TAP Block Diagram (2-die module)
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents (per die)
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x72
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0 0 1 1 0 1 1 0 0 1
1
x36
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x32
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0 0 1 1 0 1 1 0 0 1
1
x18
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0 0 1 1 0 1 1 0 0 1
1
x16
X X X X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0 0 1 1 0 1 1 0 0 1
1
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
108
1
0
Control Signals
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
Test Access Port (TAP) Controller
108
1
0
Control Signals
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Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
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SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
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JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
V
DD
0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DDQ
/2
Output reference level
V
DDQ
/2
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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JTAG Port Timing Diagram
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
V
IHJ3
2.0
V
DD3
+0.3
V
1
3.3 V Test Port Input Low Voltage
V
ILJ3
0.3
0.8
V
1
2.5 V Test Port Input High Voltage
V
IHJ2
0.6 * V
DD2
V
DD2
+0.3
V
1
2.5 V Test Port Input Low Voltage
V
ILJ2
0.3
0.3 * V
DD2
V
1
TMS, TCK and TDI Input Leakage Current
I
INHJ
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
I
INLJ
1
100
uA
3
TDO Output Leakage Current
I
OLJ
1
1
uA
4
Test Port Output High Voltage
V
OHJ
1.7
--
V
5, 6
Test Port Output Low Voltage
V
OLJ
--
0.4
V
5, 7
Test Port Output CMOS High
V
OHJC
V
DDQ
100 mV
--
V
5, 8
Test Port Output CMOS Low
V
OLJC
--
100 mV
V
5, 9
Notes:
1. Input Under/overshoot voltage must be 2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. V
ILJ
V
IN
V
DDn
3. 0 V
V
IN
V
ILJn
4. Output Disable, V
OUT
= 0 to V
DDn
5. The TDO output driver is served by the V
DDQ
supply.
6. I
OHJ
= 4 mA
7. I
OLJ
= + 4 mA
8. I
OHJC
= 100 uA
9. I
OHJC
= +100 uA
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKL
tTKL
tTKH
tTKH
tTKC
tTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
34/41
2003, GSI Technology
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
JTAG Port AC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
50
--
ns
TCK Low to TDO Valid
tTKQ
--
20
ns
TCK High Pulse Width
tTKH
20
--
ns
TCK Low Pulse Width
tTKL
20
--
ns
TDI & TMS Set Up Time
tTS
10
--
ns
TDI & TMS Hold Time
tTH
10
--
ns
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
35/41
2003, GSI Technology
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
Symbol
Min
Typ
Max
Units
Symbol
Min
Typ
Max
Units
A
--
--
1.70
mm
D1
--
18.0 (BSC)
--
mm
A1
0.40
0.50
0.60
mm
E
13.9
14.0
14.1
mm
b
0.50
0.60
0.70
mm
E1
--
10.0 (BSC)
--
mm
c
0.31
0.36
0.38
mm
e
--
1.00 (BSC)
--
mm
D
21.9
22.0
22.1
mm
aaa
--
0.15
--
mm
Rev 1.0
A
A1
C
b
e
e
E
E1
D1
D
aaa
Bottom View
Side View
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
36/41
2003, GSI Technology
Package Dimensions--119-Bump FPBGA (Package B, Variation 2
)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1 2 3 4 5 6 7
7 6 5 4 3 2 1
A1
TOP VIEW
A1
BOTTOM VIEW
1.27
7.62
1.
27
20
.3
2
140.10
2
2

0.
10
B
A
0.20(4x)
0.10
0.30
C
C A B
S
S
0.60~0.90 (119x)
C
SEATING PLANE
0.
15
C
0.
5
0
~0.
7
0
1.
86
.0
.
1
3
0.
70
0
.0
5
0.
15
C
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.
56
0
.0
5
S
S
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
37/41
2003, GSI Technology
Package Dimensions--165-Bump FPBGA (Package E; Variation 1)
A
B
C
D
E
F
G
H
I
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11
11 10 9 8 7 6 5 4 3 2 1
A1
TOP VIEW
A1
BOTTOM VIEW
1.0
1.0
10.0
1.
0
1.
0
14
.0
150.05
170.05
A
B
0.20(4x)
0.10
0.25
C
C A B
M
M
0.44~0.64(165x)
C
SEATING PLANE
0.
20
C
0.
36
~0
.4
6
1.
40
M
A
X.
0.
53
R
E
F
0.
35
C
0.
36
REF
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
38/41
2003, GSI Technology

Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
4M x 18
GS864418B-250
Pipeline/Flow Through
119 BGA (var. 2)
250/6.5
C
4M x 18
GS864418B-225
Pipeline/Flow Through
119 BGA (var. 2)
225/6.5
C
4M x 18
GS864418B-200
Pipeline/Flow Through
119 BGA (var. 2)
200/6.5
C
4M x 18
GS864418B-166
Pipeline/Flow Through
119 BGA (var. 2)
166/8
C
4M x 18
GS864418B-150
Pipeline/Flow Through
119 BGA (var. 2)
150/8.5
C
4M x 18
GS864418B-133
Pipeline/Flow Through
119 BGA (var. 2)
133/8.5
C
4M x 18
GS864418E-250
Pipeline/Flow Through
165 BGA (var. 1)
250/6.5
C
4M x 18
GS864418E-225
Pipeline/Flow Through
165 BGA (var. 1)
225/6.5
C
4M x 18
GS864418E-200
Pipeline/Flow Through
165 BGA (var. 1)
200/6.5
C
4M x 18
GS864418E-166
Pipeline/Flow Through
165 BGA (var. 1)
166/8
C
4M x 18
GS864418E-150
Pipeline/Flow Through
165 BGA (var. 1)
150/8.5
C
4M x 18
GS864418E-133
Pipeline/Flow Through
165 BGA (var. 1)
133/8.5
C
2M x 36
GS864436B-250
Pipeline/Flow Through
119 BGA (var. 2)
250/6.5
C
2M x 36
GS864436B-225
Pipeline/Flow Through
119 BGA (var. 2)
225/6.5
C
2M x 36
GS864436B-200
Pipeline/Flow Through
119 BGA (var. 2)
200/6.5
C
2M x 36
GS864436B-166
Pipeline/Flow Through
119 BGA (var. 2)
166/8
C
2M x 36
GS864436B-150
Pipeline/Flow Through
119 BGA (var. 2)
150/8.5
C
2M x 36
GS864436B-133
Pipeline/Flow Through
119 BGA (var. 2)
133/8.5
C
2M x 36
GS864436E-250
Pipeline/Flow Through
165 BGA (var. 1)
250/6.5
C
2M x 36
GS864436E-225
Pipeline/Flow Through
165 BGA (var. 1)
225/6.5
C
2M x 36
GS864436E-200
Pipeline/Flow Through
165 BGA (var. 1)
200/6.5
C
2M x 36
GS864436E-166
Pipeline/Flow Through
165 BGA (var. 1)
166/8
C
2M x 36
GS864436E-150
Pipeline/Flow Through
165 BGA (var. 1)
150/8.5
C
2M x 36
GS864436E-133
Pipeline/Flow Through
165 BGA (var. 1)
133/8.5
C
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS864418B-150IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
39/41
2003, GSI Technology
1M x 72
GS864472C-250
Pipeline/Flow Through
209 BGA
250/6.5
C
1M x 72
GS864472C-225
Pipeline/Flow Through
209 BGA
225/6.5
C
1M x 72
GS864472C-200
Pipeline/Flow Through
209 BGA
200/6.5
C
1M x 72
GS864472C-166
Pipeline/Flow Through
209 BGA
166/8
C
1M x 72
GS864472C-150
Pipeline/Flow Through
209 BGA
150/8.5
C
1M x 72
GS864472C-133
Pipeline/Flow Through
209 BGA
133/8.5
C
4M x 18
GS864418B-250I
Pipeline/Flow Through
119 BGA (var. 2)
250/6.5
I
4M x 18
GS864418B-225I
Pipeline/Flow Through
119 BGA (var. 2)
225/6.5
I
4M x 18
GS864418B-200I
Pipeline/Flow Through
119 BGA (var. 2)
200/6.5
I
4M x 18
GS864418B-166I
Pipeline/Flow Through
119 BGA (var. 2)
166/8
I
4M x 18
GS864418B-150I
Pipeline/Flow Through
119 BGA (var. 2)
150/8.5
I
4M x 18
GS864418B-133I
Pipeline/Flow Through
119 BGA (var. 2)
133/8.5
I
4M x 18
GS864418E-250I
Pipeline/Flow Through
165 BGA (var. 1)
250/6.5
I
4M x 18
GS864418E-225I
Pipeline/Flow Through
165 BGA (var. 1)
225/6.5
I
4M x 18
GS864418E-200I
Pipeline/Flow Through
165 BGA (var. 1)
200/6.5
I
4M x 18
GS864418E-166I
Pipeline/Flow Through
165 BGA (var. 1)
166/8
I
4M x 18
GS864418E-150I
Pipeline/Flow Through
165 BGA (var. 1)
150/8.5
I
4M x 18
GS864418E-133I
Pipeline/Flow Through
165 BGA (var. 1)
133/8.5
I
2M x 36
GS864436B-250I
Pipeline/Flow Through
119 BGA (var. 2)
250/6.5
I
2M x 36
GS864436B-225I
Pipeline/Flow Through
119 BGA (var. 2)
225/6.5
I
2M x 36
GS864436B-200I
Pipeline/Flow Through
119 BGA (var. 2)
200/6.5
I
2M x 36
GS864436B-166I
Pipeline/Flow Through
119 BGA (var. 2)
166/8
I
2M x 36
GS864436B-150I
Pipeline/Flow Through
119 BGA (var. 2)
150/8.5
I
2M x 36
GS864436B-133I
Pipeline/Flow Through
119 BGA (var. 2)
133/8.5
I
2M x 36
GS864436E-250I
Pipeline/Flow Through
165 BGA (var. 1)
250/6.5
I
2M x 36
GS864436E-225I
Pipeline/Flow Through
165 BGA (var. 1)
225/6.5
I
Ordering Information for GSI Synchronous Burst RAMs (Continued)
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS864418B-150IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
40/41
2003, GSI Technology
2M x 36
GS864436E-200I
Pipeline/Flow Through
165 BGA (var. 1)
200/6.5
I
2M x 36
GS864436E-166I
Pipeline/Flow Through
165 BGA (var. 1)
166/8
I
2M x 36
GS864436E-150I
Pipeline/Flow Through
165 BGA (var. 1)
150/8.5
I
2M x 36
GS864436E-133I
Pipeline/Flow Through
165 BGA (var. 1)
133/8.5
I
1M x 72
GS864472C-250I
Pipeline/Flow Through
209 BGA
250/6.5
I
1M x 72
GS864472C-225I
Pipeline/Flow Through
209 BGA
225/6.5
I
1M x 72
GS864472C-200I
Pipeline/Flow Through
209 BGA
200/6.5
I
1M x 72
GS864472C-166I
Pipeline/Flow Through
209 BGA
166/8
I
1M x 72
GS864472C-150I
Pipeline/Flow Through
209 BGA
150/8.5
I
1M x 72
GS864472C-133I
Pipeline/Flow Through
209 BGA
133/8.5
I
Ordering Information for GSI Synchronous Burst RAMs (Continued)
Org
Part Number
1
Type
Package
Speed
2
(MHz/ns)
T
A
3
Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS864418B-150IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T
A
= C = Commercial Temperature Range. T
A
= I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Product Preview
GS864418(B/E)/GS864436(B/E)/GS864472(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
41/41
2003, GSI Technology
72Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
8644xx_r1
Creation of new datasheet
8644xx_r1; 8644xx_r1_01
Content
Updated Operating Currents table
Updated FT AC Characteristics for tKQ
8644xx_r1_01;
8644xx_r1_02
Content
Updated FT tKQ and PL tS/tH and FT current numbers for 250
and 225 MHz (match 200 MHz)
Updated basic format
Added thermal characteristics to mechanical drawings
Updated JTAG section for module
8644xx_r1_02;
8644xx_r1_03
Format/Content
Updated format
Added variation information to package mechanicals