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Preliminary

GS88237AB-250/225/200/166/150/133

256K x 36

9Mb SCD/DCD Sync Burst SRAMs

250 MHz133MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

119-Bump BGA
Commercial Temp
Industrial Temp

Features

· Single/Dual Cycle Deselect selectable
· IEEE 1149.1 JTAG-compatible Boundary Scan
· ZQ mode pin for user-selectable high/low output drive
· 2.5 V or 3.3 V +10%/10% core power supply
· 2.5 V or 3.3 V I/O supply
· LBO pin for Linear or Interleaved Burst mode
· Internal input resistors on mode pins allow floating mode pins
· Byte Write (BW) and/or Global Write (GW) operation
· Internal self-timed write cycle
· Automatic power-down for portable applications
· JEDEC-standard 119-bump BGA package

Functional Description

Applications

The GS88237AB is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.

SCD and DCD Pipelined Reads

The GS88237AB is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD
mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.

FLXDriveTM

The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.

Core and Interface Voltages

The GS88237AB operates on a 2.5 V or 3.3 V power supply. All
input are 3.3 V and 2.5 V compatible. Separate output power
(V

DDQ

) pins are used to decouple output noise from the internal

circuits and are 3.3 V and 2.5 V compatible.

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

tCycle

2.0
4.0

2.2
4.4

2.5
5.0

2.9
6.0

3.3
6.7

3.5
7.5

ns
ns

3.3 V

Current

330 300 270 230 215 190 mA

2.5 V

Current

320 295 265 225 210 185 mA

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Preliminary

GS88237AB-250/225/200/166/150/133

GS88237A Pad Out

119 Bump BGA

Top View

DDQ

ADSP

DDQ

ADSC

DQP

DDQ

ADV

DDQ

SCD

DDQ

DQP

LBO

DDQ

DNU

DDQ

TMS

TDI

TCK

TDO

DDQ

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Preliminary

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GS88237A BGA Pin Description

Symbol

Type

Description

, A

Address field LSBs and Address Counter Preset Inputs

Address Inputs

I/O

Data Input and Output pins

, B

Byte Write Enable for DQ

, DQ

I/Os; active low (x36 Version)

No Connect

Clock Input Signal; active high

Byte Write--Writes all enabled bytes; active low

Global Write Enable--Writes all bytes; active low

Chip Enable; active low

Output Enable; active low

ADV

Burst address counter advance enable; active low

ADSP, ADSC

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

LBO

Linear Burst Order mode; active low

SCD

Single Cycle Deselect/Dual Cycle Deselect Mode Control

Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

TMS

Scan Test Mode Select

TDI

Scan Test Data In

TDO

Scan Test Data Out

TCK

Scan Test Clock

Core power supply

I/O and Core Ground

DDQ

Output driver power supply

DDQ

/DNU

DDQ

or V

(must be tied high)

Do Not Use (must be left floating)

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Preliminary

GS88237AB-250/225/200/166/150/133

GS88237A (PE = 1) x32 Mode Block Diagram

Counter

Load

i
s
t
e
r

Reg

i
s
t
er

A0An

LBO

ADV
CK

ADSC
ADSP

BW
B

Power Down

Control

Memory

Array

DQx1DQx9

Parity

Encode

Compare

Note: Only x36 version shown for simplicity.

SCD

Parity

Encode

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Preliminary

GS88237AB-250/225/200/166/150/133

Note:
Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name

Pin

Name

State

Function

Burst Order Control

LBO

Linear Burst

Interleaved Burst

Power Down Control

L or NC

Active

Standby, I

= I

Single/Dual Cycle Deselect Control

SCD

Dual Cycle Deselect

H or NC

Single Cycle Deselect

FLXDrive Output Impedance Control

High Drive (Low Impedance)

H or NC

Low Drive (High Impedance)

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

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Preliminary

GS88237AB-250/225/200/166/150/133

Byte Write Truth Table

Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B

, B

, and/or B

may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes "

" and "

" are only available on the x36 version.

Function

Notes

Read

Write byte a

2, 3

Write byte b

2, 3

Write byte c

2, 3, 4

Write byte d

2, 3, 4

Write all bytes

2, 3, 4

Write all bytes

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Preliminary

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Synchronous Truth Table

Operation

Address Used

State

Diagram

Key

ADSP

ADSC

ADV

Deselect Cycle, Power Down

None

High-Z

Read Cycle, Begin Burst

External

Read Cycle, Begin Burst

External

Write Cycle, Begin Burst

External

Read Cycle, Continue Burst

Next

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Next

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Current

Read Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst

Current

Write Cycle, Suspend Burst

Current

Notes:
1. X = Don't Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as "Q" in the Truth Table above).

4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

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Preliminary

GS88237AB-250/225/200/166/150/133

First Write

First Read

Burst Write

Burst Read

Deselect

Simple Synchronous Operation

Simple Burst Synchronou

s Operation

Simplified State Diagram

Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B

, B

, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

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Preliminary

GS88237AB-250/225/200/166/150/133

First Write

First Read

Burst Write

Burst Read

Deselect

Simplified State Diagram with G

Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet

Data Input Set Up Time.

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Preliminary

GS88237AB-250/225/200/166/150/133

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.

Absolute Maximum Ratings

(All voltages reference to V

)

Symbol

Description

Value

Unit

Voltage on V

Pins

0.5 to 4.6

DDQ

Voltage in V

DDQ

Pins

0.5 to 4.6

Voltage on Clock Input Pin

0.5 to 6

I/O

Voltage on I/O Pins

0.5 to V

DDQ

+0.5 (

4.6 V max.)

Voltage on Other Input Pins

0.5 to V

+0.5 (

4.6 V max.)

Input Current on Any Pin

+/20

OUT

Output Current on Any I/O Pin

+/20

Package Power Dissipation

1.5

STG

Storage Temperature

55 to 125

BIAS

Temperature Under Bias

55 to 125

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88237AB-250/225/200/166/150/133

Power Supply Voltage Ranges

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

3.3 V Supply Voltage

DD3

3.0

3.3

3.6

2.5 V Supply Voltage

DD2

2.3

2.5

2.7

3.3 V V

DDQ

I/O Supply Voltage

DDQ3

3.0

3.3

3.6

2.5 V V

DDQ

I/O Supply Voltage

DDQ2

2.3

2.5

2.7

Notes:
1.

The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDQ3

Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Input High Voltage

2.0

+ 0.3

Input Low Voltage

0.3

0.8

DDQ

I/O Input High Voltage

IHQ

2.0

DDQ

+ 0.3

1,3

DDQ

I/O Input Low Voltage

ILQ

0.3

0.8

1,3

Notes:
1.

Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

DDQ2

Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Input High Voltage

0.6*V

+ 0.3

Input Low Voltage

0.3

0.3*V

DDQ

I/O Input High Voltage

IHQ

0.6*V

DDQ

+ 0.3

1,3

DDQ

I/O Input Low Voltage

ILQ

0.3

0.3*V

1,3

Notes:
1.

Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88237AB-250/225/200/166/150/133

Note: These parameters are sample tested.

Recommended Operating Temperatures

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Note:
1.

Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Capacitance

= 25

C, f = 1 MH

, V

= 2.5 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Input Capacitance

= 0 V

Input/Output Capacitance

I/O

OUT

= 0 V

20% tKC

2.0 V

50%

Undershoot Measurement and Timing

Overshoot Measurement and Timing

20% tKC

+ 2.0 V

50%

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88237AB-250/225/200/166/150/133

AC Test Conditions

Parameter

Conditions

Input high level

0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

Output reference level

DDQ

Output load

Fig. 1

Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

= 0 to V

1 uA

ZZ and PE Input Current

IN1

0 V

1 uA
1 uA

1 uA

100 uA

SCD and ZQ Input Current

IN2

0 V

100 uA

1 uA

1 uA
1 uA

Output Leakage Current

Output Disable, V

OUT

= 0 to V

1 uA

Output High Voltage

OH2

= 8 mA, V

DDQ

= 2.375 V

1.7 V

Output High Voltage

OH3

= 8 mA, V

DDQ

= 3.135 V

2.4 V

Output Low Voltage

= 8 mA

0.4 V

DDQ/2

30pF

Output Load 1

* Distributed Test Jig Capacitance

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88237AB-250/225/200/166/150/133

Operatin

g Curren

Notes:

and I

DDQ

apply to any combination of V

DD3

, V

DD2

, V

DDQ3

, and

operation.

All parameters listed are worst case scenario.

Parameter

T
est Conditions

Mode

Symbol

-250

-225

-200

-166

-150

-133

70°C

85°C

70°C

85°C

°
C

85°C

70°C

85°C

70°C

85°C

70°C

85°C

Operating

Current

3.3 V

e
vic

e
S

e
lected;

All other inputs

o
r

Out

p
ut

ope

(x36)

peline

DDQ

290

300

265

275

240

250

205

215

190

200

170

180

Operating

Current

2.5 V

e
vic

e
S

e
lected;

All other inputs

o
r

Out

p
ut

ope

(x36)

peline

DDQ

290

300

265

275

240

250

205

215

190

200

170

180

Standby

Current

peline

Des

e
l
e
ct

Current

e
vic

e
Desel

e
cted;

All other inputs

peline

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88237AB-250/225/200/166/150/133

AC Electrical Characteristics

Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Parameter

Symbol

-250

-225

-200

-166

-150

-133

Unit

Min

Max

Min

Max

Min

Max

Min

Max Min Max Min Max

Pipeline

Clock Cycle Time

tKC

4.0

4.4

5.0

6.0

6.7

7.5

Clock to Output Valid

tKQ

2.0

2.2

2.5

2.9

3.3

3.5

Clock to Output Invalid

tKQX

1.0

Clock to Output in Low-Z

tLZ

1.0

Setup time

1.2

1.3

1.4

1.5

Hold time

0.2

0.3

0.4

0.5

G to Output Valid

tOE

1.8

2.0

2.5

2.9

3.3

3.5

G to output in High-Z

tOHZ

1.8

2.0

2.5

Clock HIGH Time

tKH

1.3

1.5

1.7

Clock LOW Time

tKL

1.5

1.7

Clock to Output in

High-Z

tHZ

1.5 2.3

1.5 2.5

1.5 3.0

1.5

3.0

1.5 3.0

G to output in Low-Z

tOLZ

ZZ setup time

tZZS

ZZ hold time

tZZH

ZZ recovery

tZZR

100

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88237AB-250/225/200/166/150/133

Pipeline Mode Timing (+1)

Begin

e
a
d A

ont

Desele

r
it

e B

e
a
d C

d C+

e
a
d C+2

d C+

ont

Desele

t
KQX

tKC
tKC

tKL
tKL

tKH
tKH

Q(A)

D(B)

Q(C)

Q(C+2

)

Q(C+3

)

l
ect

wit

h

E1

E2 an

d E

3

o
n
l
y
sa

p
le

d

with

ADSC

ADSC i

n
it

ted

e
a
d

A0An

aDQd

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88237AB-250/225/200/166/150/133

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of "dummy read cycles" (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V

. The JTAG output

drivers are powered by V

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V

or V

. TDO should be left unconnected.

ADSP

ADSC

tKH tKL

tKC

tZZR

tZZH

tZZS

~ ~

Snooze

Sleep Mode Timing Diagram

~ ~
~ ~

~ ~

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Preliminary

GS88237AB-250/225/200/166/150/133

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and
0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising
edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI
and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM's JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG Pin Descriptions

Pin

Pin Name

I/O

Description

TCK

Test Clock

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.

TMS

Test Mode Select

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.

TDI

Test Data In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.

TDO

Test Data Out

Out

Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.

Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Rev: 1.01a 2/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

ID Register Contents

Die

Revision

Code

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

x72

X X X X

0 0 1 1 0 1 1 0 0 1

x36

X X X X

0 0 1 1 0 1 1 0 0 1

x32

X X X X

0 0 1 1 0 1 1 0 0 1

x18

X X X X

0 0 1 1 0 1 1 0 0 1

x16

X X X X

0 0 1 1 0 1 1 0 0 1

Instruction Register

ID Code Register

Boundary Scan Register

· · ·

31 30 29

· · ·

Bypass Register

TDI

TDO

TMS

TCK

Test Access Port (TAP) Controller

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88237AB-250/225/200/166/150/133

paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction

Code

Description

Notes

EXTEST

000

Places the Boundary Scan Register between TDI and TDO.

IDCODE

001

Preloads ID Register and places it between TDI and TDO.

1, 2

SAMPLE-Z

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.

RFU

011

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

SAMPLE/

PRELOAD

100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.

GSI

101

GSI private instruction.

RFU

110

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

BYPASS

111

Places Bypass Register between TDI and TDO.

Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

3.3 V Test Port Input High Voltage

IHJ3

2.0

DD3

+0.3

3.3 V Test Port Input Low Voltage

ILJ3

0.3

0.8

2.5 V Test Port Input High Voltage

IHJ2

0.6 * V

DD2

+0.3

2.5 V Test Port Input Low Voltage

ILJ2

0.3

0.3 * V

DD2

TMS, TCK and TDI Input Leakage Current

INHJ

300

TMS, TCK and TDI Input Leakage Current

INLJ

100

TDO Output Leakage Current

OLJ

Test Port Output High Voltage

OHJ

1.7

5, 6

Test Port Output Low Voltage

OLJ

0.4

5, 7

Test Port Output CMOS High

OHJC

DDQ

100 mV

5, 8

Test Port Output CMOS Low

OLJC

100 mV

5, 9

Notes:
1. Input Under/overshoot voltage must be 2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. V

ILJ

DDn

3. 0 V

ILJn

4. Output Disable, V

OUT

= 0 to V

DDn

5. The TDO output driver is served by the V

DDQ

supply.

6. I

OHJ

= 4 mA

7. I

OLJ

= + 4 mA

8. I

OHJC

= 100 uA

9. I

OHJC

= +100 uA

Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.

JTAG Port AC Test Conditions

Parameter

Conditions

Input high level

0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

DDQ

Output reference level

DDQ

30pF

JTAG Port AC Test Load

* Distributed Test Jig Capacitance

Rev: 1.01a 2/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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JTAG Port Timing Diagram

JTAG Port AC Electrical Characteristics

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.

Parameter

Symbol

Min

Max

Unit

TCK Cycle Time

tTKC

TCK Low to TDO Valid

tTKQ

TCK High Pulse Width

tTKH

TCK Low Pulse Width

tTKL

TDI & TMS Set Up Time

tTS

TDI & TMS Hold Time

tTH

tTKQ

tTS

tTH

tTKH

tTKL

TCK

TMS

TDI

TDO

tTKC

Rev: 1.01a 2/2003

25/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88237AB-250/225/200/166/150/133

Package Dimensions--119-Pin PBGA

Pin 1
Corner

Package Dimensions--119-Pin PBGA

Unit: mm

Symbol

Description

Min. Nom. Max

Width

13.9

14.0

14.1

Length

21.9

22.0

22.1

Package Height (including ball)

1.73

1.86

1.99

Ball Size

0.60

0.75

0.90

Ball Height

0.50

0.60

0.70

Package Height (excluding balls) 1.16

1.26

1.36

Width between Balls

1.27

Package Height above board

0.65

0.70

0.75

Width of package between balls

7.62

Length of package between balls

20.32

Variance of Ball Height

0.15

Bottom View

Top View

Side View

Rev: 1.01a 2/2003

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Ordering Information for GSI Synchronous Burst RAMs

Org

Part Number

Type

Package

Speed

(MHz)

Status

256K x 36

GS88237AB-250

S/DCD Pipeline

BGA

250

256K x 36

GS88237AB-225

S/DCD Pipeline

BGA

225

256K x 36

GS88237AB-200

S/DCD Pipeline

BGA

200

256K x 36

GS88237AB-166

S/DCD Pipeline

BGA

166

256K x 36

GS88237AB-150

S/DCD Pipeline

BGA

150

256K x 36

GS88237AB-133

S/DCD Pipeline

BGA

133

256K x 36

GS88237AB-250I

S/DCD Pipeline

BGA

250

256K x 36

GS88237AB-225I

S/DCD Pipeline

BGA

225

256K x 36

GS88237AB-200I

S/DCD Pipeline

BGA

200

256K x 36

GS88237AB-166I

S/DCD Pipeline

BGA

166

256K x 36

GS88237AB-150I

S/DCD Pipeline

BGA

150

256K x 36

GS88237AB-133I

S/DCD Pipeline

BGA

133

Notes:
1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS88237AB-150IB.
2. T

= C = Commercial Temperature Range. T

= I = Industrial Temperature Range.

3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

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