S7030/S7031 series is a family of FFT-CCD image sensors specifically designed for low-light-level detection in scientific applications. By using
the binning operation, S7030/S7031 series can be used as a linear image sensor having a long aperture in the direction of the device length. This
makes S7030/S7031 series ideally suited for use in spectrophotometry. The binning operation offers significant improvement in S/N and signal
processing speed compared with conventional methods by which signals are digitally added by an external circuit. S7030/S7031 series also
features low noise and low dark signal (MPP mode operation). This enables low-light-level detection and long integration time, thus achieving a
wide dynamic range.
S7030/S7031 series has an effective pixel size of 24 24 m and is available in image areas ranging from 12.288 (H) 1.392(V) mm
2
(512 58
pixels) up to a large image area of 24.576 (H) 6.000 (V) mm
2
(1024 250 pixels).
Features
l Non-cooled type: S7030 series
One-stage TE-cooled type: S7031 series
l Pixel size: 24 24 m
l Line, pixel binning
l Greater than 90 % quantum efficiency at peak sensitivity
wavelength
l Wide spectral response range
l Low readout noise
l Wide dynamic range
l MPP operation
l High UV sensitivity with good stability
Applications
l Fluorescence spectrometer, ICP
l Raman spectrometer
l Industrial inspection requiring
l Semiconductor inspection
l DNA sequencer
l Low-light-level detection
I M A G E S E N S O R
CCD area image sensor
Back-thinned FFT-CCD
S7030/S7031 series
I General ratings
Parameter
Specification
Pixel size
24 (H) 24 (V) m
Vertical clock phase
2 phases
Horizontal clock phase
2 phases
Output circuit
One-stage MOSFET source follower
Package
24 pin ceramic DIP (refer to dimensional outlines)
Window
Quartz glass *
1
*1: Window-less and AR-coated sapphire glass are available upon request.
I Selection guide
Type No.
Cooling
Number of total
pixels
Number of active
pixels
Active area
[mm (H) mm (V)]
Suitable
multichannel
detector head
S7030-0906
532 64
512 58
12.288 1.392
S7030-0907
532 128
512 122
12.288 2.928
S7030-0908
532 256
512 250
12.288 6.000
S7030-1006
1044 64
1024 58
24.576 1.392
S7030-1007
1044 128
1024 122
24.576 2.928
S7030-1008
Non-cooled
1044 256
1024 250
24.576 6.000
C7040
S7031-0906
532 64
512 58
12.288 1.392
S7031-0907
532 128
512 122
12.288 2.928
S7031-0908
532 256
512 250
12.288 6.000
S7031-1006
1044 64
1024 58
24.576 1.392
S7031-1007
1044 128
1024 122
24.576 2.928
S7031-1008
One-stage
TE-cooled
1044 256
1024 250
24.576 6.000
C7041
1
CCD area image sensor
S7030/S7031 series
I Absolute maximum ratings (Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating temperature
Topr
-50
-
+30
C
Storage temperature
Tstg
-50
-
+70
C
OD voltage
V
OD
-0.5
-
+25
V
RD voltage
V
RD
-0.5
-
+18
V
ISV voltage
V
ISV
-0.5
-
+18
V
ISH voltage
V
ISH
-0.5
-
+18
V
IGV voltage
V
IG1V
, V
IG2V
-10
-
+15
V
IGH voltage
V
IG1H
, V
IG2H
-10
-
+15
V
SG voltage
V
SG
-10
-
+15
V
OG voltage
V
OG
-10
-
+15
V
RG voltage
V
RG
-10
-
+15
V
TG voltage
V
TG
-10
-
+15
V
Vertical clock voltage
V
P1V
, V
P2V
-10
-
+15
V
Horizontal clock voltage
V
P1H
, V
P2H
-10
-
+15
V
I Operating conditions (MPP mode, Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output transistor drain voltage
V
OD
18
20
22
V
Reset drain voltage
V
RD
11.5
12
12.5
V
Output gate voltage
V
OG
1
3
5
V
Substrate voltage
V
SS
-
0
-
V
Test point (vertical input source)
V
ISV
-
V
RD
-
V
Test point (horizontal input source)
V
ISH
-
V
RD
-
V
Test point (vertical input gate)
V
IG1V
, V
IG2V
-8
0
-
V
Test point (horizontal input gate)
V
IG1H
, V
IG2H
-8
0
-
V
High
V
P1VH
, V
P2VH
4
6
8
Vertical shift register
clock voltage
Low
V
P1VL
, V
P2VL
-9
-8
-7
V
High
V
P1HH
, V
P2HH
4
6
8
Horizontal shift register
clock voltage
Low
V
P1HL
, V
P2HL
-9
-8
-7
V
High
V
SGH
4
6
8
Summing gate voltage
Low
V
SGL
-9
-8
-7
V
High
V
RGH
4
6
8
Reset gate voltage
Low
V
RGL
-9
-8
-7
V
High
V
TGH
4
6
8
Transfer gate voltage
Low
V
TGL
-9
-8
-7
V
I Electrical characteristics (Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Signal output frequency
fc
-
-
1
MHz
Vertical shift register capacitance *
2
C
P1V
, C
P2V
-
3,000
-
pF
Horizontal shift register capacitance *
2
C
P1H
, C
P2H
-
120
-
pF
Summing gate capacitance
C
SG
-
7
-
pF
Reset gate capacitance
C
RG
-
7
-
pF
Transfer gate capacitance
C
TG
-
120
-
pF
Charge transfer efficiency *
3
CTE
0.99995
0.99999
-
-
DC output level *
4
Vout
12
15
18
V
Output impedance *
4
Zo
-
3
-
k9
Power consumption *
4
*
5
P
-
15
-
mW
*2: S7030/S7031-1007
*3: Charge transfer efficiency per pixel, measured at half of the full well capacity.
*4: The values depend on the load resistance. (Typical, VOD=20 V, Load resistance=22 k9)
*5: Power consumption of the on-chip amplifier.
2
CCD area image sensor
S7030/S7031 series
0
10
100 200
WAVELENGTH (nm)
TRANSMITTANCE (%)
300 400 500 600 700 800 900 1000 1100 1200
20
30
40
50
60
70
80
90
100
(Typ. Ta=25 C)
QUARTZ WINDOW
AR COATED SAPPHIRE
QUANTUM EFFICIENCY (%)
WAVELENGTH (nm)
(Typ. Ta=25 C)
0
200
400
600
800
1000
1200
10
20
30
40
50
60
70
80
90
100
FRONT-SIDED
FRONT-SIDED
(UV COAT)
BACK-THINNED
G Window material
Type No.
Window material
S7030/S7031
series
Quartz glass *
11
(option: window-less,
AR-coated sapphire glass *
12
)
S7032 series
(two-stage TE-
cooled types)
AR-coated sapphire glass *
12
(option: window-less)
*11: Resin sealing
*12: Hermetic sealing
*10: Spectral response with quartz glass (or AR-coated
sapphire glass) is decreased by the transmittance
I Spectral response (without window)
*10
I Spectral transmittance characteristics
KMPDB0058EA
KMPDB0110EA
I Dark current vs. temperature
3
I Electrical and optical characteristics (Ta=25 C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Saturation output voltage
Vsat
-
Fw Sv
-
V
Vertical
150,000
300,000
-
Full well capacity
Horizontal
Fw
300,000
600,000
-
e
-
CCD node sensitivity
Sv
1.8
2.2
-
V/e
-
25 C
-
4,000
12,000
Dark current *
6
MPP mode
(tentative data)
0 C
DS
-
200
600
e
-
/pixel/
s
Readout noise *
7
Nr
-
8
16
e
-
rms
Line binning
18,750
75,000
-
-
Dynamic range *
8
Area scanning
DR
9,375
37,500
-
-
Photo response non-uniformity *
9
PRNU
-
3
10
%
Spectral response range
l
-
200 to 1100
-
nm
*6: Dark current nearly doubles for every 5 to7C increase in temperature.
*7: Operating frequency is 150 kHz.
*8: Dynamic range (DR) = Full well/Readout noise
*9: Measured at the half of the full well capacity output.
Fixed pattern noise (peak to peak)
Signal
100
Photo response non-uniformity (PRNU) [%]
-50
-40
-30
-20
0
-10
10
20
30
TEMPERATURE (C)
0.1
1
10
100
1000
10000
DARK CURRENT (e
-
/pixel/s)
(Typ.)
KMPDB0037EB
CCD area image sensor
S7030/S7031 series
I Device structure
23
22
21
20
14
15
24
1
2
12
11
8
9
3
4
5
2 BEVEL
SIGNAL OUT
2
n
4 BLANK
4 BLANK
V=58, 122, 250
H=512, 1024
4 BEVEL
THINNING
THINNING
1 2 3 4 5
2
3
4
5
V
H
6 BEVEL
6 BEVEL
2
n
SIGNAL OUT
13
10
KMPDC0016EB
INTEGRATION PERIOD
(Shutter must be open)
VERTICAL BINNING PERIOD
(Shutter must be closed)
P1V
P2V, TG
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
3.. 62
3..126
3..254
63
127
255
64
128
256
58 + 6 (BEVEL): S703*-0906/-1006
122 + 6 (BEVEL): S703*-0907/-1007
250 + 6 (BEVEL): S703*-0908/-1008
Tpwv
Tovr
Tpwh, Tpws
Tpwr
1
2
3
531
1043
532
1044
: S703*-0906/-0907/-0908
: S703*-1006/-1007/-1008
4..530
4..1042
1
2
D19
D2
D1
D20
D3..D10, S1..S1024, D11..D18
RG
OS
S1..S512
: S703*-0906/-0907/-0908
: S703*-1006/-1007/-1008
I Timing chart
KMPDC0017EB
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Pulse width
Tpwv
6 *
14
-
-
s
P1V, P2V, TG
Rise and fall time
Tprv, Tpfv
*
13
200
-
-
ns
Pulse width
Tpwh
500
-
-
ns
Rise and fall time
Tprh, Tpfh
10
-
-
ns
P1H, P2H
Duty ratio
-
*
13
-
50
-
%
Pulse width
Tpws
500
-
-
ns
Rise and fall time
Tprs, Tpfs
10
-
-
ns
SG
Duty ratio
-
-
-
50
-
%
Pulse width
Tpwr
100
-
-
ns
RG
Rise and fall time
Tprr, Tpfr
-
5
-
-
ns
TG P1H
Overlap time
Tovr
-
3
-
-
s
*13: Symmetrical pulses should be overlapped at 50 % of maximum amplitude.
*14: In case of S7030/S7031-0908, -1007.
Line bininng
4
CCD area image sensor
S7030/S7031 series
INTEGRATION PERIOD
(Shutter must be open)
P1V
RG
OS
P2V, TG
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
ENLARGED VIEW
4.. 63
4..127
4..255
Tpwv
Tovr
Tpwr
D1
D2
D3
D4
D18
D19
D20
D5..D10, S1..S1024, D11..D17
P2V, TG
P1H
P2H, SG
RG
OS
Tpwh, Tpws
1
2
3
64
58 + 6 (BEVEL): S703 *-0906/-1006
128
122 + 6 (BEVEL): S703 *-0907/-1007
256
250 + 6 (BEVEL): S703 *-0908/-1008
S1..S512
: S703 *-0906/-0907/-0908
: S703 *-1006/-1007/-1008
KMPDC0126EA
INTEGRATION PERIOD
(Shutter must be open)
P1V
RG
OS
P2V, TG
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
ENLARGED VIEW
Tpwv
Tovr
Tpwr
D1
D2
D3
D4
D18
D19
D20
D5..D10, S1..S1024, D11..D17
P2V, TG
P1H
P2H, SG
RG
OS
Tpwh, Tpws
1
2
3
S1..S512
: S703 *-0906/-0907/-0908
: S703 *-1006/-1007/-1008
4.. 63
4..127
4..255
64
58 + 6 (BEVEL): S703 *-0906/-1006
128
122 + 6 (BEVEL): S703 *-0907/-1007
256
250 + 6 (BEVEL): S703 *-0908/-1008
KMPDC0127EA
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Pulse width
Tpwv
6 *
%
-
-
s
P1V, P2V, TG
Rise and fall time
Tprv, Tpfv
*
$
200
-
-
ns
Pulse width
Tpwh
500
-
-
ns
Rise and fall time
Tprh, pfh
10
-
-
ns
P1H, P2H
Duty ratio
-
*
$
-
50
-
%
Pulse width
Tpws
500
-
-
ns
Rise and fall time
Tprs, Tpfs
10
-
-
ns
SG
Duty ratio
-
-
-
50
-
%
Pulse width
Tpwr
100
-
-
ns
RG
Rise and fall time
Tprr, Tpfr
-
5
-
-
ns
TG P1H
Overlap time
Tovr
-
3
-
-
s
*16: Symmetrical pulses should be overlapped at 50 % of maximum amplitude.
*17: In case of S7030/S7031-0908, -1007.
Area scanning 1: low dark current mode
Area scanning 2: large full well mode
5
CCD area image sensor
S7030/S7031 series
WINDOW 16.3
8.2
34.0
50.0
2.54
22.9
19.0
4.0
42.0
22.4
A
7.3
1.0
7.7
6.7
4.8
ACTIVE AREA
12.29
PHOTOSENSITIVE SURFACE
1st PIN INDICATION PAD
3.0
TE-COOLER
S7031-0906: A=1.392
S7031-0907: A=2.928
S7031-0908: A=6.000
(24 ) 0.5
4.4
4.8
2.4
3.8
PHOTOSENSITIVE SURFACE
1st PIN INDICATION PAD
3.0
(24 ) 0.5
WINDOW 16.3
8.2
34.0
2.54
22.9
22.4
A
ACTIVE AREA
12.29
S7030-0906: A=1.392
S7030-0907: A=2.928
S7030-0908: A=6.000
I Dimensional outlines (unit: mm)
S7030-0906/-0907/-0908
S7030-1006/-1007/-1008
KMPDA0046EC
KMPDA0047EC
S7031-0906/-0907/-0908
S7031-1006/-1007/-1008
KMPDA0048EC
KMPDA0049EC
3.0
PHOTOSENSITIVE SURFACE
4.4
2.4
4.8
3.8
WINDOW 28.6
22.9
22.4
ACTIVE AREA 24.58
B
8.2
44.0
2.54
1st PIN INDICATION PAD
S7030-1006: B=1.392
S7030-1007: B=2.928
S7030-1008: B=6.000
(24 ) 0.5
(24 ) 0.5
7.3
1.0
3.0
6.7
4.8
PHOTOSENSITIVE SURFACE
7.7
1st PIN INDICATION PAD
B
4.0
19.0
22.4
22.9
44.0
52.0
60.0
2.54
WINDOW 28.6
ACTIVE AREA 24.58
8.2
S7031-1006: B=1.392
S7031-1007: B=2.928
S7031-1008: B=6.000
TE-COOLER
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Pulse width
Tpwv
6 *
'
-
-
s
P1V, P2V, TG
Rise and fall time
Tprv, Tpfv
*
&
200
-
-
ns
Pulse width
Tpwh
500
-
-
ns
Rise and fall time
Tprh, Tpfh
10
-
-
ns
P1H, P2H
Duty ratio
-
*
&
-
50
-
%
Pulse width
Tpws
500
-
-
ns
Rise and fall time
Tprs, Tpfs
10
-
-
ns
SG
Duty ratio
-
-
-
50
-
%
Pulse width
Tpwr
100
-
-
ns
RG
Rise and fall time
Tprr, Tpfr
-
5
-
-
ns
TG - P1H
Overlap time
Tovr
-
3
-
-
s
*18: Symmetrical pulses should be overlapped at 50 % of maximum amplitude.
*19: In case of S7030/S7031-0908, -1007.
6
CCD area image sensor
S7030/S7031 series
I Pin connections
S7030 series
S7031 series
Pin
No.
Symbol
Function
Symbol
Function
Remark
(standard operation)
1
RD
Reset drain
RD
Reset drain
+12 V
2
OS
Output transistor source
OS
Output transistor source
R
L
=10 k to 100 k9
3
OD
Output transistor drain
OD
Output transistor drain
+20 V
4
OG
Output gate
OG
Output gate
+3 V
5
SG
Summing gate
SG
Summing gate
Same pulse as P2H
6
-
-
7
-
-
8
P2H
CCD horizontal register clock-2
P2H
CCD horizontal register clock-2
9
P1H
CCD horizontal register clock-1
P1H
CCD horizontal register clock-1
10
IG2H
Test point (horizontal input gate-2)
IG2H
Test point (horizontal input gate-2)
0 V
11
IG1H
Test point (horizontal input gate-1)
IG1H
Test point (horizontal input gate-1)
0 V
12
ISH
Test point (horizontal input source)
ISH
Test point (horizontal input source)
Connect to RD
13
TG *
Transfer gate
TG *
Transfer gate
Same pulse as P2V
14
P2V
CCD vertical register clock-2
P2V
CCD vertical register clock-2
15
P1V
CCD vertical register clock-1
P1V
CCD vertical register clock-1
16
-
Th1
Thermistor
17
-
Th2
Thermistor
18
-
P-
TE-cooler-
19
-
P+
TE-cooler+
20
SS
Substrate (GND)
SS
Substrate (GND)
GND
21
ISV
Test point (vertical input source)
ISV
Test point (vertical input source)
Connect to RD
22
IG2V
Test point (vertical input gate-2)
IG2V
Test point (vertical input gate-2)
0 V
23
IG1V
Test point (vertical input gate-1)
IG1V
Test point (vertical input gate-1)
0 V
24
RG
Reset gate
RG
Reset gate
*20: Isolation gate between vertical register and horizontal register. In standard operation, TG should be applied the same pulse as
P2V.
I Specifications of built-in TE-cooler (Typ.)
Parameter
Symbol
Condition
S7031-0906/-0907/-0908
S7031-1006/-1007/-1008
Unit
Internal resistance
Rint
Ta=25 C
2.5
1.2
9
Maximum current *
Imax Tc *
=Th *
!
=25 C
1.5
3.0
A
Maximum voltage
Vmax Tc *
=Th *
!
=25 C
3.8
3.6
V
Maximum heat absorption*
"
Qmax
3.4
5.1
W
Maximum temperature
of heat radiating side
-
70
70
C
*21: Maximum current Imax:
If the current greater than this value flows into the thermoelectric cooler, the heat absorption begins to decrease due to the
Joule heat. It should be noted that this value is not the damage threshold value. To protect the thermoelectric cooler and
maintain stable operation, the supply current should be less than 60 % of this maximum current.
*22: Temperature of the cooling side of thermoelectric cooler.
*23: Temperature of the heat radiating side of thermoelectric cooler.
*24: Maximum heat absorption Qmax.
This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler when the
maximum current is supplied to the unit.
0
1
2
3
V
O
L
T
A
GE (V)
CCD TEMPERA
TURE
(
C)
4
7
6
5
-40
-30
4
3
2
CURRENT (A)
1
0
-20
-10
0
10
20
30
(Typ. Ta=25 C)
VOLTAGE vs. CURRENT
CCD TEMPERATURE vs. CURRENT
0
1
2
3
V
O
L
T
A
GE (V)
CCD TEMPERA
TURE
(
C)
4
7
6
5
-40
-30
2.0
1.5
1.0
CURRENT (A)
0.5
0
-20
-10
0
10
20
30
(Typ. Ta=25 C)
VOLTAGE vs. CURRENT
CCD TEMPERATURE vs. CURRENT
KMPDB0178EA
KMPDB0179EA
S7031-0906/-0907/-0908
S7031-1006/-1007/-1008
7
CCD area image sensor
S7030/S7031 series
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, http://www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658
France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvgen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions.
Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. 2003 Hamamatsu Photonics K.K.
Input
Symbol
Value
Supply voltage
V
D1
V
A1+
V
A1-
V
A2
V
D2
Vp
V
F
+5 Vdc, 200 mA
+15 Vdc, +100 mA
-15 Vdc, -100 mA
+24 Vdc, 30 mA
+5 Vdc, 30 mA (C7041)
+5 Vdc, 2.5 A (C7041)
+12 Vdc, 100 mA (C7041)
Master start
fms
HCMOS logic compatible
Master clock
fmc
HCMOS logic compatible,
1 MHz
Features
l C7040: for S7030 series
C7041: for S7031 series
l Area scanning or full line-binnng operation
l Readout frequency: 250 kHz
l Readout noise: 20 e-rms
l T=50 C (T changes by cooling method.)
Cat. No. KMPD1023E09
Feb. 2003 DN
Multichannel detector heads C7040, C7041
I Precaution for use (Electrostatic countermeasures)
G Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with
an earth ring, in order to prevent electrostatic damage due to electrical charges from friction.
G Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge.
G Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to
discharge.
G Ground the tools used to handle these sensors, such as tweezers and soldering irons.
It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the
amount of damage that occurs.
I Element cooling/heating temperature incline rate
Element cooling/heating temperature incline rate should be set at less than 5 K/min.
I Specifications of built-in temperature sensor
A chip thermistor is built in the same package with a CCD chip, and the CCD chip temperature can be monitored with it. A relation
between the thermistor resistance and absolute temperature is expressed by the following equation.
R1 = R2 expB (1 / T1 - 1 / T2)
where R1 is the resistance at absolute temperature T1 (K)
R2 is the resistance at absolute temperature T2 (K)
B is so-called the B constant (K)
The characteristics of the thermistor used are as follows.
R (298K) = 10 kW
B (298K / 323K) = 3450 K
KMPDB0111EA
(Typ. Ta=25 C)
10 k
220
240
260
TEMPERATURE (K)
RESIST
ANCE
280
300
100 k
1 M
8
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