S7963, S7964 and S7965 are a family of FFT-CCD image sensors with small active area and feature low noise and low dark current (MPP mode
operation). This enables low-light-level detection and long integration time, thus achieving a wide dynamic range. Binning operation and/or
summing operation offers significant improvement in S/N. Due to the low noise amprifier on a CCD chip, a combination of full binning and full
summing operation makes CCD as a very low noise photodiode.
S7963 has an effective pixel size of 24 24 m and is available in image areas of 1.536 (H) 1.536 (V) mm
2
. S7965 has relatively large image
area of 5.184 (H) 1.152 (V) mm
2
.
Two-stage TE-cooler is built into the package for thermoelectric cooling. At room temperature operation, the device can be cooled down to -20 C
without using any other cooling technique. In addition, since both the CCD chip and the TE-cooler are hermetically sealed, no dry air is required,
thus allowing easy handling.
Features
l Small area
l Pixel size: 24 24 m
l Line, pixel binning
l Two-stage TE-cooled
l Line, pixel binning
l Greater than 90 % quantum efficiency
l Low readout noise
l MPP operation
l Low price
Applications
l Low-light-level detection
l Small area, high-speed imaging
l UV detection
l Industrial inspection
I M A G E S E N S O R
CCD area image sensor
Small area, back-thinned FFT-CCD
S7963, S7964, S7965
I Selection guide
Type No.
Cooling
Number of total pixels
Number of active pixels
Active area
[mm (H) mm (V)]
S7963
80 72
64 64
1.536 1.536
S7964
124 56
108 48
2.592 1.152
S7965
Two-stage TE cooled
232 56
216 48
5.184 1.152
I General ratings
Parameter
Specification
Pixel size
24 (H) 24 (V) m
Vertical clock phase
2 phase
Horizontal clock phase
2 phase
Output circuit
One-stage MOSFET source follower
Package
16-pin metal package
Cooling
Two-stage TE-cooler
Window
Hermetically sealed quartz
1
CCD area image sensor
S7963, S7964, S7965
I Absolute maximum ratings
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating temperature
Topr
-50
-
+30
C
Storage temperature
Tstg
-50
-
+70
C
OD voltage
V
OD
-0.5
-
+25
V
RD voltage
V
RD
-0.5
-
+18
V
SG voltage
V
SG
-10
-
+15
V
OG voltage
V
OG
-10
-
+15
V
RG voltage
V
RG
-10
-
+15
V
All vertical clock
V
P1V
, V
P2V
-10
-
+15
V
All horizontal clock
V
P1H
, V
P2H
-10
-
+15
V
Note) All voltage are respect to the SS terminal.
I Operating conditions (MPP mode)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output transistor drain voltage
V
OD
18
20
22
V
Reset drain voltage
V
RD
11.5
12
12.5
V
Output gate voltage
V
OG
1
3
5
V
Substrate voltage
Vss
-
0
-
V
High
V
P1VH
, V
P2VH
4
6
8
Vertical shift register clock voltage
Low
V
P1VL
, V
P2VL
-9
-8
-7
V
High
V
P1HH
, V
P2HH
4
6
8
Horizontal shift register clock voltage
Low
V
P1HL
, V
P2HL
-9
-8
-7
V
High
V
SGH
4
6
8
Summing gate voltage
Low
V
SGL
-9
-8
-7
V
High
V
RGH
4
6
8
Reset gate voltage
Low
V
RGL
-9
-8
-7
V
I Electrical characteristics (Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Signal output frequency
fc
-
80 k
1 M
Hz
Reset clock frequency
frg
-
80 k
1 M
Hz
Vertical shift register capacitance (S7965)
C
P1V
, C
P2V
-
300
-
pF
Horizontal shift register capacitance (S7965)
C
P1H
, C
P2H
-
100
-
pF
Summing gate capacitance
C
SG
-
7
-
pF
Reset gate capacitance
C
RG
-
7
-
pF
Charge transfer efficiency *
1
CTE
0.99995
0.99999
-
-
DC output level *
2
Vout
12
15
18
V
Output impedance *
2
Zo
-
3 k
-
W
Power consumption *
2,
*
3
P
-
15
-
mW
*1: Charge transfer efficiency per pixel, measured at half of the full well capacity.
*2: V
OD
=20 V, Load resistance=22 kW
*3: Power consumption of the on chip amplifier.
I Electrical and optical characteristics (Ta =0 C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Saturation output voltage
Vsat
Fw Sv
V
Vertical
150
300
-
Full well capacity
Horizontal (Summing)
Fw
1,500
3,000
-
ke
-
CCD node sensitivity
Sv
-
0.6
-
V / e
-
25 C
-
4,000
12,000
Dark current *
4
(MPP mode)
0 C
DS
-
200
600
e
-
/pixel/s
Readout noise *
5
Nr
-
30 (TBD)
60
e
-
rms
Area scanning
2,500
10,000
-
Dynamic range
Line binning
DR
25,000
100,000
-
-
Photo response non-uniformity *
6
PRNU
-
3
10
%
Spectral response range *
7
l
-
200 to 1100
-
nm
*4: Dark current nearly doubles for every 5 to 7 C increase in temperature.
*5: -40 C, Readout frequency is 80 kHz.
*6: Measured at the half of the full well capacity output.
*7: No window material below 200 nm
2
CCD area image sensor
S7963, S7964, S7965
I Spectral response (without window)
KMPDB0058EA
QUANTUM EFFICIENCY (%)
WAVELENGTH (nm)
(Typ. Ta=25 C)
0
200
400
600
800
1000
1200
10
20
30
40
50
60
70
80
90
100
FRONT-SIDED
FRONT-SIDED
(UV COAT)
BACK-THINNED
I Dark current vs. temperature
KMPDB0037EB
-50
-40
-30
-20
0
-10
10
20
30
TEMPERATURE (C)
0.1
1
10
100
1000
10000
DARK CURRENT (e
-
/pixel/s)
(Typ.)
I Device structure
KMPDC0134EA
ACTIVE PIXEL
TOTAL PIXEL
4 BLANK
4 BLANK
THINNING
THINNING
BEVEL
BEVEL ACTIVE PIXEL
N
M
1 2 3 4
2
3
4
4 BEVEL
4 BEVEL
P1H
SG
OG
OS
RD
RG
OD
P2H
5
6
2
14
4
1
12
3
TOTAL PIXEL
P2V
10
P1V
11
SS
13
3
CCD area image sensor
S7963, S7964, S7965
INTEGRATION PERIOD
(Shutter must be open)
P1V
RG
OS
P2V
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
ENLARGED VIEW
Tpwv
Tovr
Tpwr
P2V
P1H
P2H, SG
RG
OS
Tpwh, Tpws
I Timing chart
Area scanning 1 (low dark current mode)
Parameter
Symbol
Min.
Typ.
Max
Unit
Pulse width
Tpwv
1
-
-
s
P1V, P2V
Rise and fall time
Tprv, Tpfv
50
-
-
ns
Pulse width
Tpwh
500
-
-
ns
Rise and fall time
Tprh, Tpfh
10
-
-
ns
P1H, P2H
Duty ratio
-
-
50
-
%
Pulse width
Tpws
500
-
-
ns
Rise and fall time
Tprs, Tpfs
10
-
-
ns
SG
Duty ratio
-
-
50
-
%
Pulse width
Tpwr
100
-
-
ns
RG
Rise and fall time
Tprr, Tpfr
5
-
-
ns
P2V - P1H
Overlap time
Tovr
3
-
-
s
4
KMPDC0131EA
CCD area image sensor
S7963, S7964, S7965
KMPDC0132EA
Area scanning 2 (large full well mode)
Parameter
Symbol
Min.
Typ.
Max
Unit
Pulse width
Tpwv
1
-
-
s
P1V, P2V
Rise time, fall time
Tprv, Tpfv
50
-
-
ns
Pulse width
Tpwh
500
-
-
ns
Rise and fall time
Tprh, Tpfh
10
-
-
ns
P1H, P2H
Duty ratio
-
-
50
-
%
Pulse width
Tpws
500
-
-
ns
Rise and fall time
Tprs, Tpfs
10
-
-
ns
SG
Duty ratio
-
-
50
-
%
Pulse width
Tpwr
100
-
-
ns
RG
Rise and fall time
Tprr, Tpfr
5
-
-
ns
P2V - P1H
Overlap time
Tovr
3
-
-
s
INTEGRATION PERIOD
(Shutter must be open)
P1V
RG
OS
P2V
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
ENLARGED VIEW
Tpwv
Tovr
Tpwr
P2V
P1H
P2H, SG
RG
OS
Tpwh, Tpws
5
CCD area image sensor
S7963, S7964, S7965
Parameter
Symbol
Min.
Typ.
Max
Unit
Pulse width
Tpwv
1
-
-
s
P1V, P2V
Rise and fall time
Tprv, Tpfv
50
-
-
ns
Pulse width
Tpwh
500
-
-
ns
Rise and fall time
Tprh, Tpfh
10
-
-
ns
P1H, P2H
Duty ratio
-
-
50
-
%
Pulse width
Tpws
500
-
-
ns
Rise and fall time
Tprs, Tpfs
10
-
-
ns
SG
Duty ratio
-
-
50
-
%
Pulse width
Tpwr
100
-
-
ns
RG
Rise and fall time
Tprr, Tpfr
5
-
-
ns
P2V - P1H
Overlap time
Tovr
3
-
-
s
INTEGRATION PERIOD
INTEGRATION PERIOD
P1V
P2H
SG
READOUT PERIOD
VERTICAL BINNING PERIOD
Tpwv
Tovr
P2V
P1H
RG
Vos
Tpwh, Tpws
Tpwr
KMPDC0133EA
Line binning
6
CCD area image sensor
S7963, S7964, S7965
26.0
12
2.0
5.5
23.0
18.0
3.8
1.2
WINDOW
7.0
WINDOW
7.0
2.54
3.2
7.62
12.7
17.0
PIN No.16
PIN No.1
(16 ) 0.45
PHOTOSENSITIVE
SURFACE
4.7
10.5
10.8
6.3
KMPDA0134EC
I Dimensional outline (unit: mm)
I Pin connection
Pin No.
Symbol
Function
Remark
1
RG
Reset gate
+6/-8 V
2
OS
Output transistor source
Output
3
OD
Output transistor drain
+20 V
4
SG
Summing gate
same pulse as P2H
5
P2H
CCD horizontal register clock-2
+6/-8 V
6
P1H
CCD horizontal register clock-1
+6/-8 V
7
P-
TE-cooler (-)
8
P+
TE-cooler (+)
9
NC
10
P2V
CCD vertical register clock-2
+6/-8 V
11
P1V
CCD vertical register clock-1
+6/-8 V
12
RD
Reset drain
+12 V
13
SS
Substrate
GND
14
OG
Output gate
+3 V
15
Th1
Thermister
16
Th2
Thermister
I Specifications of built-in TE-cooler
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Internal resistance
Rint
Ta=27 C
-
3.0
-
9
Maximum current *
&
Imax
Th *
'
=27 C
,T *
=,Tmax
-
-
1.3
A
Maximum voltage
Vmax
Th*
'
=27 C
,T=,Tmax
I=Imax
-
-
3.5
V
Maximum heat absorption *
Qmax
Tc *
=Th *
'
=27 C
I=Imax
-
-
1.4
W
Maximum temperature at hot side
-
-
-
50
C
CCD temperature
-
Ta=25 C
-
-20
-
C
*8: If the current is greater than Imax, the heat absorption begins to decrease due to the Joule heat. It should be noted that this
value is not a damage threshold. To protect the thermoelectric cooler and maintain stable operation, the supply current
should be less than 60 % of this maximum current.
*9: Temperature at hot side of thermoelectric cooler.
*10: ,T=Th - Tc
*11: This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler element when
the maximum current is supplied to the unit.
*12: Temperature at cool side of thermoelectric cooler.
7
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, http://www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658
France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvgen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions.
Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. 2003 Hamamatsu Photonics K.K.
Cat. No. KMPD1051E0
5
Feb. 2003 DN
CCD area image sensor
S7963, S7964, S7965
I Specifications of built-in temperature sensor
A chip thermistor is built in the same package with a CCD chip, and the CCD chip temperature can be monitored with it. A relation
between the thermistor resistance and absolute temperature is expressed by the following equation.
R1 = R2 expB (1 / T1 1 / T2)
where R1 is the resistance at absolute temperature T1 (K)
R2 is the resistance at absolute temperature T2 (K)
B is so-called the B constant (K)
The characteristics of the thermistor used are as follows.
R (298 K)=10 kW
B (298 K / 323 K)=3450 K.
I Specifications of built-in TE-cooler (TBD)
KMPDB0181EB
(Typ. Ta=25 C)
10 k
220
240
260
TEMPERATURE (K)
RESIST
ANCE
280
300
100 k
1 M
KMPDB0111EA
I Precaution for use (electrostatic countermeasures)
G Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with
an earth ring, in order to prevent electrostatic damage due to electrical charges from friction.
G Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge.
G Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to
discharge.
G Ground the tools used to handle these sensors, such as tweezers and soldering irons.
It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the
amount of damage that occurs.
I Element cooling/heating temperature incline rate
Element cooling/heating temperature incline rate should be set at less than 5 K/min.
8
0
0
CURRENT (A)
VOLTAGE (V)
CCD TEMPERATURE (
C)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
(Typ. Th *=25 C)
0.5
1.5
2.5
1.0
2.0
3.0
-30
-10
10
-20
0
30
20
VOLTAGE - CURRENT
CCD TEMPERATURE -
CURRENT
* Temperature at hot side of TE-cooler
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