S7986-01 and S7987-01 are a family of FT-CCD area image sensors specifically designed for high speed operation. A high frame rate is attained
by employing a wide band width on-chip amplifier. In area scan operation, S7986-01 and S7987-01 can be used as a high frame rate camera, and
2/3-inch NTSC B/W TV correspondence. S7986-01 and S7987-01 also feature low dark signal (MPP mode operation). S7986-01 and S7987-01
have an effective pixel size of 14 14 m and is available in image areas of 9.212 (H) 6.860 (V) mm.
One-stage peltier cooler is built into the package for thermoelectric cooling (S7987-01). At room temperature operation, the device can be cooled
down to -10 C (Typ.) without using any other cooling technique. In addition, since both the CCD chip and the peltier cooler are hermetically
sealed, no dry air is required, thus allowing easy handling.
Features
Applications
I M A G E S E N S O R
CCD area image sensor
Back-thinned FT-CCD for low-light-level NTSC B/W TV application
S7986-01, S7987-01
I Selection and order guide
Type No.
Cooling
Number of
total pixels
Number of
active pixels
Active area
[mm (H) mm (V)]
S7986-01
Non-cooled
S7987-01
One-stage TE-cooled
680 500
658 490
9.212 6.860
I General ratings
Parameter
Specification
CCD structure
Frame transfer (2/3-inch NTSC B/W TV correspondence)
Fill factor
100 %
Number of active pixels
658 (H) 490 (V)
Pixel size
14 (H) 14 (V) m
Active area
9.212 (H) 6.860 (V) mm
Vertical clock phase
2 phase
Horizontal clock phase
2 phase
Output circuit
Two-stage MOSFET source follower
Package
24 pin ceramic package
Window
Sapphire glass
Temporary window are available upon request
G High-speed on-chip amplifier
(14 MHz, 2/3-inch NTSC B/W TV correspondence)
G Greater than 90 % quantum efficiency
G Wide spectrum range
G Built-in TE-cooler
G MPP operation
G Non-cooled types: S7986-01
One-stage TE-cooled types: S7987-01
(Two-stage TE-cooled types are optional)
G High-speed UV imaging
G Semiconductor inspection
G Microscope
1
CCD area image sensor
S7986-01, S7987-01
I Absolute maximum ratings (Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating temperature
Topr
-50
-
+30
C
Storage temperature
Tstg
-50
-
+70
C
OD voltage
V
OD
-0.5
-
+25
V
RD voltage
V
RD
-0.5
-
+18
V
ISV voltage
V
ISV
-0.5
-
+18
V
ISH voltage
V
ISH
-0.5
-
+18
V
IGV voltage
V
IG1V
, V
IG2V
-10
-
+15
V
IGH voltage
V
IG1H
, V
IG2H
-10
-
+15
V
SG voltage
V
SG
-10
-
+15
V
OG voltage
V
OG
-10
-
+15
V
RG voltage
V
RG
-10
-
+15
V
TG voltage
V
TG
-10
-
+15
V
Vertical clock voltage (image area)
V
P1VI
, V
P2VI
-10
-
+15
V
Vertical clock voltage (storage area)
V
P1VS
, V
P2VS
-10
-
+15
V
Horizontal clock voltage
V
P1H
, V
P2H
-10
-
+15
V
I Operating conditions (MPP mode, Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output transistor drain voltage
V
OD
12
15
18
V
Reset drain voltage
V
RD
11.5
12
12.5
V
Output gate voltage
V
OG
1
3
5
V
Substrate voltage
V
SS
-
0
-
V
Test point (vertical input source)
V
ISV
-
V
RD
-
V
Test point (horizontal input source)
V
ISH
-
V
RD
-
V
Test point (vertical input gate)
V
IG1V
, V
IG2V
-8
0
-
V
Test point (horizontal input gate)
V
IG1H
, V
IG2H
-8
0
-
V
High
V
P1VIH
, V
P2VIH
4
6
8
Vertical shift register
clock voltage (Image area)
Low
V
P1VIL
, V
P2VIL
-9
-8
-7
V
High
V
P1VSH
, V
P2VSH
4
6
8
Vertical shift register
clock voltage (Storage area)
Low
V
P1VSL
, V
P2VSL
-9
-8
-7
V
High
V
P1HH
, V
P2HH
4
6
8
Horizontal shift register
clock voltage
Low
V
P1HL
, V
P2HL
-9
-8
-7
V
High
V
SGH
4
6
8
Summing gate voltage
Low
V
SGL
-9
-8
-7
V
High
V
RGH
4
6
8
Reset gate voltage
Low
V
RGL
-9
-8
-7
V
High
V
TGH
4
6
8
Transfer gate voltage
Low
V
TGL
-9
-8
-7
V
I Electrical characteristics (Ta=25 C)
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Signal output frequency
fc
-
-
1
14
MHz
Reset clock frequency
frg
-
-
1
14
MHz
Vertical shift register capacitance
(Image area)
C
P1VI
C
P2VI
-
-
3,000 (TBD)
-
pF
Vertical shift register capacitance
(Storage area)
C
P1VS
C
P2VS
-
-
3,000 (TBD)
-
pF
Horizontal shift register capacitance
C
P1H
, C
P2H
-
-
100 (TBD)
-
pF
Summing gate capacitance
C
SG
-
-
7
-
pF
Reset gate capacitance
C
RG
-
-
7
-
pF
Transfer gate capacitance
C
TG
-
-
50 (TBD)
-
pF
Transfer efficiency
CTE
*
1
0.99995
0.99999
-
-
DC output level
Vout
*
2
-
8 (TBD)
-
V
Output impedance
Zo
*
2
-
500 (TBD)
-
W
Power dissipation
P
*
2,
*
3
-
60 (TBD)
-
mW
*1: Charge transfer efficiency per pixel, measured at half of the full well capacity.
*2: V
OD
=15 V, Load resistance=2.2 kW
*3: Power dissipation of the on-chip amplifier.
2
CCD area image sensor
S7986-01, S7987-01
I Electrical and optical characteristics (Ta=25 C, unless otherwise noted)
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Saturation output voltage
Vsat
-
-
Fw Sv
-
V
Vertical
30
65
-
Full well capacity
Horizontal
Fw
-
60
130
-
ke-
CCD node sensitivity
Sv
*
4
1.5
2.0
-
V/e-
25 C
-
2,000
6,000
Dark current
(MPP mode)
0 C
DS
*
5
-
100
300
e-/pixel/s
Readout noise
Nr
*
6
-
150
300
e-rms
Dynamic range (area scanning)
DR
*
7
100
430
-
-
Spectral response range
l
-
-
200 to 1,100
-
nm
Photo response non-uniformity
PRNU
*
8
-
-
+/-10
%
*4: V
OD
=15 V, Load resistance=2.2 kW
*5: Dark current doubles for every 5 to 7 C.
*6: -40 C, operating frequency is 12 MHz.
*7: DR = Fw / Nr
*8: Measured at half of the full well capacity.
PRNU (%) = noise / signal 100
Noise: fixed pattern noise (peak to peak)
I Pin connections
S7986-01
S7987-01
Pin
No.
Symbol
Description
Symbol
Description
Remark
1
RD
Reset drain
RD
Reset drain
2
OS
Output transistor source
OS
Output transistor source
3
OD
Output transistor drain
OD
Output transistor drain
4
OG
Output gate
OG
Output gate
5
SG
Summing gate
SG
Summing gate
Same timing as P2H
6
NC
NC
7
NC
NC
8
P2H
CCD horizontal register clock-2
P2H
CCD horizontal register clock-2
9
P1H
CCD horizontal register clock-1
P1H
CCD horizontal register clock-1
10
IG2H
Test point (horizontal input gate-2)
IG2H
Test point (horizontal input gate-2)
Shorted to 0 V
11
IG1H
Test point (horizontal input gate-1)
IG1H
Test point (horizontal input gate-1)
Shorted to 0 V
12
ISH
Test point (horizontal input source)
ISH
Test point (horizontal input source)
Shorted to RD
13
TG
Transfer gate
TG
Transfer gate
Same timing as P2VS
*9
14
P2VS CCD vertical register clock-2
(storage area)
P2VS CCD vertical register clock-2
(storage area)
15
P1VS CCD vertical register clock-1
(storage area)
P1VS CCD vertical register clock-1
(storage area)
16
NC
Th1
Thermistor
17
NC
Th2
Thermistor
18
NC
P-
TE-cooler-
19
NC
P+
TE-cooler+
20
SS
Substrate (GND)
SS
Substrate (GND)
21
P2VI
CCD vertical register clock-2
(image area)
P2VI
CCD vertical register clock-2
(image area)
22
P1VI
CCD vertical register clock-1
(image area)
P1VI
CCD vertical register clock-1
(image area)
23
NC
NC
24
RG
Reset gate
RG
Reset gate
*9: TG is an isolation gate between vertical register and horizontal resister.
In standard operation, the same pulse of P2VS should be applied to the TG.
3
CCD area image sensor
S7986-01, S7987-01
QUANTUM EFFICIENCY (%)
WAVELENGTH (nm)
(Typ. Ta=25 C)
0
200
400
600
800
1000
1200
10
20
30
40
50
60
70
80
90
100
FRONT-SIDED
FRONT-SIDED
(UV COAT)
BACK-THINNED
KMPDB0058EA
I Spectral response without window
0
10
100
200
WAVELENGTH (nm)
TRANSMITTANCE (%)
300
400
500
600
700
800
900 1000
20
30
40
50
60
70
80
90
100
(Typ. Ta=25 C)
QUARTZ WINDOW
SAPPHIRE WINDOW
KMPDB0101EA
KMPDA0104EA
I Dimensional outlines (unit: mm)
3.0
PHOTOSENSITIVE SURFACE
4.0
2.4
4.8
3.4
WINDOW 12.0
22.9
22.4
ACTIVE AREA 6.860
9.212
12.0
44.0
2.54
1st PIN INDEX MARK
(24 ) 0.5
1 2
24 23
INDEX MARK
(24 ) 0.5
6.9
1.0
3.0
6.3
4.8
PHOTOSENSITIVE SURFACE
7.7
1st PIN INDEX MARK
9.212
4.0
19.0
22.4
22.9
44.0
52.0
60.0
2.54
WINDOW 12.0
ACTIVE AREA 6.860
12.0
1 2
24 23
INDEX MARK
KMPDA0103EA
I Spectral transmittance characteristic
of window material
S7986-01
S7987-01
4
CCD area image sensor
S7986-01, S7987-01
KMPDC0099EA
I Timing chart for "2 line binning TV rate operation"
P2VI
P2VS
P1H
P2H
RG
Vos
P1H
P2H, SG
RG
Vos
SHUTTER CLOSE (VERTICAL TRANSFER)
SHUTTER OPEN
EXPANDED VIEW
DARK SIGNAL
PHOTO GENERATED SIGNAL
D1
D3
D2
P2VS
g
g
HORIZONTAL TRANSFER
KMPDC0098EA
I Device structure
10 BEVEL
490 IMAGE
500 STORAGE
4 BLANK
THINNING
THINNING
1 2 3 4 5
...
...
...
2
3
4
5
490
658
22 BEVEL
658 SIGNAL OUT
13
14
21
22
20
15
12
11
10
9
8
5
4
2
1
24
3
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Pulse width
Tpwv
1
-
-
s
P1VI, P2VI, P1VS, P2VS, TG
Rise and fall time
Tprv, Tpfv
*
20
-
-
ns
Pulse width
Tpwh
35
-
-
ns
Rise and fall time
Tprh, Tpfh
10
-
-
ns
P1H, P2H
Duty ratio
-
*
-
50
-
%
Pulse width
Tpws
35
-
-
ns
Rise and fall time
Tprs, Tpfs
10
-
-
ns
SG
Duty ratio
-
-
-
50
-
%
Pulse width
Tpwr
15
-
-
ns
RG
Rise and fall time
Tprr, Tpfr
-
5
-
-
ns
TG - P1H
Overlap time
Tovr
-
3
-
-
s
*10: Symmetrical pulses should be overlapped at 50 % of maximum amplitude.
5
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