HANBit HDD16M64F8
URL : www.hbe.co.kr 1 HANBit Electronics Co.,Ltd.
REV 1.0(August.2002)
GENERAL DESCRIPTION
The HDD16M64F8 is a 32M x 64 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module.
The module consists of eight CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K
EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed
circuit board in parallel for each DDR SDRAM. The HSD16M64F8L is a SMM(Stackable Memory Module
type) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on
both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to
be useful for a variety of high bandwidth, high performance memory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
Part Identification
HDD16M64F8
10A : 100MHz (CL=2)
HDD16M64F8
13A : 133MHz (CL=2)
HDD16M64F8
13B : 133MHz (CL=2.5)
128MB(16Mx64) Unbuffered DDR SMM based on 16Mx8 DDR SDRSM
2.5V
0.2V VDD and VDDQ power supply
Auto & self refresh capability (4096 Cycles/64ms)
All input and output are compatible with SSTL_2 interface
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
MRS cycle with address key programs
- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Data scramble : Sequential & Interleave
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
The used device is 4M x 8bit x 4Banks DDR SDRAM
DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks,
4K Ref., SMM, Part No. HDD16M64F8
HANBit HDD16M64F8
URL : www.hbe.co.kr 2 HANBit Electronics Co.,Ltd.
REV 1.0(August.2002)
PIN ASSIGNMENT
P1
P2
PIN
Symbol
PIN
Symbo
l
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
1
/CS0
35
DQ15
69
NC
1
VDDQ
35
DQ17
69
NC(DQS8)
2
NC(/CS1)
36
DQ14
70
DQS1
2
A3
36
DQ18
70
DQS3
3
VSS
37
VDDQ
71
DQS5
3
VSS
37
VDDQ
71
DQS6
4
CKE0
38
DQ13
72
VDD
4
A2
38
DQ19
72
VDD
5
NC(CKE1)
39
DQ12
73
NC
5
A1
39
DQ20
73
DQ56
6
NC
40
DQ11
74
DQ39
6
A0
40
DQ21
74
DQ57
7
VDD
41
VSS
75
DQ38
7
VDD
41
VSS
75
DQ58
8
CK0
42
DQ10
76
VSS
8
A10
42
DQ22
76
VSS
9
CK1
43
DQ9
77
DQ37
9
A11
43
DQ23
77
DQ59
10
NC
44
DQ8
78
DQ36
10
BA0
44
NC(CB6)
78
DQ60
11
VSS
45
VDD
79
VDDQ
11
VSS
45
VDD
79
VDDQ
12
NC
46
*SA0
80
DQ35
12
BA1
46
NC(CB4)
80
DQ61
13
DM0
47
*SA1
81
DQ34
13
DM2
47
NC(CB2)
81
DQ62
14
DM4
48
VSS
82
DQ33
14
DM6
48
VSS
82
DQ63
15
VDDQ
49
*SA2
83
VSS
15
VDDQ
49
NC(CB0)
83
VSS
16
NC
50
VDDQ
84
DQ32
16
NC
50
VDDQ
84
DQ55
17
NC
51
VDD
85
DQ40
17
NC
51
VDD
85
DQ54
18
VSS
52
/RAS
86
DQ41
18
VSS
52
A4
86
DQ53
19
NC
53
VSS
87
VDDQ
19
DQS7
53
VSS
87
VDDQ
20
DQS0
54
/CAS
88
DQ42
20
DQS2
54
A5
88
DQ52
21
DQS4
55
/CK0
89
DQ43
21
NC
55
A6
89
DQ51
22
VDD
56
/CK1
90
DQ44
22
VDD
56
A7
90
DQ50
23
NC
57
VDD
91
VSS
23
DQ31
57
VDD
91
VSS
24
DQ0
58
/CK2
92
DQ45
24
DQ30
58
A8
92
DQ49
25
DQ1
59
CK2
93
DQ46
25
DQ29
59
A9
93
DQ48
26
VSS
60
/WE
94
DQ47
26
VSS
60
NC(A12)
94
NC(CB7)
27
DQ2
61
VSS
95
*SCL
27
DQ28
61
VSS
95
VDD
28
DQ3
62
NC
96
*WP
28
DQ27
62
DM3
96
NC(CB5)
29
VDDQ
63
DM1
97
*VSPD
29
VDDQ
63
DM7
97
NC(CB3)
30
DQ4
64
DM5
98
VSS
30
DQ26
64
NC(DM8)
98
VSS
31
DQ5
65
VDDQ
99
*SDA
31
DQ25
65
VDDQ
99
NC(CB1)
32
DQ6
66
NC
100
VDDIN
32
DQ24
66
NC
100
VDD
33
VSS
67
VREF
33
VSS
67
NC(A13)
34
DQ7
68
VSS
34
DQ16
68
VSS
* These pins should be NC in the system which does not support SPD
PIN
PIN DESCRIPTION
PIN
PIN DESCRIPTION
A0~A11
Address input
VDD
Power supply(2.5V)
BA0~BA1
Bank Select Address
VDDQ
Power supply for DQs(2.5V)
DQ0~DQ63
Data input/output
VREF
Power supply for reference
CB0~CB7
Check bit(Data input/output)
VSPD
Serial EEPROM Power supply(3.3)
DQS0~DQS7
Data Strobe input/output
VSS
Ground
DM0~DM7
Data-in Mask
SA0~SA2
Address in EEPROM
CK0~CK2,/CK0~/CK2
Clock input
SDA
Serial data I/O
CKE0
Clock enable input
SCL
Serial clock
/CS0
Chip Select input
WP
Write protection
/RAS
Row Address strobe
VDDIN
VDD indentification flag
/CAS
Column Address strobe
NC
No connection
HANBit HDD16M64F8
URL : www.hbe.co.kr 3 HANBit Electronics Co.,Ltd.
REV 1.0(August.2002)
FUNCTIONAL BLOCK DIAGRAM
U1
U2
U3
U4
U5
U6
U8
U9
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
HANBit HDD16M64F8
URL : www.hbe.co.kr 4 HANBit Electronics Co.,Ltd.
REV 1.0(August.2002)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CK, /CK
Clock
CK and CK are differential clock inputs. All address and control input signals are
sam-pled on the positive edge of CK and negative edge of CK. Output (read) data
is referenced to both edges of CK. Internal clock signals are derived from CK/CK.
CKE
Clock Enable
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides
PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions
except for disabling outputs, which is achieved asynchronously. Input buffers,
excluding CK, CK and CKE are disabled during power-down and self refresh
modes, providing low standby power. CKE will recognizean LVCMOS LOW level
prior to VREF being stable on power-up.
/CS
Chip Select
CS enables(registered LOW) and disables(registered HIGH) the command
decoder.
All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the
command code.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
command is being applied.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
/CAS
Column
address
strobe
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
/WE
Write enable
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
DQS0 ~ 7
Data Strobe
Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data.
DM0~7
Input Data Mask
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. DM pins include dummy loading internally, to matches the
DQ and DQS load-ing.
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
WP
Write Protection
WP pin is connected to Vcc.
When WP is
"
high
"
, EEPROM Programming will be inhibited and the entire
memory will be write-protected.
VDDQ
Supply
DQ Power Supply : +2.5V
0.2V.
VDD
Supply
Power Supply : +2.5V
0.2V (device specific).
VSS
Supply
DQ Ground.
VREF
Supply
SSTL_2 reference voltage.
HANBit HDD16M64F8
URL : www.hbe.co.kr 5 HANBit Electronics Co.,Ltd.
REV 1.0(August.2002)
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNTE
Voltage on any pin relative to Vss
V
IN
, V
OUT
-o.5 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DD
-1.0 ~ 3.6
V
Voltage on V
DDQ
supply relative to Vss
V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
8.0
W
Short circuit current
I
OS
50
mA
Notes: Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70
C) )
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Supply Voltage
V
DD
2.3
2.7
V
I/O Supply Voltage
V
DDQ
2.3
2.7
V
I/O Reference Voltage
V
REF
1.15
1.35
V
1
I/O Termination Voltage(system)
V
TT
V
REF
0.04
V
REF
+ 0.04
V
2
Input High Voltage
V
IH
(DC)
V
REF
+ 0.15
V
REF
+ 0.3
V
Input Low Voltage
V
IL
(DC)
-0.3
V
REF
- 0.15
V
Input Voltage Level, CK and /CK inputs
V
IN
(DC)
-0.3
V
DDQ
+ 0.3
V
Input Differential Voltage, CK and /CK inputs
V
ID
(DC)
0.3
V
DDQ
+ 0.6
V
Input leakage current
I
LI
-2
2
uA
3
Output leakage current
I
OZ
-5
5
uA
Output High current (V
OUT
= 1.95V)
I
OH
-16.8
mA
Output Low current (V
OUT
= 0.35V)
I
OL
16.8
mA
Notes :
1.Typically, the value of V
REF
is expected to be about 0.5* V
DD
of the transmitting device.
V
REF
is expected to track variation in V
DDQ .
2.Peak to peak AC noise on V
REF
may not exceed
2% V
REF
(DC).
3.V
TT
of the transmitting device must track V
REF
of the receiving device.
CAPACITANCE
(V
DD
= min to max, V
DDQ
= 2.5V
to 2.7V, T
A
= 25
C, f = 100MHz)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input capacitance(A0~A11, BA0~BA1, /RAS, /CAS,/WE)
C
IN1
49
57
pF
Input capacitance(CKE0)
C
IN2
42
50
pF
Input capacitance(/CS0)
C
IN3
42
50
pF
Input capacitance(CLK0, CLK1,CLK2)
C
IN4
22
25
pF
Input capacitance(DM0~DM7)
C
IN5
6
8
pF
Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7)
C
OUT1
6
8
pF
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