HANBit HDD32M64F8

URL : www.hbe.co.kr 1 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)

GENERAL DESCRIPTION

The HANBiT HDD32M64F8 is 32M bit x 64 Double Data Rate SDRAM high density memory modules. The HANBiT

HDD32M64F8 consists of eight CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages mounted on a 200pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The HDD32M64F8 is Dual In-line Memory Modules and inten-ded for mounting into
200pin edge connector sockets.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on

both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be
useful for a variety of high bandwidth, high performance memory system applications.

FEATURES

Part Identification

HDD32M64F8

10A : 100MHz (CL=2)

HDD32M64F8

13A : 133MHz (CL=2)

HDD32M64F8

13B : 133MHz (CL=2.5)

Power supply : V

: 2.5V

0.2V, V

DDQ

: 2.5V

0.2V

Double-data-rate architecture; two data transfers per clock cycle

Bidirectional data strobe(DQS)

Differential clock inputs(CK and CK)

DLL aligns DQ and DQS transition with CK transition

Programmable Read latency 2, 2.5 (clock)

Programmable Burst length (2, 4, 8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

Serial presence detect with EEPROM

DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks,
8K Ref., SMM, Part No. HDD32M64F8

HANBit HDD32M64F8

URL : www.hbe.co.kr 2 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)

PIN ASSIGNMENT

PIN

Symbol

PIN

Symbol

PIN

Symbol

PIN

Symbol

PIN

Symbol

PIN

Symbol

/CS0

DQ15

VDDQ

DQ17

NC(DQS8)

DQ14

DQS1

DQ18

DQS3

VSS

VDDQ

DQS5

VSS

VDDQ

DQS6

CKE0

DQ13

VDD

DQ19

VDD

DQ12

DQ20

DQ56

DQ11

DQ39

DQ21

DQ57

VDD

VSS

DQ38

VDD

VSS

DQ58

CK0

DQ10

VSS

A10

DQ22

VSS

CK1

DQ9

DQ37

A11

DQ23

DQ59

DQ8

DQ36

BA0

NC(CB6)

DQ60

VSS

VDD

VDDQ

VSS

VDD

VDDQ

*SA0

DQ35

BA1

NC(CB4)

DQ61

DM0

*SA1

DQ34

DM2

NC(CB2)

DQ62

DM4

VSS

DQ33

DM6

VSS

DQ63

VDDQ

*SA2

VSS

VDDQ

NC(CB0)

VSS

VDDQ

DQ32

VDDQ

DQ55

VDD

DQ40

VDD

DQ54

VSS

/RAS

DQ41

VSS

DQ53

VSS

VDDQ

DQS7

VSS

VDDQ

DQS0

/CAS

DQ42

DQS2

DQ52

DQS4

/CK0

DQ43

DQ51

VDD

/CK1

DQ44

VDD

DQ50

VDD

VSS

DQ31

VDD

VSS

DQ0

/CK2

DQ45

DQ30

DQ49

DQ1

CK2

DQ46

DQ29

DQ48

VSS

/WE

DQ47

VSS

A12

NC(CB7)

DQ2

VSS

*SCL

DQ28

VSS

VDD

DQ3

*WP

DQ27

DM3

NC(CB5)

VDDQ

DM1

*VSPD

VDDQ

DM7

NC(CB3)

DQ4

DM5

VSS

DQ26

NC(DM8)

VSS

DQ5

VDDQ

*SDA

DQ25

VDDQ

NC(CB1)

DQ6

100

VDDIN

DQ24

100

VDD

VSS

VREF

VSS

NC(A13)

DQ7

VSS

DQ16

VSS

* These pins should be NC in the system which does not support SPD

PIN

PIN DESCRIPTION

PIN

PIN DESCRIPTION

A0~A12

Address input

VDD

Power supply(2.5V)

BA0~BA1

Bank Select Address

VDDQ

Power supply for DQs(2.5V)

DQ0~DQ63

Data input/output

VREF

Power supply for reference

CB0~CB7

Check bit(Data input/output)

VSPD

Serial EEPROM Power supply(3.3)

DQS0~DQS7

Data Strobe input/output

VSS

Ground

DM0~DM7

Data-in Mask

SA0~SA2

Address in EEPROM

CK0~CK2,/CK0~/CK2

Clock input

SDA

Serial data I/O

CKE0

Clock enable input

SCL

Serial clock

/CS0

Chip Select input

Write protection

/RAS

Row Address strobe

VDDIN

VDD indentification flag

/CAS

Column Address strobe

No connection

HANBit HDD32M64F8

URL : www.hbe.co.kr 4 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CK, /CK

Clock

CK and /CK are differential clock inputs. All address and control input signals are

sampled on the positive edge of CK and negative edge of CK. Output (read) data

is referenced to both edges of CK. Internal clock signals are derived from CK/CK.

CKE

Clock Enable

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Deactivating the clock provides

PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE

POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions

except for disabling outputs, which is achieved asynchronously. Input buffers,

excluding CK, CK and CKE are disabled during power-down and self refresh

modes, providing low standby power. CKE will recognizean LVCMOS LOW level

prior to VREF being stable on power-up.

/CS

Chip Select

/CS enables(registered LOW) and disables(registered HIGH) the command

decoder.

All commands are masked when /CS is registered HIGH. /CS provides for external

bank selection on systems with multiple banks. /CS is considered part of the

command code.

A0 ~ A12

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA9

BA0 ~ BA1 Bank select address

BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE

command is being applied.

/RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with /RAS low.

Enables row access & precharge.

/CAS

Columnaddress strobe

Latches column addresses on the positive going edge of the CLK with /CAS low.

Enables column access.

/WE

Write enable

Enables write operation and row precharge.

Latches data in starting from /CAS, /WE active.

DQS0 ~ 7

Data Strobe

Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

DM0~7

Input Data Mask

DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. DM pins include dummy loading internally, to matches the

DQ and DQS load-ing.

DQ0 ~ 63

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Write Protection

WP pin is connected to Vcc.

When WP is

high

, EEPROM Programming will be inhibited and the entire

memory will be write-protected.

VDDQ

Supply

DQ Power Supply : +2.5V

0.2V.

VDD

Supply

Power Supply : +2.5V

0.2V (device specific).

VSS

Supply

DQ Ground.

VREF

Supply

SSTL_2 reference voltage.

HANBit HDD32M64F8

URL : www.hbe.co.kr 5 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

RATING

UNTE

Voltage on any pin relative to Vss

, V

OUT

-0.5 ~ 3.6

Voltage on V

supply relative to Vss

-1.0 ~ 3.6

Voltage on V

DDQ

supply relative to Vss

DDQ

-0.5 ~ 3.6

Storage temperature

STG

-55 ~ +150

Power dissipation

8.0

Short circuit current

Notes:

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS

(Recommended operating conditions (Voltage referenced to Vss = 0V, T

= 0 to 70

C) )

PARAMETER

SYMBOL

MIN

MAX

UNIT

NOTE

Supply Voltage

2.3

2.7

I/O Supply Voltage

DDQ

2.3

2.7

I/O Reference Voltage

REF

DDQ

/2-50mV

DDQ

/2+50mV

I/O Termination Voltage(system)

REF

0.04

REF

+ 0.04

Input High Voltage

(DC)

REF

+ 0.15

REF

+ 0.3

Input Low Voltage

(DC)

-0.3

REF

- 0.15

Input Voltage Level, CK and /CK inputs

(DC)

-0.3

DDQ

+ 0.3

Input Differential Voltage, CK and /CK inputs

(DC)

0.3

DDQ

+ 0.6

Input leakage current

-2

Output leakage current

-5

Output High current (V

OUT

= 1.95V)

-16.8

Output Low current (V

OUT

= 0.35V)

16.8

Output High Current(Half strengh driver)

-9

Output High Current(Half strengh driver)

Notes
1. Includes

25mV margin for DC offset on

REF

, and a combined total of

50mV margin for all AC noise and DC offset on

REF

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on

REF

and internal DRAM noise coupled

REF

, both of which may result in

REF

noise.

REF

should be de-coupled with an inductance of

3nH.

2. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to

REF

, and must track variations in the DC level of

REF

3. V

is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a

REF

envelop that has been bandwidth limited to 200MHZ.

5. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

HANBit HDD32M64F8

URL : www.hbe.co.kr 6 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)

INPUT/OUTPUT CAPACITANCE

= 2.5V, V

DDQ

= 2.5V, T

= 25

C, f = 1MHz)

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Input Capacitance(A0

~ A12, BA0

~ BA1,RAS,CAS, WE )

IN1

Input Capacitance(CKE0)

IN2

Input Capacitance( CS0)

IN3

Input Capacitance( CLK0, CLK

,CLK

)

IN4

Data & DQS input/output Capacitance(DQ0~DQ63)

OUT1

Input Capacitance(DM0~DM8)

IN5

AC OPERATING CONDITIONS

PARAMETER/ CONDITION

STMBOL

MIN

MAX

UNIT

NOTE

Input High (Logic 1) Voltage, DQ, DQS and DM signals

(AC)

REF

+ 0.31

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

(AC)

REF

- 0.31

Input Differential Voltage, CK and CK inputs

(AC)

0.7

DDQ

+0.6

Input Crossing Point Voltage, CK and CK inputs

(AC)

0.5*V

DDQ

-0.2

0.5*V

DDQ

+0.2

Note 1. V

is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V

is expected to equal 0.5* V

DDQ

of the transmitting device and must track variations in the DC level of the same.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation.

the AC and DC input specificatims are refation to a V

REF

envelope that has been bandwidth limited 20MHz.

AC OPERATING TEST CONDITIONS

PARAMETER

VALUE

UNIT

NOTE

Input reference voltage for Clock

0.5 * V

DDQ

Input signal maximum peak swing

1.5

Input signal minimum slew rate

0.5

V/ns

Input Levels(V

)

REF

+0.31/V

REF

-0.31

Input timing measurement reference level

REF

Output timing measurement reference level

Output load condition

See Load Circuit

HANBit HDD32M64F8

URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)

AC TIMMING PARAMETERS & SPECIFICATIONS

(THESE AC CHARICTERISTICS WERE TESTED ON THE COMPONENT)

DDR200

DDR266A

DDR266B

-10A

-13A

-13B

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

NOTE

Row cycle time

Refresh row cycle time

RFC

1,2

Row active time

RAS

120K

1,2

/RAS to /CAS delay

RCD

Row precharge time

Row active to Row active delay

RRD

Write recovery time

Last data in to Read command

CDLR

Col. address to Col. address delay

CCD

CL=2.0

7.5

Clock cycle time

CL=2.5

7.5

Clock high level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock low level width

0.45

0.55

0.45

0.55

0.45

0.55

DQS-out access time from CK/CK

DQSCK

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

Output data access time from CK/CK

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

Data strobe edge to ouput data edge

DQSQ

+0.6

+0.5

Read Preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

Read Postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

Data out high impedence time from CK-/CK

HZQ

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

CK to valid DQS-in

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS-in setup time

WPRES

DQS-in hold time

WPREH

0.25

DQS-in falling edge to CK rising-setup time

DSS

0.2

DQS-in falling edge to CK rising hold time

DSH

0.2

DQS-in high level width

DQSH

0.35

DQS-in low level width

DQSL

0.35

DQS-in cycle time

DSC

0.9

1.1

0.9

1.1

0.9

1.1

Address and Control Input setup time

1.1

0.9

Address and Control Input hold time

1.1

0.9

Mode register set cycle time

MRD

DQ & DM setup time to DQS

0.6

0.5

DQ & DM hold time to DQS

0.6

0.5

DQ & DM input pulse width

DIPW

1.75

Power down exit time

PDEX

HANBit HDD32M64F8

URL : www.hbe.co.kr 8 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)

Exit self refresh to write command

XSW

116

Exit self refresh to bank active command

XSA

Exit self refresh to read command

XSR

200

Cycle

Refresh interval time

REF

15.6

Output DQS valid window

0.35

DQS write postamble time

WPST

0.25

Notes :

1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on t

DQSS

3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with t

RCD

satisfied after this command.

5. For registered DIMMs, t

and t

are

45% of the period including both the half period jitter (t

JIT

(HP) ) of the PLL and the half jitter due to

crosstalk (t

JIT

(crosstalk) ) on the DIMM.

6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate

(V/ns)

(ps)

0.5

0.4

+50

0.3

+100

This derating table is used to increase t

in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate

based on the lesser of AC-AC slew rate and DC-DC slew rate.

7. I/O Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate

(V/ns)

(ps)

0.5

0.4

+75

0.3

+150

This derating table is used to increase t

in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate

based on the lesser of AC-AC slew rate and DC-DC slew rate.

8. I/O Setup/Hold Plateau Derating
I/O Input Level

(mV)

(ps)

280

+50

This derating table is used to increase t

in the case where the input level is flat below V

REF

310mV for a duration of up to 2ns.

9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate

(ns/V)

(ps)

0.25

+50

0.5

+100

This derating table is used to increase t

in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate

is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall

Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.

11. For each of the terms, if not already an integer, round to the next highest integer. t

is actual to the system clock cycle time.

HANBit HDD32M64F8

URL : www.hbe.co.kr 9 HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)

COMMAND TRUTH TABLE

(V=VALID, X=DO

T CARE, H=LOGIC HIGH, L=LOGIC LOW)

COMMAND

CKE

n-1

CKE

/CS

/RAS

/CAS

/WE

0,1

A10/

A11

A9~A0

NOTE

Extended MRS

OP code

1,2

Mode register set

OP code

1,2

Auto refresh

Entry

Refresh

Self
refresh Exit

Bank active & Row Addr.

Row address

Auto

precharge

disable

Read &
column
address

Auto

precharge

eable

Column

Address

(A0 ~ A9)

Auto

precharge

disable

Write &
column
address

Auto

precharge

enable

Column

Address

(A0 ~ A9)

4,6

Burst Stop

Bank selection

Precharge

All banks

Entry

Clock suspend or
active power down

Exit

Entry

Precharge power
down mode

Exit

No operation command

Note :

1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

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