HANBit HDD32M64F8K

URL : www.hbe.co.kr 1 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

GENERAL DESCRIPTION

The HDD32M64F8K is a 32M x 64 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module.

The module consists of sixteen CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K
EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed
circuit board in parallel for each DDR SDRAM. The HSD32M64F8K is a SMM(Stackable Memory Module
type) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on
both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to
be useful for a variety of high bandwidth, high performance memory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.

FEATURES

Part Identification

HDD32M64F8K

10A : 100MHz (CL=2)

HDD32M64F8K

13A : 133MHz (CL=2)

HDD32M64F8K

13B : 133MHz (CL=2.5)

256MB(32Mx64) Unbuffered DDR SMM based on 16Mx8 DDR SDRSM

2.5V

0.2V VDD and VDDQ power supply

Auto & self refresh capability (4096 Cycles/64ms)

All input and output are compatible with SSTL_2 interface

Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

MRS cycle with address key programs

- Latency (Access from column address) : 2, 2.5

- Burst length : 2, 4, 8

- Data scramble : Sequential & Interleave

Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

The used device is 4M x 8bit x 4Banks DDR SDRAM

DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks,
4K Ref., SMM, Part No. HDD32M64F8K

HANBit HDD32M64F8K

URL : www.hbe.co.kr 2 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

PIN ASSIGNMENT

PIN

Symbol

PIN

Symbol

PIN

Symbol

PIN

Symbol

PIN

Symbol

PIN

Symbol

/CS0

DQ15

VDDQ

DQ17

NC(DQS8)

/CS1

DQ14

DQS1

DQ18

DQS3

VSS

VDDQ

DQS5

VSS

VDDQ

DQS6

CKE0

DQ13

VDD

DQ19

VDD

CKE1

DQ12

DQ20

DQ56

DQ11

DQ39

DQ21

DQ57

VDD

VSS

DQ38

VDD

VSS

DQ58

CK0

DQ10

VSS

A10

DQ22

VSS

CK1

DQ9

DQ37

A11

DQ23

DQ59

DQ8

DQ36

BA0

NC(CB6)

DQ60

VSS

VDD

VDDQ

VSS

VDD

VDDQ

*SA0

DQ35

BA1

NC(CB4)

DQ61

DM0

*SA1

DQ34

DM2

NC(CB2)

DQ62

DM4

VSS

DQ33

DM6

VSS

DQ63

VDDQ

*SA2

VSS

VDDQ

NC(CB0)

VSS

VDDQ

DQ32

VDDQ

DQ55

VDD

DQ40

VDD

DQ54

VSS

/RAS

DQ41

VSS

DQ53

VSS

VDDQ

DQS7

VSS

VDDQ

DQS0

/CAS

DQ42

DQS2

DQ52

DQS4

/CK0

DQ43

DQ51

VDD

/CK1

DQ44

VDD

DQ50

VDD

VSS

DQ31

VDD

VSS

DQ0

/CK2

DQ45

DQ30

DQ49

DQ1

CK2

DQ46

DQ29

DQ48

VSS

/WE

DQ47

VSS

NC(A12)

NC(CB7)

DQ2

VSS

*SCL

DQ28

VSS

VDD

DQ3

*WP

DQ27

DM3

NC(CB5)

VDDQ

DM1

*VSPD

VDDQ

DM7

NC(CB3)

DQ4

DM5

VSS

DQ26

NC(DM8)

VSS

DQ5

VDDQ

*SDA

DQ25

VDDQ

NC(CB1)

DQ6

100

VDDIN

DQ24

100

VDD

VSS

VREF

VSS

NC(A13)

DQ7

VSS

DQ16

VSS

* These pins should be NC in the system which does not support SPD

PIN

PIN DESCRIPTION

PIN

PIN DESCRIPTION

A0~A11

Address input

VDD

Power supply(2.5V)

BA0~BA1

Bank Select Address

VDDQ

Power supply for DQs(2.5V)

DQ0~DQ63

Data input/output

VREF

Power supply for reference

CB0~CB7

Check bit(Data input/output)

VSPD

Serial EEPROM Power supply(3.3)

DQS0~DQS7

Data Strobe input/output

VSS

Ground

DM0~DM7

Data-in Mask

SA0~SA2

Address in EEPROM

CK0~CK2,/CK0~/CK2

Clock input

SDA

Serial data I/O

CKE0~CKE1

Clock enable input

SCL

Serial clock

/CS0~/CS1

Chip Select input

Write protection

/RAS

Row Address strobe

VDDIN

VDD indentification flag

/CAS

Column Address strobe

No connection

HANBit HDD32M64F8K

URL : www.hbe.co.kr 3 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

U10

U11

U13

U14

U15

U16

U18

U19

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7

Stacking

FUNCTIONAL BLOCK DIAGRAM

HANBit HDD32M64F8K

URL : www.hbe.co.kr 4 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CK, /CK

Clock

CK and CK are differential clock inputs. All address and control input signals are

sam-pled on the positive edge of CK and negative edge of CK. Output (read) data

is referenced to both edges of CK. Internal clock signals are derived from CK/CK.

CKE

Clock Enable

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Deactivating the clock provides

PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE

POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions

except for disabling outputs, which is achieved asynchronously. Input buffers,

excluding CK, CK and CKE are disabled during power-down and self refresh

modes, providing low standby power. CKE will recognizean LVCMOS LOW level

prior to VREF being stable on power-up.

/CS

Chip Select

CS enables(registered LOW) and disables(registered HIGH) the command

decoder.

All commands are masked when CS is registered HIGH. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the

command code.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

BA0 ~ BA1 Bank select address

BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE

command is being applied.

/RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with /RAS low.

Enables row access & precharge.

/CAS

Columnaddress strobe

Latches column addresses on the positive going edge of the CLK with /CAS low.

Enables column access.

/WE

Write enable

Enables write operation and row precharge.

Latches data in starting from /CAS, /WE active.

DQS0 ~ 7

Data Strobe

Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

DM0~7

Input Data Mask

DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. DM pins include dummy loading internally, to matches the

DQ and DQS load-ing.

DQ0 ~ 63

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Write Protection

WP pin is connected to Vcc.

When WP is

high

, EEPROM Programming will be inhibited and the entire

memory will be write-protected.

VDDQ

Supply

DQ Power Supply : +2.5V

0.2V.

VDD

Supply

Power Supply : +2.5V

0.2V (device specific).

VSS

Supply

DQ Ground.

VREF

Supply

SSTL_2 reference voltage.

HANBit HDD32M64F8K

URL : www.hbe.co.kr 5 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

RATING

UNTE

Voltage on any pin relative to Vss

, V

OUT

-o.5 ~ 3.6

Voltage on V

supply relative to Vss

-1.0 ~ 3.6

Voltage on V

DDQ

supply relative to Vss

DDQ

-0.5 ~ 3.6

Storage temperature

STG

-55 ~ +150

Power dissipation

16.0

Short circuit current

Notes: Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS

(Recommended operating conditions (Voltage referenced to Vss = 0V, T

= 0 to 70

C) )

PARAMETER

SYMBOL

MIN

MAX

UNIT

NOTE

Supply Voltage

2.3

2.7

I/O Supply Voltage

DDQ

2.3

2.7

I/O Reference Voltage

REF

1.15

1.35

I/O Termination Voltage(system)

REF

0.04

REF

+ 0.04

Input High Voltage

(DC)

REF

+ 0.15

REF

+ 0.3

Input Low Voltage

(DC)

-0.3

REF

- 0.15

Input Voltage Level, CK and /CK inputs

(DC)

-0.3

DDQ

+ 0.3

Input Differential Voltage, CK and /CK inputs

(DC)

0.3

DDQ

+ 0.6

Input leakage current

-2

Output leakage current

-5

Output High current (V

OUT

= 1.95V)

-16.8

Output Low current (V

OUT

= 0.35V)

16.8

Notes :

1.Typically, the value of V

REF

is expected to be about 0.5* V

of the transmitting device.

REF

is expected to track variation in V

DDQ .

2.Peak to peak AC noise on V

REF

may not exceed

2% V

REF

(DC).

3.V

of the transmitting device must track V

REF

of the receiving device.

CAPACITANCE

= min to max, V

DDQ

= 2.5V

to 2.7V, T

= 25

C, f = 100MHz)

DESCRIPTION

SYMBO

MIN

MAX

UNITS

Input capacitance(A0~A11, BA0~BA1, /RAS, /CAS,/WE)

IN1

107

Input capacitance(CKE0,CKE1)

IN2

Input capacitance(/CS0~/CS1)

IN3

Input capacitance(CLK0, CLK1,CLK2)

IN4

Input capacitance(DM0~DM7)

IN5

Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7)

OUT1

HANBit HDD32M64F8K

URL : www.hbe.co.kr 6 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, V

= 2.5V, T =25

VERSION

NOTE

PARAMETER

SYMBO

TEST

CONDITION

-10A

-13A

-13B

UNIT

Operating current

(One bank active)

DD1

Burst length = 2

(min), CL=2.5

OUT

= 0mA,

Active-Read-Presharge

1520

1600

Precharge standby

current in

power-down mode

DD2P

CKE

(max)

= tCK(min), All banks

idle

Precharge

standby current in

non power-down mode

DD2N

CKE

(min)

/CS

(min), t

= tCK(min)

288

320

Active standby current in

power-down mode

DD3P

All banks idle, CKE

(max), t

= tCK(min)

480

560

Active standby current in

non power-down mode

(One bank active)

DD3N

Onel banks,

Active-Read-Presharge,

RAS

(max),

tCK(min)

720

800

CL=2.

Operating current (Read)

DD4R

Burst length = 2

= t

(min),

OUT

= 0mA,

CL=2

1840

2160

CL=2.

Operating current (Write)

DD4W

Burst length = 2

= t

(min)

CL=2

1840

2240

Auto refresh current

DD5

REF

(min)

2720

2880

Self refresh current

DD6

CKE

0.2V

AC OPERATING CONDITIONS

PARAMETER

STMBOL

MIN

MAX

UNIT

NOTE

Input High (Logic 1) Voltage, DQ, DQS and DM signals

(AC)

VREF + 0.35

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

(AC)

VREF - 0.35

Input Differential Voltage, CK and CK inputs

(AC)

0.7

VDDQ+0.6

Input Crossing Point Voltage, CK and CK inputs

(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

Notes:

1. VID is the magnitude of the difference between the input level on CK and the input on CK.

The value of V

is expected to equal 0.5* V

DDQ

of the transmitting device and must track variations in the DC level

of the same

HANBit HDD32M64F8K

URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

AC OPERATING TEST CONDITIONS

PARAMETER

VALUE

UNIT

NOTE

Input reference voltage for Clock

0.5 * V

DDQ

Input signal maximum peak swing

1.5

Input signal minimum slew rate

1.0

Input Levels(V

)

REF

+0.35/V

REF

Input timing measurement reference level

REF

Output timing measurement reference level

Output load condition

See Load Circuit

AC CHARACTERISTICS

(These AC charicteristics were tested on the Component)

DDR200

DDR266A

DDR266B

-10A

-13A

-13B

PARAMETER

SYMBO

MIN

MAX

MIN

MAX

MIN

MAX

UNIT NOTE

Row cycle time

Refresh row cycle time

RFC

1,2

Row active time

RAS

120K

1,2

/RAS to /CAS delay

RCD

Row precharge time

Row active to Row active delay

RRD

Write recovery time

Last data in to Read command

CDLR

Col. address to Col. address delay

CCD

CL=2.0

7.5

Clock cycle time

CL=2.5

7.5

HANBit HDD32M64F8K

URL : www.hbe.co.kr 8 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

Clock high level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock low level width

0.45

0.55

0.45

0.55

0.45

0.55

DQS-out access time from CK/CK

DQSCK

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

Output data access time from CK/CK

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

Data strobe edge to ouput data edge

DQSQ

+0.6

+0.5

Read Preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

Read Postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

Data out high impedence time from CK-

/CK

HZQ

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

CK to valid DQS-in

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS-in setup time

WPRES

DQS-in hold time

WPREH

0.25

DQS-in falling edge to CK rising-setup

time

DSS

0.2

DQS-in falling edge to CK rising hold

time

DSH

0.2

DQS-in high level width

DQSH

0.35

DQS-in low level width

DQSL

0.35

DQS-in cycle time

DSC

0.9

1.1

0.9

1.1

0.9

1.1

Address and Control Input setup time

1.1

0.9

Address and Control Input hold time

1.1

0.9

Mode register set cycle time

MRD

DQ & DM setup time to DQS

0.6

0.5

DQ & DM hold time to DQS

0.6

0.5

DQ & DM input pulse width

DIPW

1.75

Power down exit time

PDEX

Exit self refresh to write command

XSW

116

Exit self refresh to bank active

command

XSA

Exit self refresh to read command

XSR

200

Cycle

Refresh interval time

REF

15.6

Output DQS valid window

0.35

DQS write postamble time

WPST

0.25

Notes :

1. Maximum burst refresh of 8.
2. t

HZQ

transitions occurs in the same assess time windows as valid data transitions. These parameters are not

referenced to a specific voltage level, but specify when the device output is no longer driving.

3. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going

from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was
in progress, DQS could be High at this time, depending on t

DQSS.

HANBit HDD32M64F8K

URL : www.hbe.co.kr 9 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

SIMPLIFIED TRUTH TABLE

COMMAND

CKE

n-1

CKE

/CS

/WE DM

0,1

A10/

A11

A9~A0

NOTE

Extended MRS

OP code

1,2

Mode register set

OP code

1,2

Auto refresh

Entry

Refresh

Self
refres
h

Exit

Bank active & row addr.

Row address

Auto

precharge

disable

Read &
column
address

Auto

precharge

eable

Column

Address

(A0 ~ A9)

Auto

precharge

disable

Write &
column
address

Auto

precharge

enable

Column

Address

(A0 ~ A9)

4,6

Burst Stop

Bank selection

Precharg
e

All banks

Entry

Clock suspend or
active power down

Exit

Entry

Precharge power
down mode

Exit

No operation command

(V=Valid, X=Don't care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

HANBit HDD32M64F8K

URL : www.hbe.co.kr 10 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t

after the end of burst.

6. Burst stop command is valid at every burst length.

7. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges

(Write DM latency is 0)

PACKAGING INFORMATION

Unit : mm

Front

Side

Rear-Side

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