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Электронный компонент: HMD1M4Z1

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HANBit HMD1M4Z1
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV.1.0(August.2002)
1
PIN ASSIGNMENT

DESCRIPTION
The HMD1M4Z1 is an 1M x 4 bits Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of
memory cells
within the same row. Power supply voltage (+5V ), access time (-5, -6), power consumption(Normal or Low power), and package
type (ZIP) are optional features of this Module. The HMD1M4Z1 have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities.
The HMD1M4Z1 is optimized for application to the systems, which are required high density and large capacity such as main
memory for main frames and mini computers, personal computer and high performance microprocessor systems.
The HMD1M4Z1 provides common data and outputs.
Features
w
Fast Page Mode operation
w
CAS-before-RAS refresh capability
w
RAS-only and Hidden refresh capability
w
Fast parallel test mode capability
w
TTL(5V) compatible inputs and outputs
w
Early write or output enable controlled write
w
Available in 20pin ZIP packages
w
Single +5V
10% power supply
w
1,024 Refresh Cycles/16ms
w
Performance Range
PIN DESCRIPTION
PIN
SYMBOL
1
/OE
2
/CAS
3
DQ2
4
DQ3
5
V
SS
6
DQ0
7
DQ1
8
/WE
9
/RAS
10
A9
11
A0
12
A1
13
A2
14
A3
15
V
CC
16
A4
17
A5
18
A6
19
A7
20
A8
Speed
t
RAC
t
CAC
t
RC
t
PC
HMD1M4Z1-5
50
15
90
35
HMD1M4Z1-6
60
15
110
40
PIN
FUNCTION
PIN
FUNCTION
A0
A9
Address Inputs
/WE
Read/Write
Enable
DQ0
DQ3
Data
Input/Output
Vcc
Power
(+5V)
/RAS
Row Address
Strobe
Vss
Ground
/CAS
Column
Address Strobe
NC
No
Connection
/OE
Data Output
Enable
4Mbit(1Mx4bit) Fast Page Mode, 1K Refresh, 20Pin ZIP, 5V Design
Part No. HMD1M4Z1
HANBit HMD1M4Z1
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV.1.0(August.2002)
2
ABSOLUTE MAXIMUM RATINGS
*
SYMBOL
PARAMETER
RATING
UNIT
TA
Ambient Temperature under Bias
0 ~ 70
C
TSTG
Storage Temperature (Plastic)
-55 ~ 150
C
VIN/VOUT
Voltage on any Pin Relative to Vss
-1.0 ~ 7.0
V
VCC
Power Supply Voltage
-1.0 ~ 7.0
V
IOUT
Short Circuit Output Current
50
mA
PD
Power Dissipation
600
mW
*NOTE: 1. Stress greater than above absolute Maximum Ratings? May cause permanent damage to the device.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 ~ 70C)
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
V
IH
2.4
-
Vcc+1
V
Input Low Voltage
V
IL
-1.0
-
0.8
V
*NOTE: All voltages referenced to Vcc
DC AND OPERATING CHARACTERISTICS
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
OH
Output High Level Voltage (IOUT = -5mA)
2.4
V
V
OL
Output Low Level Voltage (IOUT = 4.2mA)
0
0.4
V
-5
85
I
CC1
Operating Current
(/RAS,/CAS,Address Cycling : tRC = tRC min)
-6
75
mA
I
CC2
Standby Current (/RAS,/CAS = V
IH
)
-
2
mA
-5
85
I
CC3
/RAS Only Refresh Current
(/RAS Cycling, /CAS = V
IH
,: tRC = tRC min)
-6
75
mA
-5
65
I
CC4
Fast Page Mode Current
(/RAS =V
IL
, /CAS, Address Cycling : tPC = tPC min)
-6
55
mA
mA
I
CC5
Standby Current (/RAS,/CAS >= Vcc
0.2V)
1
mA
-5
85
I
CC6
/CAS before /RAS Refresh Current (tRC = tRC min)
-6
75
mA
I
CCS
Self Refresh Current
(/RAS=/UCAS=/LCAS=V
IL,
/WE=/OE=A0~A9= Vcc
0.2V or 0.2V,
DQ0~DQ31= Vcc
0.2V, 0.2V or Open)
-
-
uA
I
I(L)
Input Leakage Current
(Any Input (0V<=V
IN
<= V
IN
+ 0.5V, All Other Pins Not Under Test = 0V)
-5
5
uA
I
O(L)
Output Leakage Current(DOUT is Disabled, 0V<=V
OUT
<= Vcc)
-5
5
uA
HANBit HMD1M4Z1
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV.1.0(August.2002)
3
Note: 1. Icc depends on output load condition when the device is selected.
Icc (max) is specified at the output open condition.
2. Address can be changed once or less while /RAS = V
IL.
3. Address can be changed once or less while /CAS = V
IH
CAPACITANCE
( T
A
=25
o
C, Vcc = 5V+/- 10%, f = 1Mhz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS NOTE
Input Capacitance (A0-A9)
C
I1
-
5
pF 1
Input Capacitance (/WE,/RAS, /CAS0-
/CAS3,/OE)
C
I2
-
7
pF 1,2
Input/Output Capacitance (DQ0-31)
C
DQ1
-
7
pF 1,2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /CAS = VIH to disable DOUT.
AC CHARACTERISTICS
( 0
o
C
T
A
70oC , Vcc = 5V
10%, V
IH
/V
IL
= 2.4/0.8V, V
OH
/V
OL
=2.4/0.4V, See notes 1,2)
-5
-6
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
NOTE
t
RC
Random Read or Write Cycle Time
90
110
ns
t
RWC
Read-modify-writer cycle time
132
152
ns
t
RAC
Access Time from /RAS
50
60
ns
3,4,10
t
CAC
Access Time from /CAS
15
15
ns
3,4,5
t
aa
Access Time from Column Address
25
30
ns
3,10
t
OFF
Output Buffer Turn-off Time
0
12
0
12
ns
6
t
T
Transition Time (Rise and Fall)
3
50
3
50
ns
2
t
RP
/RAS Precharge Time
30
40
ns
t
RAS
/RAS Pulse Width
50
10K
60
10K
ns
t
RSH
/RAS Hold Time
15
15
ns
t
CSH
/CAS Hold Time
50
60
ns
t
CAS
/CAS Pulse Width
15
10K
15
10K
ns
t
RCD
/RAS to /CAS Delay Time
20
35
20
45
ns
4
t
RAD
/RAS to Column Address Delay Time
15
25
15
30
ns
10
t
CRP
/CAS to /RAS Precharge Time
5
5
ns
t
ASR
Row Address Setup Time
0
0
ns
t
RAH
Row Address Hold Time
10
10
ns
t
ASC
Column Address Setup Time
0
0
ns
11
t
CAH
Column Address Hold Time
10
10
ns
11
t
RAL
Column Address to /RAS Lead Time
25
30
ns
t
RCS
Read Command Setup Time
0
0
ns
HANBit HMD1M4Z1
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV.1.0(August.2002)
4
t
RCH
Read Command Hold Time to /CAS
0
0
ns
8
t
RRH
Read Command Hold Time to /RAS
0
0
ns
8
t
WCH
Write Command Hold Time
10
10
ns
t
WP
Write Command Pulse Width
10
10
ns
t
RWL
Write Command to /RAS Lead Time
15
15
ns
t
CWL
Write Command to /CAS Lead Time
13
15
ns
t
DS
Data-in Setup Time
0
0
ns
9
t
DH
Data-in Hold Time
10
10
ns
9
t
REF
Refresh Period (1024 Cycle)
16
16
ms
t
wcs
Write Command Setup Time
0
0
ms
7
t
CWD
/CAS to /WE delay time
37
37
ms
7,13
t
RWD
/RAS to /WE delay time
72
82
ns
7
t
AWD
Column Address to /WE delay time
47
52
ns
7
t
CPWD
/CAS precharge to /WE delay time
52
57
ns
7
t
CSR
/CAS Setup Time
(/CAS-before-/RAS Refresh Cycle)
10
10
ns
15
t
CHR
/CAS Hold Time
(/CAS-before-/RAS Refresh Cycle)
10
10
ns
16
t
RPC
/RAS Precharge to /CAS Hold Time
5
5
ns
t
CPA
Access Time from /CAS Precharge
30
35
ns
3
t
PC
Fast Page Mode Cycle Time
35
40
ns
t
CP
Fast Page Mode /RAS Precharge Time
10
10
ns
12
t
RASP
Fast Page Mode /CAS Pulse Time
50
200K
60
200K
ns
t
RHCP
/RAS Hold Time time from /CAS
Precharge
30
35
ns
t
OEA
/OE Access Time
15
15
ns
3
t
OED
/OE to data delay
12
12
ns
t
OEZ
Output buffer turn off delay time from
/OE
0
12
0
12
ns
t
OEH
/OE command hold time
15
15
ns
t
RASS
/RAS Pulse Width(CBR self refresh)
100
100
us
t
PRS
/RAS Precharge Time(CBR self refresh)
90
110
ns
t
CHS
/CAS Hold Time(CBR self refresh)
-50
-50
ns
Note: 1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only refresh or /CAS-before-/RAS refresh
cycles
before proper device operation is achieved.
2. Input voltage levels are V
IH
/
V
IL.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Also, transition times are measured between
.
V
IH
and V
IL
are assumed to be 5ns for all inputs.
3. Measured with a load circuit equivalent to 2TTL loads and 100pF.
HANBit HMD1M4Z1
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV.1.0(August.2002)
5
4. Operation with the t
RCD
(max) limit insures that t
RAC
(max) can be met, t
RCD
(max) is specified as a reference point only,
if t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
5. Assumes that t
RCD
<= t
RCD
(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
/
V
OL .
7. T
WCS,
T
RWD,
T
CWD,
T
CPWD
are non restrictive operating parameter. They are included in the data sheet as electrical
characteristics
only. If t
wcs
>= t
wcs
(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout
the entire cycle. If t
CWD
>= t
CWD
(min), t
RWD
>= t
RWD
(min), T
CPWD
>= T
CPWD
(min), then the cycle is a read-modify-write
cycle and the data output will contain the data read from the selected address. If neither of the above conditions is
satisfied, the condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycles.
9. These parameters are referenced to /CAS falling edge in early write cycles and to /WE falling edge in /OE controlled
write cycle and read-modify-write cycles.
10. Operation with the t
RAD
(max) limit insures that t
RAC
(max) can be met, t
RAD
(max) is specified as a reference point only,
if t
RAD
is greater than the specified t
RAD
(max) limit, then access time is controlled exclusively by t
AA
.
11. t
ASC,
t
CAH
are are referenced to the earlier /CAS falling edge.
12. t
CP
is specified from the later /CAS rising edge in the previous cycle to the earlier /CAS falling edge in the next cycle.
13. t
CWD
is referenced to the later /CAS falling edge at word read-modify-write cycle.
14. t
CWL
is specified from /WE falling edge to the earlier /CAS rising edge .
15. t
CSR
is referenced to the earlier /CAS falling edge before /RAS transition low.
16. t
CHR
is referenced to the later /CAS rising edge after /RAS transition low.
PACKAGING INFORMATION
HANBit HMD1M4Z1
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV.1.0(August.2002)
6

ORDERING INFORMATION
Part Number
Density
Org.
Package
Component
Number
Vcc
MODE
SPEED
HMD1M4Z1-5
4Mbit
1M x 4Bit
20 Pin-ZIP
1EA
5V
FP
50ns
HMD1M4Z1-6
4Mbit
1M x 4Bit
20 Pin-ZIP
1EA
5V
FP
60ns
1.8
0.30 mm
2.54 mm
97. 80
0. 20
1.94
0.20
1.27
0.20
1.94
0.20