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Электронный компонент: HMD4M32M2VE

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HANBit HMD4M32M2VE
URL:www.hbe.co.kr
H ANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
1

GENERAL DESCRIPTION
The HMD4M32M2VE is a 4M x 32 bit dynamic RAM high-density memory module. The module consists of two CMOS
4M x 16 bit DRAMs in 50-pin TSOP packages mounted on a 72-pin. A 0.1 or 0.22uF decoupling capacitor is mounted on
the printed circuit board for each DRAM components. The module is a single In-line memory module with edge
connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered
from a single 3.3V DC power supply. All inputs and outputs are LVTTL-compatible.
FEATURES
w
Part Identification
HMD4M32M2VE----Lead finish Solder
HMD4M32M2VEG- Lead finish Gold
w
Access times : 50, 60ns
w
High-density 16MByte design
w
4K Cycles/64ms Ref, Gold
w
Single +3.3V
0.3V power supply
w
JEDEC standard pinout
w
EDO Mode operation
w
LVTTL compatible inputs and outputs
w
FR4-PCB design
OPTIONS MARKING
w
Timing
50ns access -5
60ns access -6
w
Packages
72-pin SIMM
M
PERFORMANCE RANGE
Speed
tRAC
tCAC
tRC
5
50ns
13ns
84ns
6
60ns
15ns
104ns
PIN NAMES
Pin Name
Function
Pin Name
Function
Pin Name
Function
A0-A11
Address Input(4K Ref)
/RAS0
Row Address Strobe
Vss
Ground
DQ0-DQ31 Data In/Out
/CAS0 - /CAS3
Column Address Strobe
NC
No Connection
/W
Read/Write Input
PD1 - PD4
Presence Detect
Vcc
Power(+3.3V)
16Mbyte(4Mx32) DRAM SIMM EDO MODE, 4K Refresh, 3.3V
Part No. HMD4M32M2VE, HMD4M32M2VEG
PIN ASSIGNMENT
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
VSS
19
A10
37
NC
55
DQ11
2
DQ0
20
DQ4
38
NC
56
DQ27
3
DQ16
21
DQ20
39
VSS
57
DQ12
4
DQ1
22
DQ5
40
/CAS0
58
DQ28
5
DQ17
23
DQ21
41
/CAS2
59
VCC
6
DQ2
24
DQ6
42
/CAS3
60
DQ29
7
DQ18
25
DQ22
43
/CAS1
61
DQ13
8
DQ3
26
DQ7
44
/RAS0
62
DQ30
9
DQ19
27
DQ23
45
NC
63
DQ14
10
VCC
28
A7
46
NC
64
DQ31
11
NC
29
A11
47
/W
65
DQ15
12
A0
30
VCC
48
NC
66
NC
13
A1
31
A8
49
DQ8
67
PD1
14
A2
32
A9
50
DQ24
68
PD2
15
A3
33
NC
51
DQ9
69
PD3
16
A4
34
NC
52
DQ25
70
PD4
17
A5
35
NC
53
DQ10
71
NC
18
A6
36
NC
54
DQ26
72
VSS
HANBit HMD4M32M2VE
URL:www.hbe.co.kr
H ANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
2
FUNCTIONAL BLOCK DIAGRAM
Toall DRAMs
0.1uF
or
0.22uF
Capacitor
for each DRAM
DQ0-DQ7

DQ8-DQ15






DQ16-DQ23

DQ24-DQ31
/RAS0
/CAS0
/CAS1
/CAS2
/CAS3
/W
A0-A11

/RAS


/LCAS


/UCAS


/OE




/W A0-A11
U0

/RAS


/LCAS


/UCAS


/OE




/W A0-A11
U2
Vcc
Vss
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7



DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7




DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
HANBit HMD4M32M2VE
URL:www.hbe.co.kr
H ANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
Voltage on Any Pin Relative to Vss
V
IN ,OUT
-0.5V to 6.5V
Voltage on Vcc Supply Relative to Vss
Vcc
-0.5V to 4.6V
Power Dissipation
P
D
2W
Storage Temperature
T
STG
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
w
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to V
SS
, TA=0 to 70 o C )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
Supply Voltage
Vcc
3.0
3.3
3.6
V
Ground
Vss
0
0
0
V
Input High Voltage
V
IH
2.0
-
+5.5
V
Input Low Voltage
V
IL
-0.3
-
0.8
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
SPEED
MIN
MAX
UNITS
-5
-
220
mA
I
CC1
-6
-
200
mA
I
CC2
-
4
mA
-5
-
220
mA
I
CC3
-6
-
200
mA
-5
-
220
mA
I
CC4
-6
-
200
mA
I
CC5
-
600
mA
-5
-
220
mA
I
CC6
-6
-
200
mA
I
l(L)
-10
10
A
I
O(L)
-10
10
A
V
OH
2.4
-
V
V
OL
-
0.4
V
I
CC1
: Operating Current * (/RAS , /CAS , Address cycling @t
RC
=min.)
I
CC2
: Standby Current ( /RAS=/CAS=V
IH
)
HANBit HMD4M32M2VE
URL:www.hbe.co.kr
H ANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
4
I
CC3
: /RAS Only Refresh Current * (/CAS=V
IH
, /RAS, Address cycling @t
RC
=min )
I
CC4
: Fast Page Mode Current * (/RAS=V
IL
, /CAS, Address cycling @t
PC
=min )
I
CC5
: Standby Current (/RAS=/CAS=Vcc-0.2V )
I
CC6
: /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t
RC
=min )
* NOTE: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the
output open. I
CC
is specified as an average current. In I
CC1
and I
CC3
, address cad be changed maximum once
while /RAS=V
IL
. In I
CC4
, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( T
A
=25
o
C, Vcc = 3.3V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A11)
C
IN1
-
10
pF
Input Capacitance (/W)
C
IN2
-
14
pF
Input Capacitance (/RAS0, /RAS1)
C
IN3
-
14
pF
Input Capacitance (/CAS0-/CAS3)
C
IN4
-
14
pF
Input/Output Capacitance (DQ0-31)
C
DQ1
-
14
pF
AC CHARACTERISTICS
( 0
o
C
T
A
70oC , Vcc = 3.3V
10%, See notes 1,2.)
-5
-6
STANDARD OPERATION
SYMBOL
MIN
MAX
MIN
MAX
UNIT
Random read or write cycle time
t
RC
84
104
ns
Access time from /RAS
t
RAC
50
60
ns
Access time from /CAS
t
CAC
13
15
ns
Access time from column address
t
AA
25
30
ns
/CAS to output in Low-Z
t
CLZ
3
3
ns
Transition time (rise and fall)
t
T
1
50
1
50
ns
/RAS precharge time
t
RP
30
40
ns
/RAS pulse width
t
RAS
50
10K
60
10K
ns
/RAS hold time
t
RSH
13
15
ns
/CAS hold time
t
CSH
38
45
ns
/CAS pulse width
t
CAS
8
10K
10
10K
ns
/RAS to /CAS delay time
t
RCD
20
37
20
45
ns
/RAS to column address delay time
t
RAD
15
25
15
30
ns
/CAS to /RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
HANBit HMD4M32M2VE
URL:www.hbe.co.kr
H ANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
5
Column address hold time
t
CAH
8
10
ns
Column Address to /RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold referenced to /CAS
t
RCH
0
0
ns
Read command hold referenced to /RAS
t
RRH
0
0
ns
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to /RAS lead time
t
RWL
10
10
ns
Write command to /CAS lead time
t
CWL
8
10
ns
Data-in set-up time
t
DS
0
0
ns
Data-in hold time
t
DH
8
10
ns
Refresh period
t
REF
64
64
ns
Write command set-up time
t
WCS
0
0
ns
/CAS setup time (C-B-R refresh)
t
CSR
5
5
ns
/CAS hold time (C-B-R refresh)
t
CHR
10
10
ns
/RAS precharge to /CAS hold time
t
RPC
5
5
ns
Access time from /CAS precharge
t
CPA
35
40
ns
Fast page mode cycle time
t
PC
28
35
ns
/CAS precharge time (Fast page)
t
CP
8
10
ns
/RAS pulse width (Fast page )
t
RASP
50
100K
60
100K
ns
/W to /RAS precharge time (C-B-R refresh)
t
WRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
t
WRH
10
10
ns
NOTES
1.
An initial pause of 200
s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.
V
IH (min)
and V
IL (max)
are reference levels for measuring timing of input signals. Transition times are measured between
V
IH(min)
and V
IL(max)
and are assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 1TTL loads and 100pF
4.
Operation within the t
RCD(max)
limit insures that t
RAC(max)
can be met. t
RCD(max)
is specified as a reference point only. If t
RCD
is greater than the specified t
RCD(max)
limit, then access time is controlled exclusively by t
CAC
.
5.
Assumes that t
RCD
t
RCD(max)
6. t
AR
, t
WCR
, t
DHR
are referenced to t
RAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
or V
OL
.
8. t
WCS
, t
RWD
, t
CWD
and t
AWD
are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If t
WCS
tWCS(min)
the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
11. Operation within the t
RAD(max)
limit insures that t
RAC(max)
can be met. t
RAD(max)
is specified as a reference
point only. If t
RAD
is greater than the specified t
RAD(max)
limit. then access time is controlled by t
AA
.