HANBit HMD4M32M8EG/8EAG
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV. 1.0(August. 2002)
1
GENERAL DESCRIPTION
The HMD4M32M8E is a 4M x 32 bit dynamic RAM high-density memory module. The module consists of eight CMOS
4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single
In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
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Part Identification
HMD4M32M8EG-- 2048 Cycles/32ms Ref. Gold
HMD4M32M8EAG-- 4096 Cycles/64ms Ref. Gold
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Access times : 50, 60ns
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High-density 16MByte design.
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Single + 5V
0.5V power supply
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JEDEC standard pinout
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EDO(extended data out) mode operation
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TTL compatible inputs and outputs
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FR4-PCB design
OPTIONS MARKING
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Timing
50ns access -5
60ns access -6
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Packages
72-pin SIMM M
PRESENCE DETECT PINS
Pin
50ns
60ns
PD1
Vss
Vss
PD2
NC
NC
PD3
Vss
NC
PD4
Vss
NC
PERFORMANCE RANGE
Speed
tRAC
tCAC
tRC
tHPC
5
50ns
13ns
90ns
26ns
6
60ns
15ns
110ns
30ns
PIN SYMBOL PIN
SYMBOL
PIN
SYMBOL
1
Vss
25
DQ22
49
DQ8
2
DQ0
26
DQ7
50
DQ24
3
DQ16
27
DQ23
51
DQ9
4
DQ1
28
A7
52
DQ25
5
DQ17
29
A11
53
DQ10
6
DQ2
30
Vcc
54
DQ26
7
DQ18
31
A8
55
DQ11
8
DQ3
32
A9
56
DQ27
9
DQ19
33
NC
57
DQ12
10
Vcc
34
/RAS2
58
DQ28
11
NC
35
NC
59
Vcc
12
A0
36
NC
60
DQ29
13
A1
37
NC
61
DQ13
14
A2
38
NC
62
DQ30
15
A3
39
Vss
63
DQ14
16
A4
40
/CAS0
64
DQ31
17
A5
41
/CAS2
65
DQ15
18
A6
42
/CAS3
66
NC
19
A10
43
/CAS1
67
Vss
20
DQ4
44
/RAS0
68
PD2
21
DQ20
45
NC
69
PD3
22
DQ5
46
NC
70
PD4
23
DQ21
47
/WE
71
NC
24
DQ6
48
NC
72
Vss
16Mbyte(4Mx32) 72-pin EDO MODE, 2K/4K Ref. SIMM Design 5V
Part No. HMD4M32M8EG, HMD4M32M8EAG
PIN ASSIGNMENT
A0-A11:Address Input (4K Ref.)
A0-A10:Address Input (2K Ref.)
*Note: A11 is used for only HMD4M32M8EAG
HANBit HMD4M32M8EG/8EAG
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV. 1.0(August. 2002)
2
FUNCTIONAL BLOCK DIAGRAM
DQ0
CAS DQ1
RAS DQ2
OE W A0-A10(A11) DQ3
U1
DQ0
CAS DQ1
RAS DQ2
OE W A0-A10(A11) DQ3
U2
DQ0
CAS DQ1
RAS DQ2
OE W A0-A10(A11) DQ3
U4
DQ0
CAS DQ1
RAS DQ2
OE W A0-A10(A11) DQ3
U5
DQ0
CAS DQ1
RAS DQ2
OE W A0-A10(A11) DQ3
U6
DQ0
CAS DQ1
RAS DQ2
OE W A0-A10(A11) DQ3
U7
DQ0
CAS DQ1
RAS DQ2
OE W A0-A10(A11) DQ3
U8
DQ0
CAS DQ1
RAS DQ2
OE W A0-A10(A11) DQ3
U9
Vcc
Vss
0.1uF or 0.22uF Capacitor
for each DRAM
To all DRAMs
DQ0-DQ3
DQ4-DQ7
DQ8-DQ11
DQ12-DQ15
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
/CAS0
/RAS0
/CAS1
/CAS2
/CAS3
/WE
A0-A10(A11)
/RAS2
HANBit HMD4M32M8EG/8EAG
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV. 1.0(August. 2002)
3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
Voltage on Any Pin Relative to Vss
V
IN ,OUT
-1V to 7.0V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 7.0V
Power Dissipation
P
D
8W
Storage Temperature
T
STG
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
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Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to V
SS
, TA=0 to 70 o C )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
V
IH
2.4
-
Vcc+1
V
Input Low Voltage
V
IL
-1.0
-
0.8
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
SPEED
MIN
MAX
UNITS
-5
-
880
mA
I
CC1
-6
-
800
mA
I
CC2
-
16
mA
-5
-
880
mA
I
CC3
-6
-
800
mA
-5
-
880
mA
I
CC4
-6
-
800
mA
I
CC5
-
8
mA
-5
-
880
mA
I
CC6
-6
-
800
mA
I
l(L)
-40
40
A
I
O(L)
-5
5
A
V
OH
2.4
-
V
V
OL
-
0.4
V
I
CC1
: Operating Current * (/RAS , /CAS , Address cycling @t
RC
=min.)
I
CC2
: Standby Current ( /RAS=/CAS=V
IH
)
I
CC3
: /RAS Only Refresh Current * ( /CAS=V
IH
, /RAS, Address cycling @t
RC
=min )
HANBit HMD4M32M8EG/8EAG
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV. 1.0(August. 2002)
4
I
CC4
: Fast Page Mode Current * (/RAS=V
IL
, /CAS, Address cycling @t
PC
=min )
I
CC5
: Standby Current (/RAS=/CAS=Vcc-0.2V )
I
CC6
: /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t
RC
=min )
I
IL
: Input Leakage Current (Any input 0V
V
IN
6.5V, all other pins not under test = 0V)
I
OL
: Output Leakage Current (Data out is disabled, 0V
V
OUT
5.5V
V
OH
: Output High Voltage Level (I
OH
= -5mA )
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA )
* NOTE: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the
output open. I
CC
is specified as an average current. In I
CC1
and I
CC3
, address cad be changed maximum once
while /RAS=V
IL
. In I
CC4
, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( T
A
=25
o
C, Vcc = 5V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A10)
C
IN1
-
64
pF
Input Capacitance (/WE)
C
IN2
-
70
pF
Input Capacitance (/RAS0,/RAS2)
C
IN3
-
42
pF
Input Capacitance (/CAS0-/CAS3)
C
IN4
-
30
pF
Input/Output Capacitance (DQ0-31)
C
DQ1
-
17
pF
AC CHARACTERISTICS
( 0
o
C
T
A
70oC , Vcc = 5V
10%, See notes 1,2.)
-5
-6
STANDARD OPERATION
SYMBOL
MIN
MAX
MIN
MAX
UNIT
Random read or write cycle time
t
RC
90
110
ns
Access time from /RAS
t
RAC
50
60
ns
Access time from /CAS
t
CAC
13
15
ns
Access time from column address
t
AA
25
30
ns
/CAS to output in Low-Z
t
CLZ
3
3
ns
Output buffer turn-off delay from /CAS
t
CEZ
3
13
3
15
ns
Transition time (rise and fall)
t
T
2
50
2
50
ns
/RAS precharge time
t
RP
30
40
ns
/RAS pulse width
t
RAS
50
10K
60
10K
ns
/RAS hold time
t
RSH
13
15
ns
/CAS hold time
t
CSH
38
45
ns
/CAS pulse width
t
CAS
8
10K
10
10K
ns
/RAS to /CAS delay time
t
RCD
20
37
20
45
ns
/RAS to column address delay time
t
RAD
15
25
15
30
ns
/CAS to /RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
HANBit HMD4M32M8EG/8EAG
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV. 1.0(August. 2002)
5
Column address hold time
t
CAH
8
10
ns
Column address hold referenced to /RAS
t
AR
40
45
ns
Column Address to /RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold referenced to /CAS
t
RCH
0
0
ns
Read command hold referenced to /RAS
t
RRH
0
0
ns
Write command hold time
t
WCH
10
10
ns
Write command hold referenced to /RAS
t
WCR
40
45
ns
Write command pulse width
t
WP
10
10
ns
Write command to /RAS lead time
t
RWL
13
15
ns
Write command to /CAS lead time
t
CWL
8
10
ns
Data-in set-up time
t
DS
0
0
ns
Data-in hold time
t
DH
8
10
ns
Data-in hold referenced to /RAS
t
DHR
40
45
ns
Refresh period
t
REF
32
32
ns
Write command set-up time
t
WCS
0
0
ns
/CAS to /W delay time
t
CWD
36
40
ns
/RAS to /W delay time
t
RWD
73
85
ns
/CAS precharge(C-B-R counter test)
t
CPT
20
20
ns
Column address to /W delay time
t
AWD
48
55
ns
Access time from /CAS precharge
t
CPA
30
35
ns
/CAS precharge time (Hyper Page cycle)
t
CP
8
10
ns
/RAS pulse width (Hyper Page cycle)
t
RASP
50
200K
60
200K
ns
/WE to /RAS precharge time (C-B-R refresh)
t
WRP
10
10
ns
/WE to /RAS hold time (C-B-R refresh)
t
WRH
10
10
ns
NOTES
1.
An initial pause of 200
s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.
V
IH (min)
and V
IL (max)
are reference levels for measuring timing of input signals. Transition times are measured between
V
IH(min)
and V
IL(max)
and are assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 1TTL loads and 100pF
4.
Operation within the t
RCD(max)
limit insures that t
RAC(max)
can be met. t
RCD(max)
is specified as a reference point only. If t
RCD
is greater than the specified t
RCD(max)
limit, then access time is controlled exclusively by t
CAC
.
5.
Assumes that t
RCD
t
RCD(max)
6. t
AR
, t
WCR
, t
DHR
are referenced to t
RAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
or V
OL
.
8. t
WCS
, t
RWD
, t
CWD
and t
AWD
are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If t
WCS
tWCS(min)
the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
11. Operation within the t
RAD(max)
limit insures that t
RAC(max)
can be met. t
RAD(max)
is specified as a reference
point only. If t
RAD
is greater than the specified t
RAD(max)
limit. then access time is controlled by t
AA
.
HANBit HMD4M32M8EG/8EAG
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV. 1.0(August. 2002)
6
0.25 mm MAX
MIN
2.54
mm
1.27
Gold : 1.04
0.10 mm
Solder:0.914
0.10mm
TIMING DIAGRAM
Please refer to attached timing diagram chart (IV)
PACKAGING INFORMATION
SIMM Design
ORDERING INFORMATION
Part Number
Density
Org.
Package
Refresh
Cycle
Vcc
Speed
HMD4M32M8EG-5
16MByte
4MX 32bit
72 Pin-SIMM
2,048 Cycles
32ms Ref.
5.0V
50ns
HMD4M32M8EAG-5
16MByte
4MX 32bit
72 Pin-SIMM
4,096 Cycle
64ms Ref.
5.0V
50ns
HMD4M32M8EG-6
16MByte
4MX 32bit
72 Pin-SIMM
2,048 Cycles
32ms Ref.
5.0V
60ns
HMD4M32M8EAG-6
16MByte
4MX 32bit
72 Pin-SIMM
4,096 Cycle
64ms Ref.
5.0V
60ns
1.27
0.08
mm
1.27 mm
3.34 mm
1
107.95 mm
2.03
mm
1.02 mm
6.35
95.25 mm
6.35
3.18 mm DIA
0.51 mm
101.19 mm
3.38 mm
R 1.57 mm
16.00
6.35 mm
10.16 mm
72
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